A resource access method, device, readable storage medium, and BMC chip

Abstract

The present application discloses a resource access method, device, readable storage medium, and BMC chip in the field of computer technology. The BMC chip provided by the present application can simultaneously carry and run two operating systems, and these two operating systems are used to execute different types of tasks. Among them, the first processor core group in the BMC chip is equipped with a non-real-time operating system, so that the first processor core group accesses non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks; the second processor core group in the BMC chip is equipped with a real-time operating system, so that the second processor core group accesses real-time hardware resources based on the real-time operating system to execute real-time control tasks. This solution can reduce the power consumption of the BMC system and enable the server host to boot up as soon as possible. A resource access device, readable storage medium, and BMC chip provided by the present application also have the above technical effects.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and particularly to a resource access method, device, readable storage medium, and BMC chip. Background Art

[0002] Existing BMC chips can only carry a single operating system. Based on this operating system, various resources on the BMC and its host can be monitored and managed, and the services implemented by this operating system are numerous and complex.

[0003] Among them, the real-time requirements for information such as fan speed and motherboard temperature are relatively high, and the acquisition and monitoring of this information with high real-time requirements will increase the power consumption of the BMC system. In addition, since the single operating system carried by the BMC chip also needs to carry other complex services, its startup is slow, and the server host needs to start after the BMC system starts. Therefore, the single operating system carried by the current BMC chip will delay the startup process of the server host.

[0004] Therefore, how to reduce the power consumption of the BMC system is a problem that those skilled in the art need to solve. Summary of the Invention

[0005] In view of this, the purpose of the present application is to provide a resource access method, device, readable storage medium, and BMC chip to reduce the power consumption of the BMC system. The specific solutions are as follows:

[0006] In a first aspect, the present application provides a resource access method applied to a BMC chip. The BMC chip includes: a first processor core group composed of at least one processor core, a second processor core group composed of at least one processor core, non-real-time hardware resources, and real-time hardware resources;

[0007] Among them, the first processor core group carries a non-real-time operating system, and the first processor core group accesses the non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks;

[0008] The second processor core group carries a real-time operating system, and the second processor core group accesses the real-time hardware resources based on the real-time operating system to execute real-time control tasks;

[0009] Among them, the non-real-time operating system and the real-time operating system run in parallel in the BMC chip.

[0010] Optionally, it further includes:

[0011] After the second processor core group controls the startup of the real-time operating system, the BMC chip triggers the startup process of its own server.

[0012] Optionally, the non-real-time hardware resources include: hardware resources for detecting the host status;

[0013] Accordingly, the first processor core group accesses the hardware resources for detecting the host status based on the non-real-time operating system to detect the operating status of the server to which the BMC chip belongs.

[0014] Optionally, the real-time hardware resources include: hardware resources for monitoring sensor information and / or hardware resources for detecting abnormal information;

[0015] Accordingly, the second processor core group accesses the hardware resources for monitoring sensor information and / or the hardware resources for detecting abnormal information based on the real-time operating system to obtain sensor information and / or abnormal information.

[0016] Optionally, the first processor core group accesses the non-real-time hardware resources based on the non-real-time operating system and the first virtualization configuration;

[0017] Accordingly, the second processor core group accesses the real-time hardware resources based on the real-time operating system and the second virtualization configuration.

[0018] Optionally, the first processor core group modifies the first virtualization configuration based on the non-real-time operating system to change the non-real-time hardware resources accessible to the first processor core group;

[0019] Accordingly, the second processor core group modifies the second virtualization configuration based on the real-time operating system to change the real-time hardware resources accessible to the second processor core group.

[0020] Optionally, the BMC chip further includes: a control bus;

[0021] Accordingly, the first processor core group sends a non-real-time access instruction to the control bus based on the non-real-time operating system, so that the control bus determines the non-real-time hardware resources accessible by the non-real-time access instruction according to the first preset access configuration, and after obtaining the non-real-time access result when accessing the non-real-time hardware resources, returns the non-real-time access result to the first processor core group;

[0022] The second processor core group sends a real-time access instruction to the control bus based on the real-time operating system, so that the control bus determines the real-time hardware resources accessible by the real-time access instruction according to a second preset access configuration, and after obtaining a real-time access result by accessing the real-time hardware resources, returns the real-time access result to the second processor core group.

[0023] In a second aspect, the present application provides an electronic device, including:

[0024] A memory for storing a computer program;

[0025] A processor for executing the computer program to implement the resource access method disclosed above.

[0026] In a third aspect, the present application provides a readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the resource access method disclosed above.

[0027] In a fourth aspect, the present application provides a BMC chip, including: a first processor core group composed of at least one processor core, a second processor core group composed of at least one processor core, non-real-time hardware resources, and real-time hardware resources;

[0028] Wherein, the first processor core group is equipped with a non-real-time operating system; the first processor core group is used for: accessing the non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks; the second processor core group is equipped with a real-time operating system; the second processor core group is used for: accessing the real-time hardware resources based on the real-time operating system to execute real-time control tasks;

[0029] Wherein, the non-real-time operating system and the real-time operating system run in parallel in the BMC chip.

[0030] Optionally, the BMC chip is further used for: after the second processor core group controls the real-time operating system to start, triggering the power-on process of the server to which it belongs.

[0031] Optionally, the non-real-time hardware resources include: hardware resources for detecting the host status;

[0032] Correspondingly, the first processor core group is specifically used for: accessing the hardware resources for detecting the host status based on the non-real-time operating system to detect the operating status of the server to which the BMC chip belongs.

[0033] Optionally, the real-time hardware resources include: hardware resources for monitoring sensor information and / or hardware resources for detecting abnormal information;

[0034] Correspondingly, the second processor core group is specifically configured to: access the hardware resources for monitoring sensor information and / or the hardware resources for detecting abnormal information based on the real-time operating system, so as to obtain sensor information and / or abnormal information.

[0035] Optionally, the first processor core group is specifically configured to: access the non-real-time hardware resources based on the non-real-time operating system and the first virtualization configuration;

[0036] Correspondingly, the second processor core group is specifically configured to: access the real-time hardware resources based on the real-time operating system and the second virtualization configuration.

[0037] Optionally, the first processor core group is specifically configured to: modify the first virtualization configuration based on the non-real-time operating system, so as to change the non-real-time hardware resources accessible to the first processor core group;

[0038] Correspondingly, the second processor core group is specifically configured to: modify the second virtualization configuration based on the real-time operating system, so as to change the real-time hardware resources accessible to the second processor core group.

[0039] Optionally, the BMC chip further includes: a control bus;

[0040] Correspondingly, the first processor core group is specifically configured to: send a non-real-time access instruction to the control bus based on the non-real-time operating system, so that the control bus determines the non-real-time hardware resources accessible by the non-real-time access instruction according to the first preset access configuration, and after obtaining a non-real-time access result when accessing the non-real-time hardware resources, return the non-real-time access result to the first processor core group;

[0041] The second processor core group is specifically configured to: send a real-time access instruction to the control bus based on the real-time operating system, so that the control bus determines the real-time hardware resources accessible by the real-time access instruction according to the second preset access configuration, and after obtaining a real-time access result when accessing the real-time hardware resources, return the real-time access result to the second processor core group.

[0042] As can be seen from the above solution, the present application provides a resource access method, which is applied to a BMC chip. The BMC chip includes: a first processor core group composed of at least one processor core, a second processor core group composed of at least one processor core, non-real-time hardware resources, and real-time hardware resources. Among them, the first processor core group is equipped with a non-real-time operating system, and the first processor core group accesses the non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks. The second processor core group is equipped with a real-time operating system, and the second processor core group accesses the real-time hardware resources based on the real-time operating system to execute real-time control tasks. Among them, the non-real-time operating system and the real-time operating system run in parallel in the BMC chip.

[0043] It can be seen that the BMC chip provided by the present application can simultaneously carry and run two operating systems, and these two operating systems are used to execute different types of tasks. Among them, the first processor core group in the BMC chip is equipped with a non-real-time operating system, so that the first processor core group accesses the non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks. The second processor core group in the BMC chip is equipped with a real-time operating system, so that the second processor core group accesses the real-time hardware resources based on the real-time operating system to execute real-time control tasks. Since the real-time control tasks implemented based on the real-time operating system consume less power and are faster than those implemented based on the non-real-time operating system, the BMC chip can not only quickly complete the real-time control tasks, but also relatively reduce the system power consumption. And it also reduces the burden on the non-real-time operating system. The non-real-time operating system and the real-time operating system run in parallel in the BMC chip, optimizing the overall performance and flexibility of the BMC, which can meet the real-time monitoring and common management requirements under various complex application requirements of the server, and can also make the server host boot up as soon as possible. Because the real-time operating system starts faster than the non-real-time operating system, and after the real-time operating system starts, it can be considered that the BMC system has completed the startup. Therefore, when the real-time operating system starts, the server host can be immediately started.

[0044] Correspondingly, a resource access device, a readable storage medium, and a BMC chip provided by the present application also have the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0046] Figure 1 A flowchart of a resource access method disclosed in this application;

[0047] Figure 2 A schematic diagram of an electronic device disclosed in this application;

[0048] Figure 3 Another schematic diagram of an electronic device disclosed in this application;

[0049] Figure 4 A schematic diagram of a BMC chip disclosed in this application. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0051] Currently, the monitoring and management subsystem (BMC, Board Management Chip) set in the server can monitor the underlying hardware status of the server and also implement remote unified management functions, such as: installation, system update, power on / off, etc. The processor of the BMC is a BMC chip with an independent operating system. This BMC chip can communicate with the server host CPU and can also monitor the hardware interfaces of the server host. The operating system carried by the BMC chip needs to start a large number of services during the startup process, resulting in a slow startup of the operating system.

[0052] Among them, the real-time requirements for information such as fan speed and motherboard temperature are relatively high, and the acquisition and monitoring of this information with relatively high real-time requirements will increase the power consumption of the BMC system. In addition, since the single operating system carried by the BMC chip also needs to carry other complex services, its startup is slow, and the server host needs to start after the BMC system starts. Therefore, the single operating system currently carried by the BMC chip will delay the startup process of the server host. For this reason, this application provides a resource access solution and a BMC chip, which can reduce the power consumption of the BMC system and enable the server host to boot as soon as possible.

[0053] See Figure 1As shown in the figure, an embodiment of the present application discloses a resource access method, which is applied to a BMC chip. The BMC chip includes: a first processor core group composed of at least one processor core, a second processor core group composed of at least one processor core, non-real-time hardware resources, and real-time hardware resources. Among them, different processor cores can be interconnected through a standard AXI (Advanced eXtensible Interface, a bus protocol) or other buses.

[0054] The resource access method provided by the embodiment of the present application is completed by the first processor core group and the second processor core group in the BMC chip, and specifically includes:

[0055] S101. The first processor core group is equipped with a non-real-time operating system, and the first processor core group accesses non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks.

[0056] S102. The second processor core group is equipped with a real-time operating system, and the second processor core group accesses real-time hardware resources based on the real-time operating system to execute real-time control tasks.

[0057] In this embodiment, the non-real-time operating system and the real-time operating system are started and run in parallel in the BMC chip. That is to say, the above two steps have no sequence and can be executed in parallel.

[0058] It should be noted that the real-time operating system starts faster than the non-real-time operating system. After the real-time operating system starts, it can be considered that the BMC system has completed the startup. Therefore, when the real-time operating system starts, the server host can be started immediately. In a specific implementation manner, after the second processor core group controls the startup of the real-time operating system, the BMC chip triggers the startup process of the server to which it belongs, so that the server host can be powered on as soon as possible. Among them, the real-time operating system (Real Time Operating System, RTOS) cuts off complex computer services and functions. When external events or data occur, it can accept and process them at a fast enough speed, and the processing results can be used to control the production process or make a quick response to the processing system within the specified time, scheduling all available resources for real-time tasks, and having the characteristics of timely response and high reliability.

[0059] In a specific embodiment, the non-real-time hardware resources include: hardware resources for detecting the host status; correspondingly, the first processor core group accesses the hardware resources for detecting the host status based on a non-real-time operating system to detect the operating status of the server to which the BMC chip belongs. Of course, the non-real-time hardware resources also include: sensors, registers, etc. that can implement other functions and have low real-time requirements.

[0060] In a specific embodiment, the real-time hardware resources include: hardware resources for monitoring sensor information and / or hardware resources for detecting abnormal information; correspondingly, the second processor core group accesses the hardware resources for monitoring sensor information and / or the hardware resources for detecting abnormal information based on a real-time operating system to obtain sensor information and / or abnormal information. Of course, the real-time hardware resources also include: sensors, registers, etc. that can implement other functions and have high real-time requirements.

[0061] In a specific embodiment, the first processor core group accesses the non-real-time hardware resources based on a non-real-time operating system and a first virtualization configuration; correspondingly, the second processor core group accesses the real-time hardware resources based on a real-time operating system and a second virtualization configuration. Among them, the first virtualization configuration and the second virtualization configuration are implemented based on virtual machine technology. The first virtualization configuration is used to configure the non-real-time hardware resources that the first processor core group can access. The second virtualization configuration is used to configure the real-time hardware resources that the second processor core group can access. Moreover, the first virtualization configuration and the second virtualization configuration support instant changes, and after the changes, the changed first virtualization configuration and the changed second virtualization configuration can be instantaneously applied. In a specific embodiment, the first processor core group modifies the first virtualization configuration based on a non-real-time operating system to change the non-real-time hardware resources that the first processor core group can access; correspondingly, the second processor core group modifies the second virtualization configuration based on a real-time operating system to change the real-time hardware resources that the second processor core group can access.

[0062] In a specific embodiment, the BMC chip further includes: a control bus; correspondingly, the first processor core group sends non-real-time access instructions to the control bus based on a non-real-time operating system, so that the control bus determines the non-real-time hardware resources accessible by the non-real-time access instructions according to a first preset access configuration. After obtaining a non-real-time access result by accessing the non-real-time hardware resources, the non-real-time access result is returned to the first processor core group; the second processor core group sends real-time access instructions to the control bus based on a real-time operating system, so that the control bus determines the real-time hardware resources accessible by the real-time access instructions according to a second preset access configuration. After obtaining a real-time access result by accessing the real-time hardware resources, the real-time access result is returned to the second processor core group. Among them, the first preset access configuration records the identification information of the non-real-time hardware resources that can be accessed by the first processor core group. The identification information of the non-real-time hardware resources is, for example: the number of a certain register. The second preset access configuration records the identification information of the real-time hardware resources that can be accessed by the second processor core group. The identification information of the real-time hardware resources is, for example: the number of a certain register. And after the first preset access configuration and the second preset access configuration are changed, the corresponding operating system needs to be restarted to complete the application of the new configuration. For example: if the first preset access configuration is modified, then restart the non-real-time operating system.

[0063] The BMC chip provided in this embodiment can simultaneously load and run two operating systems, and these two operating systems are used to execute different types of tasks. Among them, the first processor core group in the BMC chip is loaded with a non-real-time operating system, so that the first processor core group accesses non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks; the second processor core group in the BMC chip is loaded with a real-time operating system, so that the second processor core group accesses real-time hardware resources based on the real-time operating system to execute real-time control tasks. Since the real-time control tasks are implemented based on the real-time operating system with lower power consumption and faster speed than those implemented based on the non-real-time operating system, the BMC chip can not only quickly complete real-time control tasks, but also relatively reduce the system power consumption; and also reduce the burden on the non-real-time operating system.

[0064] It can be seen that the BMC chip can achieve application management, management of various peripherals and sensor interfaces through the operating system loaded on the processor core, and can also realize data transmission and simple management of the local server remotely through the network interface. And, the non-real-time operating system and the real-time operating system in this embodiment run in parallel in the BMC chip, optimizing the overall performance and flexibility of the BMC, which can meet the real-time monitoring and common management requirements under various complex application requirements of the server, and can also make the server host boot up as soon as possible.

[0065] Based on the above embodiments, it should be noted that the functions of the BMC can be simply classified into three categories: monitoring, management, and control. Monitoring is to obtain the status information from the host and various devices and components on the motherboard; management refers to sending data information or operation requests to the host or other devices based on the status information or input instructions and through corresponding standard protocols; control is to directly achieve precise control of devices and components by outputting high and low level signals. Among them, the difference between management and control lies in that the management function has low requirements for real-time performance, but can send more complex data and instructions, and is more convenient for the operation and maintenance of servers and big data centers; while the control function often requires precise real-time control for information acquisition and monitoring of some small-scale devices and components, such as various sensors, switches, etc. Accordingly, the management and monitoring functions with non-real-time requirements are set in a non-real-time operating system below, and the monitoring and control functions with real-time requirements are set in a real-time operating system, providing a BMC architecture that supports dual systems, dividing the functions originally completed by a single operating system according to application requirements and completing them by two parallel operating systems. At the same time, define and optimize the task switching method of the dual systems to optimize the overall performance and flexibility of the monitoring and management system.

[0066] In one example, the non-real-time operating system continues to use the operating system applicable to existing BMC chips to implement the management function with non-real-time requirements and some monitoring functions that need to read data through standard protocols (such as CPU monitoring, monitoring of abnormal device operation, etc.). Another operating system uses a real-time operating system (such as FreeRTOS, etc.) to implement the control function with real-time requirements and some monitoring functions that can directly read data through the serial port.

[0067] To achieve the independent parallel operation of the dual systems carried, more than two processor cores need to be integrated in the BMC chip. For example, a dual-core processor is set in the BMC chip. Of course, two different processor cores can also be integrated in the BMC chip. For example, one uses the A series of ARM Corporation and the other uses the R series of ARM Corporation. And make the on-chip resources of the processor core where the real-time operating system is located less than those of the processor core where the non-real-time operating system is located to save costs. If two processor cores are used, these two processor cores can be interconnected through standard AXI or other buses, and peripheral interfaces and modules can be mounted.

[0068] To enable the two operating systems to access the corresponding resources in the BMC chip respectively, the various resources in the BMC chip can be virtualized so that the same resource has corresponding virtual resources in both operating systems to solve the problem of competing access.

[0069] Under normal circumstances, two operating systems do not need to compete for the same resources. To save resource overhead and reduce design complexity, virtualization technology can be not adopted to virtualize resources, but instead, the control bus in the chip can be directly configured so that the two operating systems have access rights to different hardware resources. The control bus can separately record the numbers of hardware such as registers that can be accessed by the two operating systems to implement the access configuration of the two operating systems. When a certain operating system attempts to access a certain resource, the control bus checks the register with the corresponding configuration information. If it has permission, it can access normally; if it has no permission, it will directly handle it as if there is no such resource. In this way, the mutually exclusive access to all resources can be achieved by maintaining two registers. That is: use one register to record the numbers of resources that the non-real-time operating system can access, and use another register to record the numbers of resources that the real-time operating system can access. Under this design, no on-chip resources such as interfaces need to be added to the BMC chip, and only a small amount of resources such as interrupt control and debugging interfaces for processor core management need to be added. However, dynamic function changes cannot be achieved. Specifically, after a certain operating system is started, if the register is modified to change the resources that the operating system can access, the operating system needs to be restarted. However, in the application scenario of the BMC monitoring and management system, the function division of the dual-system generally does not need to be changed frequently. Therefore, after configuring the functions in the dual-system according to requirements before power-on, it generally does not need to be changed.

[0070] Flexibly divide the BMC management functions, and then configure them in the two operating systems respectively according to different application scenarios. Some management functions can be directly implemented on the real-time operating system. In an extreme case, the non-real-time operating system as the main operating system can even be shut down to reduce power consumption.

[0071] Among them, the startup duration of the real-time operating system is much faster than that of the main operating system, generally several seconds. The two operating systems provided in this embodiment are started in parallel during the power-on process. After the real-time operating system is started, it will start to monitor and control the fans, sensors, etc. on the server motherboard. At this time, the power-on process of the server host can also be started, which can enable the server to power on quickly while ensuring reliability.

[0072] It can be seen that according to this embodiment, a dual-system BMC chip architecture can be designed, which divides the functions originally integrated on a single processor core into different processor cores, and different operating systems are carried on different processor cores. By adding a parallel real-time operating system, the real-time monitoring and control requirements under various complex application requirements of the server can be met, and at the same time, the power-on process of the server can be optimized to improve flexibility. At the same time, the competition handling of shared resources by the dual-system can be simplified through register configuration and virtualization technology, and the design implementation difficulty can be reduced while ensuring sufficient flexibility.

[0073] The following introduces an electronic device provided by an embodiment of the present application. The electronic device described below can be referred to in mutual reference with the resource access method and device described above.

[0074] See Figure 2 As shown, an embodiment of the present application discloses an electronic device, including:

[0075] A memory 201 for storing a computer program;

[0076] A processor 202 for executing the computer program to implement the method disclosed in any of the above embodiments.

[0077] See Figure 3 As shown, an embodiment of the present application also provides a device provided with a BMC chip as the above-mentioned electronic device. The device provided with the BMC chip may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. Among them, the memory is used for storing a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the resource access method disclosed in any of the foregoing embodiments.

[0078] In this embodiment, the power supply is used to provide a working voltage for each hardware device on the device provided with the BMC chip; the communication interface can create a data transmission channel between the device provided with the BMC chip and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is made here; the input / output interface is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0079] In addition, as a carrier for resource storage, the memory can be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon include an operating system, a computer program, and data, etc., and the storage method can be temporary storage or permanent storage.

[0080] Among them, the operating system is used to manage and control each hardware device and computer program on the device provided with the BMC chip to implement the operation and processing of data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the resource access method disclosed in any of the foregoing embodiments, the computer program can further include a computer program that can be used to complete other specific tasks. In addition to data such as virtual machines, the data can also include data such as the developer information of the virtual machine.

[0081] Further, the embodiment of the present application also provides a terminal as the above-mentioned electronic device. The terminal may specifically include, but is not limited to, a smart phone, a tablet computer, a laptop computer, or a desktop computer, etc.

[0082] Generally, the terminal in this embodiment includes: a processor and a memory.

[0083] Among them, the processor may include one or more processing cores, such as a 4-core processor or an 8-core processor. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning.

[0084] The memory may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory is at least used to store the following computer program. After the computer program is loaded and executed by the processor, it can implement the relevant steps in the resource access method executed by the terminal side disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of application programs.

[0085] In some embodiments, the terminal may further include a display screen, an input / output interface, a communication interface, sensors, a power supply, and a communication bus.

[0086] The following introduces a readable storage medium provided by an embodiment of the present application. The readable storage medium described below can be referred to in relation to the resource access method, device, and equipment described above.

[0087] A readable storage medium is used to store a computer program. When the computer program is executed by a processor, it implements the resource access method disclosed in the foregoing embodiments. Here, the readable storage medium is a computer-readable storage medium. As a carrier for storing resources, it can be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc. The resources stored thereon include an operating system, a computer program, and data, etc. The storage method can be transient storage or permanent storage.

[0088] The following introduces a BMC chip provided by an embodiment of the present application. The BMC chip described below can be referred to in relation to the resource access method described above.

[0089] See Figure 4 As shown, an embodiment of the present application discloses a BMC chip, including: a first processor core group composed of at least one processor core, a second processor core group composed of at least one processor core, non-real-time hardware resources, and real-time hardware resources. The first processor core group and the second processor core group can be integrated in the same processor, or different cores can be interconnected using AXI or other buses, and peripheral interfaces and modules can be mounted.

[0090] Among them, the first processor core group is equipped with a non-real-time operating system; the first processor core group is used to: access non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks; the second processor core group is equipped with a real-time operating system; the second processor core group is used to: access real-time hardware resources based on the real-time operating system to execute real-time control tasks.

[0091] Among them, the non-real-time operating system and the real-time operating system run in parallel in the BMC chip.

[0092] In a specific embodiment, the BMC chip is further used to: after the second processor core group controls the startup of the real-time operating system, trigger the startup process of the server to which it belongs.

[0093] In a specific embodiment, the non-real-time hardware resources include: hardware resources for detecting the status of the host; correspondingly, the first processor core group is specifically used to: access the hardware resources for detecting the status of the host based on the non-real-time operating system to detect the operating status of the server to which the BMC chip belongs.

[0094] In a specific embodiment, the real-time hardware resources include: hardware resources for monitoring sensor information and / or hardware resources for detecting abnormal information; correspondingly, the second processor core group is specifically configured to: access the hardware resources for monitoring sensor information and / or the hardware resources for detecting abnormal information based on a real-time operating system, so as to obtain sensor information and / or abnormal information.

[0095] In a specific embodiment, the first processor core group is specifically configured to: access non-real-time hardware resources based on a non-real-time operating system and a first virtualization configuration; correspondingly, the second processor core group is specifically configured to: access real-time hardware resources based on a real-time operating system and a second virtualization configuration.

[0096] In a specific embodiment, the first processor core group is specifically configured to: modify the first virtualization configuration based on a non-real-time operating system, so as to change the non-real-time hardware resources accessible to the first processor core group; correspondingly, the second processor core group is specifically configured to: modify the second virtualization configuration based on a real-time operating system, so as to change the real-time hardware resources accessible to the second processor core group.

[0097] In a specific embodiment, the BMC chip further includes: a control bus; correspondingly, the first processor core group is specifically configured to: send a non-real-time access instruction to the control bus based on a non-real-time operating system, so that the control bus determines the non-real-time hardware resources accessible by the non-real-time access instruction according to a first preset access configuration, and after obtaining a non-real-time access result by accessing the non-real-time hardware resources, return the non-real-time access result to the first processor core group; the second processor core group is specifically configured to: send a real-time access instruction to the control bus based on a real-time operating system, so that the control bus determines the real-time hardware resources accessible by the real-time access instruction according to a second preset access configuration, and after obtaining a real-time access result by accessing the real-time hardware resources, return the real-time access result to the second processor core group.

[0098] Wherein, for the more specific working processes of each module and unit in this embodiment, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.

[0099] It can be seen that this embodiment provides a BMC chip that can simultaneously load and run two operating systems, and these two operating systems are used to execute different types of tasks, optimizing the overall performance and flexibility of the BMC, and can meet the real-time monitoring and common management requirements under various complex application requirements of the server, and can also enable the server host to boot up as soon as possible.

[0100] The "first", "second", "third", "fourth", etc. (if any) involved in this application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments described here can be implemented in an order other than that shown or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, or devices.

[0101] It should be noted that the descriptions involving "first", "second", etc. in this application are only for descriptive purposes, and should not be construed as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. Additionally, the technical solutions between various embodiments can be combined with each other, but it must be based on what can be achieved by those of ordinary skill in the art. When the combination of technical solutions results in contradictions or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0102] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts between the various embodiments, reference can be made to each other.

[0103] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, a software module executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of readable storage medium known in the technical field.

[0104] Specific examples are used in this article to elaborate on the principles and implementation manners of this application. The descriptions of the above embodiments are only for helping to understand the method and its core idea of the processor of this application; at the same time, for those of ordinary skill in the art, based on the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A resource access method, characterized in that, Applied to a BMC chip, the BMC chip includes: a first processor core group composed of at least one processor core, a second processor core group composed of at least one processor core, non-real-time hardware resources, and real-time hardware resources; Among them, the first processor core group is equipped with a non-real-time operating system, and the first processor core group accesses the non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks; The second processor core group is equipped with a real-time operating system, and the second processor core group accesses the real-time hardware resources based on the real-time operating system to execute real-time control tasks; Among them, the non-real-time operating system and the real-time operating system are started and run in parallel in the BMC chip; After the second processor core group controls the start of the real-time operating system, the BMC chip triggers the power-on process of the server to which it belongs.

2. The resource access method according to claim 1, wherein The non-real-time hardware resources include: hardware resources for detecting the host status; Accordingly, the first processor core group accesses the hardware resources for detecting the host status based on the non-real-time operating system to detect the operating status of the server to which the BMC chip belongs.

3. The resource access method according to claim 1, wherein The real-time hardware resources include: hardware resources for monitoring sensor information and / or hardware resources for detecting abnormal information; Accordingly, the second processor core group accesses the hardware resources for monitoring sensor information and / or the hardware resources for detecting abnormal information based on the real-time operating system to obtain sensor information and / or abnormal information.

4. The resource access method according to any one of claims 1 to 3, wherein The first processor core group accesses the non-real-time hardware resources based on the non-real-time operating system and the first virtualization configuration; Accordingly, the second processor core group accesses the real-time hardware resources based on the real-time operating system and the second virtualization configuration.

5. The resource access method according to claim 4, wherein The first processor core group modifies the first virtualization configuration based on the non-real-time operating system to change the non-real-time hardware resources accessible by the first processor core group; Accordingly, the second processor core group modifies the second virtualization configuration based on the real-time operating system to change the real-time hardware resources accessible by the second processor core group.

6. The resource access method according to any one of claims 1 to 3, wherein The BMC chip further includes: a control bus; Accordingly, the first processor core group sends a non-real-time access instruction to the control bus based on the non-real-time operating system, so that the control bus determines the non-real-time hardware resources accessible by the non-real-time access instruction according to a first preset access configuration. After obtaining a non-real-time access result when accessing the non-real-time hardware resources, the non-real-time access result is returned to the first processor core group; The second processor core group sends a real-time access instruction to the control bus based on the real-time operating system, so that the control bus determines the real-time hardware resources accessible by the real-time access instruction according to a second preset access configuration. After obtaining a real-time access result when accessing the real-time hardware resources, the real-time access result is returned to the second processor core group.

7. An electronic device, characterized in that, Comprising: A memory for storing a computer program; A processor for executing the computer program to implement the method according to any one of claims 1 to 6.

8. A readable storage medium, characterized in that, For saving a computer program, wherein the computer program, when executed by a processor, implements the method according to any one of claims 1 to 6.

9. A BMC chip, characterized in that, Comprising: A first processor core group composed of at least one processor core, a second processor core group composed of at least one processor core, non-real-time hardware resources, and real-time hardware resources; Wherein, the first processor core group is equipped with a non-real-time operating system; the first processor core group is used for: accessing the non-real-time hardware resources based on the non-real-time operating system to execute non-real-time management tasks; the second processor core group is equipped with a real-time operating system; the second processor core group is used for: accessing the real-time hardware resources based on the real-time operating system to execute real-time control tasks; Wherein, the non-real-time operating system and the real-time operating system are started and run in parallel in the BMC chip; after the second processor core group controls the start of the real-time operating system, the BMC chip triggers the power-on process of the server to which it belongs.

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