Methods, systems, devices, and storage media of general management test platform components

Abstract

The application provides a method, system, device and storage medium for managing components of a general test platform, the method comprising: setting a mapping relationship between an instruction unit and a pre-defined basic stimulus, and setting a parallel trigger flag in the instruction unit; recombining the basic stimulus according to a verification scenario by a stimulus recombination management module, and sending the recombined stimulus to each test component in sequence; in response to the basic stimulus mapped by the current instruction unit being executed by the test component, feeding back an instruction completion flag to the stimulus recombination management module and executing the basic stimulus mapped by the next instruction unit; and in response to the stimulus recombination management module monitoring that the parallel trigger flag of the instruction unit is valid, ignoring the sequence limitation and directly executing the basic stimulus mapped by the instruction unit in parallel. The application can flexibly send multiple stimuli to different test components through multi-thread operation according to an actual scenario.

Description

Technical Field

[0001] This invention relates to the field of chip development, and more specifically, to a method, system, device, and storage medium for managing the components of a general-purpose test platform. Background Technology

[0002] Verification is a crucial part of chip development, determining the correctness and proper functioning of the design under test (DUT). In a verification environment, the test platform forms the foundation, determining the quality of verification, while stimuli drive the simulation, determining the efficiency. A complete test platform mainly consists of components such as a driver, sequencer, monitor, reference model, and scoreboard. Test stimuli (Sequences) generate transactions that pass through the sequencer and are ultimately received by the driver. The process of test stimulus transmission is linear; that is, test stimuli are executed serially by the test components in a fixed format. However, in scenarios involving handshakes between test components, manual multi-threading within the sequence is required.

[0003] One of the most common verification methods currently is for verification personnel to manually develop stimulus files for specific functions of the DUT (Design Under Test) based on the verification objectives, and then use drivers to input the stimuli into the DUT to test whether the relevant functions work properly. To improve efficiency and the applicability of test stimuli, verification personnel extract the stimulus parameters required for specific working scenarios of the DUT, including initial request nodes, final request nodes, and target memory addresses, as input items to the stimulus control function, automatically generating test stimulus files for that scenario. For specific scenarios, test stimuli are formed using fewer parameters, test cases are loaded, and the verification components are operated in an organized and fixed order to input the stimulus into the DUT.

[0004] The types of stimuli mainly include clock settings, resets, and I / O stimuli for the corresponding scenarios of the DUT. In the verification work, these tasks are usually output by specific test components. Verification personnel are responsible for manually writing such stimuli into test cases, using the sequence generators of various test components included in the verification environment to output the written stimuli to the driver, thereby realizing the stimulus input to the DUT, and finally observing whether the actual output of the DUT meets expectations. Summary of the Invention

[0005] In view of this, the purpose of this invention is to propose a method, system, computer device, and computer-readable storage medium for managing various components of a general-purpose test platform. This invention organizes different stimuli into an instruction unit queue according to a specific mapping relationship and a prescribed format, distributing them to different test components as expected, thereby enabling the test components to send stimuli. When the stimulus reorganization module detects that the parallel trigger bit flag in the instruction unit is set, it can hand over the next instruction unit to the test component for execution and send it to the design under test without waiting for the current instruction unit to return an instruction completion flag. This avoids the cumbersome manual configuration or management of test stimuli. Later, verification engineers can also expand the test stimuli according to the verification objectives and incorporate them into the instruction unit queue. This method allows for flexible reuse and facilitates project iteration.

[0006] Based on the above objectives, one aspect of the present invention provides a method for managing components of a general-purpose test platform, comprising the following steps: setting a mapping relationship between instruction units and predefined basic stimuli, and setting a parallel trigger flag in the instruction unit; reorganizing the basic stimuli according to the verification scenario through a stimulus reorganization management module and sending the reorganized stimuli to each test component in sequence; responding to the completion of execution of the basic stimuli mapped to the current instruction unit by the test component, feeding back an instruction completion flag to the stimulus reorganization management module and executing the basic stimuli mapped to the next instruction unit; and responding to the stimulus reorganization management module detecting that the parallel trigger flag of the instruction unit is valid, ignoring the order restriction and directly executing the basic stimuli mapped to the instruction unit in parallel.

[0007] In some implementations, setting the mapping relationship between the instruction unit and the predefined basic stimulus includes binding the predefined basic stimulus to the distribution channel of the instruction unit.

[0008] In some implementations, the step of reorganizing the basic incentives according to the verification scenario by the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: arranging different incentives in a prescribed format according to the mapping relationship to form an instruction unit queue, and distributing the corresponding incentives in the instruction unit queue to different test components according to a preset destination.

[0009] In some implementations, the step of reorganizing basic incentives according to the verification scenario through the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: numbering and storing predefined basic incentives for each basic function of the design under test, and encapsulating them in the incentive reorganization management module to form an incentive pool.

[0010] In some implementations, the step of reorganizing the basic incentives according to the verification scenario by the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: writing the incentive number of the current instruction unit into the incentive number memory, and notifying the incentive pool to send the incentive corresponding to the incentive number to the corresponding incentive distribution channel.

[0011] In some implementations, the basic incentive for directly executing the instruction unit in parallel without regard to order constraints includes: activating the counter comparator in response to the parsing block resolving to a valid parallel flag for the current instruction unit; and requesting the counter comparator to increment the current count value in the counter comparator by one each time a corresponding instruction completion flag for a parallel instruction unit is received.

[0012] In some implementations, the basic stimulus for directly executing the instruction unit in parallel without regard to the order constraint includes: in response to the current count value in the counter comparator being incremented by one and equal to the target count value, triggering a clear signal by the instruction completion flag of the last received parallel instruction unit to clear both the target count value and the current count value in the counter comparator.

[0013] In another aspect, this invention provides a system for managing components of a general-purpose test platform, comprising: a setting module configured to set a mapping relationship between instruction units and predefined basic stimuli, and to set a parallel trigger flag in the instruction units; a sending module configured to reorganize the basic stimuli according to the verification scenario through an incentive reorganization management module and send the reorganized stimuli to each test component in sequence; a feedback module configured to, in response to the completion of execution of the basic stimuli mapped to the current instruction unit by the test component, feed back an instruction completion flag to the incentive reorganization management module and execute the basic stimuli mapped to the next instruction unit; and a parallel module configured to, in response to the incentive reorganization management module detecting that the parallel trigger flag of the instruction unit is valid, ignore the order restriction and directly execute the basic stimuli mapped to the instruction unit in parallel.

[0014] In another aspect of the present invention, a computer device is provided, comprising: at least one processor; and a memory storing computer instructions executable on the processor, the instructions, when executed by the processor, implementing the steps of the method described above.

[0015] In another aspect, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method steps.

[0016] The present invention has the following beneficial technical effects:

[0017] (1) This invention enables verification personnel to conveniently manage multiple stimuli defined in the verification platform in a unified manner. They only need to input the CU queue number to realize the storage and redistribution of stimuli through the SRM module. This reduces manual intervention. Unlike the general test case implementation process, after the initial definition of basic stimuli, verification personnel can avoid repeatedly calling or combining various simple stimuli in the later stages, thus improving verification efficiency and accuracy.

[0018] (2) Based on the incentive parallel execution management principle proposed in this invention, multiple incentives can be flexibly transferred to the test components through multi-threaded operations according to the actual scenario. Complex scenarios can be achieved with simple operations according to the set logic. According to actual needs, the verification personnel can also expand the incentive pool and continuously improve the test incentives. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram illustrating an embodiment of the method for the various components of the universal management testing platform provided by the present invention;

[0021] Figure 2 A schematic diagram illustrating the incentive distribution of the incentive restructuring management module provided by this invention;

[0022] Figure 3 A schematic diagram of the instruction unit queue selector structure provided by the present invention;

[0023] Figure 4 A schematic diagram of the instruction unit parser structure provided by the present invention;

[0024] Figure 5 A schematic diagram of the parallel instruction unit queue provided by the present invention;

[0025] Figure 6 A schematic diagram of an embodiment of the components of the universal management testing platform provided by the present invention;

[0026] Figure 7 A schematic diagram of the hardware structure of the computer equipment for each component of the universal management and testing platform provided by the present invention;

[0027] Figure 8 This is a schematic diagram of an embodiment of the computer storage medium for each component of the universal management and testing platform provided by the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0029] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0030] In a first aspect, an embodiment of a method for managing the components of a general-purpose test platform is proposed. Figure 1 This diagram illustrates an embodiment of the method for the various components of the universal management testing platform provided by the present invention. For example... Figure 1 As shown, the embodiments of the present invention include the following steps:

[0031] S1. Set the mapping relationship between the instruction unit and the predefined basic stimulus, and set the parallel trigger flag in the instruction unit;

[0032] S2. The incentive reorganization management module reorganizes the basic incentives according to the verification scenario and sends the reorganized incentives to each test component in sequence.

[0033] S3. In response to the completion of the execution of the basic stimulus mapped to the current instruction unit by the tested component, an instruction completion flag is fed back to the stimulus reorganization management module, and the basic stimulus mapped to the next instruction unit is executed; and

[0034] S4. In response to the incentive reorganization management module detecting that the parallel trigger flag of the instruction unit is valid, the basic incentive mapped by the instruction unit is executed directly in parallel, ignoring the order restriction.

[0035] This invention, based on a UVM verification environment, proposes an stimulus reorganization module (SRM). SRM organizes different stimuli into a CU (Command Unit) queue according to a specific mapping relationship and a prescribed format. This queue is then distributed to different test components as expected, enabling the test components to send stimuli. Here, the test components can be VIP (Verification Intellectual Property), VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) models, Verilog models, etc. Simultaneously, this invention proposes a feedback mechanism to meet the needs of scenarios requiring parallel execution between different stimuli. This function is achieved through the CA (Command Achievement) feedback after each stimulus execution is completed. Normally, multiple stimuli execute sequentially. When SRM detects that the parallel trigger flag in a CU is set, it can hand over the next CU to the test component for execution and send it to the DUT without waiting for the current CU to feedback CA. This avoids the tedious manual configuration or management of test stimuli. Later, verification engineers can also expand the test stimuli according to the verification objectives and incorporate them into the CU queue. This method allows for flexible reuse and facilitates project iteration.

[0036] Regarding the stimulus input to the DUT, on the one hand, this invention utilizes CUs of a specific format to pre-organize multiple CU queues, which are stored locally by the proposed SRM and called on demand. When the test component finishes executing the current CU, a specific event triggers the verification environment to feed back the CA to the SRM. On the other hand, for CUs that need to be executed in parallel, when the SRM detects that the parallel trigger flag in the CU is valid, it can organize the dispatch of the next CU and hand it over to the test component for execution without waiting for the CA to be fed back after the current CU is completed. The formats of CUs and CAs in this invention are predefined. For different verification scenarios (DUT initialization and its internal functional scenarios), the SRM module reorganizes the stimuli and distributes them to each test component. After receiving the instructions, the test component will send the stimuli as expected to drive the DUT to perform functional verification. This method is easy to reuse and can be extended and randomly combined in various predefined CU queues according to the needs of verification personnel.

[0037] The instruction unit (CU) is mapped one-to-one with predefined basic stimuli, providing a simple description of each stimuli and binding it to the internal CU distribution channel. In addition, a parallel trigger flag is added to enable parallel stimuli dispatch. The main fields of the CU are defined as follows:

[0038] Class: SRM_CU_ITEM();

[0039] start

[0040] logic[x-1:0] is the stimulus number;

[0041] logic[m-1:0] Channel number;

[0042] logic parallel flag;

[0043] int: Total number of parallel CUs;

[0044] …;

[0045] Finish

[0046] The Command Completion Flag (CA) is used by the tested component to send the completed processing result back to the SRM after the basic stimulus mapped to the current CU has finished executing. A mapping relationship is established between the channel number and the distribution channel, and releasing the distribution channel restores the channel to a waiting-to-receive state. The main fields of CA are defined as follows:

[0047] Class: SRM_CA_ITEM();

[0048] start

[0049] Logic[x-1:0] is the stimulus number;

[0050] Logic[m-1:0] Channel number;

[0051] …;

[0052] Finish

[0053] The Incentive Reorganization Management (SRM) module, for example, predefines and numbers basic incentives for the DUT's (Device Under Test) basic functions, storing them within an incentive pool. Incentives for complex scenarios are composed of multiple basic incentives, ultimately forming an incentive queue. Through a specific mapping relationship, the SRM is responsible for distributing these incentives to the corresponding test components for execution, driving the DUT to complete various functional verifications. Upon successful issuance of each incentive, feedback information is sent to the SRM, forming an interaction between the SRM and the environment, thus achieving closed-loop operation. Figure 2 This is a schematic diagram of the incentive distribution in the incentive restructuring management module provided by the present invention, as shown below. Figure 2 As shown, the incentive reorganization management module includes a CU memory, a CU queue selector, a CU parser, an incentive distribution channel, and an event queue.

[0054] The CU (Computer Unit) memory stores CU queues, which are composed of multiple CUs. For more complex scenarios involving multiple test components, the CU queues are responsible for description. The CU memory contains multiple CU queues. The queue length is not fixed, and the number of queues can be expanded.

[0055] The CU queue selector is similar to a general selector. The selection signal (Sel) bit width is defined based on the number of CU queues in the CU memory. Assuming the bit width is denoted by `width`, and the number of CU queues in the CU memory is `n`, then `width ≥ INT(n)`, where `INT` represents the floor function, and `width` is rounded up. Based on the external input `Sel`, one CU queue is selected and output to the CU parser. A buffer is used to store CU queues, and each CU is output to the CU parser for parsing. A schematic diagram of the CU queue selector is shown below. Figure 3 As shown, A represents the selection signal, D corresponds to the CU queue, and O is the final output CU queue.

[0056] Figure 4 This is a schematic diagram of the instruction unit parser structure provided by the present invention. The CU parser is mainly used to determine the stimulus mapped in the stimulus pool of the instruction unit currently being processed, and to determine the test component responsible for future execution. After parsing, the stimulus number of the current CU is written into the stimulus number memory. The stimulus pool is notified to send the corresponding stimulus to the corresponding stimulus distribution channel. The CU parser is internally composed of a CU parsing block and a parallel counter. The main fields of the counter comparator are defined as follows. In the initial state, the counter is always in an inactive state, that is, the Ready signal is always 0; in the scenario of parallel execution of stimuli, as soon as the received CU parallel flag position is reached, the Ready signal is 1, and it is in the parallel scenario preparation state.

[0057] The incentive distribution channel is responsible for sending received incentives from the corresponding channel to the test component for execution. The number of channels is the same as the number of test components. Each channel has a channel open flag F, which is 1 when the channel is busy, meaning the test component is still executing the corresponding incentive. When execution is complete, the channel flag is set to 0 via an event trigger, indicating that the channel can receive new incentives. Setting the channel flag is used to prevent incentives from being lost before they are executed by the test component.

[0058] The number of events in the event queue matches the number of test components. When a test component finishes sending stimuli, it will trigger the corresponding event, carrying the CA (Certificate of Action) back to the stimulus distribution channel to release the corresponding channel. The main fields of the event are defined as follows:

[0059] Class: SRM_EVENT_ITEM();

[0060] start

[0061] Logic[m-1:0] Channel number;

[0062] SRM_CA_ITEM CA;

[0063] …;

[0064] Finish

[0065] Set the mapping relationship between the instruction unit and the predefined basic stimulus, and set the parallel trigger flag in the instruction unit.

[0066] In some implementations, setting the mapping relationship between the instruction unit and the predefined basic stimulus includes binding the predefined basic stimulus to the distribution channel of the instruction unit.

[0067] The incentive reorganization management module reorganizes the basic incentives according to the verification scenario and sends the reorganized incentives to each test component in sequence.

[0068] In some implementations, the step of reorganizing the basic incentives according to the verification scenario by the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: arranging different incentives in a prescribed format according to the mapping relationship to form an instruction unit queue, and distributing the corresponding incentives in the instruction unit queue to different test components according to a preset destination.

[0069] In some implementations, the step of reorganizing basic incentives according to the verification scenario through the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: numbering and storing predefined basic incentives for each basic function of the design under test, and encapsulating them in the incentive reorganization management module to form an incentive pool.

[0070] In some implementations, the step of reorganizing the basic incentives according to the verification scenario by the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: writing the incentive number of the current instruction unit into the incentive number memory, and notifying the incentive pool to send the incentive corresponding to the incentive number to the corresponding incentive distribution channel.

[0071] In response to the completion of the basic stimulus mapped to the current instruction unit by the tested component, the instruction completion flag is fed back to the stimulus reorganization management module and the basic stimulus mapped to the next instruction unit is executed.

[0072] In response to the incentive reorganization management module detecting that the parallel trigger flag of the instruction unit is valid, the basic incentive mapped by the instruction unit is executed directly in parallel, ignoring the order restriction.

[0073] In some implementations, the basic incentive for directly executing the instruction unit in parallel without regard to order constraints includes: activating the counter comparator in response to the parsing block resolving to a valid parallel flag for the current instruction unit; and requesting the counter comparator to increment the current count value in the counter comparator by one each time a corresponding instruction completion flag for a parallel instruction unit is received.

[0074] In some implementations, the basic stimulus for directly executing the instruction unit in parallel without regard to the order constraint includes: in response to the current count value in the counter comparator being incremented by one and equal to the target count value, triggering a clear signal by the instruction completion flag of the last received parallel instruction unit to clear both the target count value and the current count value in the counter comparator.

[0075] Normally, CUs in the CU queue are dispatched sequentially, meaning stimuli in the stimulus pool are executed serially. However, a special case arises where verifiers may want multiple stimuli to execute in parallel, meaning the next stimuli can begin execution without waiting for the current stimuli to finish (receive the corresponding CA). However, this scenario does not currently support the parallel execution of multiple stimuli for a unified test component.

[0076] In certain scenarios, multiple stimuli need to be executed in parallel. The CU queue for this type is described as follows: Figure 5 As shown, the parallel flag (sync) of non-parallel CUs is 0, while that of parallel CUs is 1 and they are arranged sequentially in the CU queue. In this scenario, when the parsing block reaches the parallel flag position of the current CU, the count comparator is set to Ready. Each time a corresponding CA belonging to a parallel CU is received (the stimulus number in the CA is compared with the stimulus number in the stimulus number memory; if they are equal, the current stimulus number is released), a request is sent to the count comparator, incrementing the current count value in the comparator. A response of 1 from the count comparator indicates that the incrementing operation is complete, and the parser can continue to send requests to the count comparator. When the incremented current count value in the count comparator equals the target count value, the Clear signal is triggered by the last received CA of the parallel CU, clearing both the target and current count values ​​in the count comparator to 0, and setting Ready to 0. At this point, all concurrent CUs have completed execution.

[0077] This invention integrates the SRM module into the verification environment to manage stimuli in the verification platform. First, the stimuli driving basic functions are remapped to CUs. The CU queue, formed by cascading CUs, reflects the functions of simple scenarios. During the realization of the verification target, the CU queues are output individually or in combination via the stimulus distribution channel in the SRM, ultimately performing the operation on the test component as expected. Second, the CA proposed in this scheme indicates that the stimulus mapped to the current CU has been executed by the test component, while releasing the internal memory space and the stimulus distribution channel, thus forming a closed-loop operation of the stimulus distribution-completion feedback mechanism. Finally, considering the multi-threaded parallel operation of the test component, a parallel execution control principle for stimuli is proposed. With the help of the simple mapping relationship between CUs and CAs, the synchronous execution process between multiple basic stimuli is realized.

[0078] This invention enables verification personnel to conveniently manage multiple stimuli defined in the verification platform in a unified manner. By simply inputting the CU queue number, the SRM module can store and redistribute the stimuli. This reduces manual intervention. Unlike the typical test case implementation process, after defining the basic stimuli initially, verification personnel can avoid repeatedly calling or combining various simple stimuli in the later stages, improving verification efficiency and accuracy.

[0079] The parallel execution management principle of incentives proposed in this invention allows for the flexible allocation of multiple incentives to different test components through multi-threaded operations, enabling complex scenarios with simplified operations according to pre-defined logic. Furthermore, verification personnel can expand the incentive pool and continuously improve the test incentives based on actual needs.

[0080] This invention provides a lightweight testing environment, unified management of test incentives, and the ability to describe the general behavior of test targets, thereby improving test case development efficiency and shortening the front-end verification cycle.

[0081] Based on the SRM incentive distribution scheme of this invention, an error feedback and handling mechanism can be added for test component incentive execution failure scenarios. Additionally, a random scenario can be defined, arranging the CU queues in the CU memory according to priority numbers. For this random scenario, the SRM module automatically distributes the specified CU queues to each test component according to priority.

[0082] It should be particularly noted that the steps in each embodiment of the methods of each component of the above-mentioned general management test platform can be interleaved, substituted, added, or deleted. Therefore, these reasonable permutations and combinations of the methods of each component of the general management test platform should also fall within the protection scope of this invention, and the protection scope of this invention should not be limited to the embodiments.

[0083] Based on the above objectives, a second aspect of this invention proposes a system for managing the components of a general-purpose testing platform. For example... Figure 6 As shown, system 200 includes the following modules: a setting module, configured to set the mapping relationship between instruction units and predefined basic stimuli, and set a parallel trigger flag in the instruction unit; a sending module, configured to reorganize the basic stimuli according to the verification scenario through the stimulus reorganization management module and send the reorganized stimuli to each test component in sequence; a feedback module, configured to, in response to the completion of the execution of the basic stimuli mapped by the current instruction unit by the test component, feed back an instruction completion flag to the stimulus reorganization management module and execute the basic stimuli mapped by the next instruction unit; and a parallel module, configured to, in response to the stimulus reorganization management module detecting that the parallel trigger flag of the instruction unit is valid, ignore the order restriction and directly execute the basic stimuli mapped by the instruction unit in parallel.

[0084] In some implementations, the setting module is configured to bind the predefined basic stimulus to the distribution channel of the instruction unit.

[0085] In some implementations, the sending module is configured to: arrange different stimuli in a prescribed format according to the mapping relationship to form an instruction unit queue, and distribute the corresponding stimuli in the instruction unit queue to different test components according to a preset destination.

[0086] In some implementations, the sending module is configured to: number and store predefined basic stimuli for each basic function of the design under test, and encapsulate them in the stimulus reorganization management module to form an stimulus pool.

[0087] In some implementations, the sending module is configured to: write the incentive number of the current instruction unit into the incentive number memory, and notify the incentive pool to send the incentive corresponding to the incentive number to the corresponding incentive distribution channel.

[0088] In some implementations, the parallel module is configured to: activate the counter comparator in response to the parsing block resolving to a valid parallel flag for the current instruction unit; and request the counter comparator to increment the current count value in the counter comparator each time a corresponding instruction completion flag belonging to a parallel instruction unit is received.

[0089] In some implementations, the parallel module is configured to: in response to the current count value in the counter comparator being incremented by one and equal to the target count value, trigger a clear signal by means of the instruction completion flag of the last received parallel instruction unit to clear both the target count value and the current count value in the counter comparator.

[0090] Based on the above objectives, a third aspect of the present invention provides a computer device, comprising: at least one processor; and a memory storing computer instructions executable by the processor to perform the following steps: S1, setting a mapping relationship between instruction units and predefined basic stimuli, and setting a parallel trigger flag in the instruction unit; S2, reorganizing the basic stimuli according to the verification scenario through a stimulus reorganization management module and sending the reorganized stimuli to each test component in sequence; S3, in response to the completion of execution of the basic stimuli mapped to the current instruction unit by the test component, feeding back an instruction completion flag to the stimulus reorganization management module and executing the basic stimuli mapped to the next instruction unit; and S4, in response to the stimulus reorganization management module detecting that the parallel trigger flag of the instruction unit is valid, ignoring the order restriction and directly executing the basic stimuli mapped to the instruction unit in parallel.

[0091] In some implementations, setting the mapping relationship between the instruction unit and the predefined basic stimulus includes binding the predefined basic stimulus to the distribution channel of the instruction unit.

[0092] In some implementations, the step of reorganizing the basic incentives according to the verification scenario by the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: arranging different incentives in a prescribed format according to the mapping relationship to form an instruction unit queue, and distributing the corresponding incentives in the instruction unit queue to different test components according to a preset destination.

[0093] In some implementations, the step of reorganizing basic incentives according to the verification scenario through the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: numbering and storing predefined basic incentives for each basic function of the design under test, and encapsulating them in the incentive reorganization management module to form an incentive pool.

[0094] In some implementations, the step of reorganizing the basic incentives according to the verification scenario by the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: writing the incentive number of the current instruction unit into the incentive number memory, and notifying the incentive pool to send the incentive corresponding to the incentive number to the corresponding incentive distribution channel.

[0095] In some implementations, the basic incentive for directly executing the instruction unit in parallel without regard to order constraints includes: activating the counter comparator in response to the parsing block resolving to a valid parallel flag for the current instruction unit; and requesting the counter comparator to increment the current count value in the counter comparator by one each time a corresponding instruction completion flag for a parallel instruction unit is received.

[0096] In some implementations, the basic stimulus for directly executing the instruction unit in parallel without regard to the order constraint includes: in response to the current count value in the counter comparator being incremented by one and equal to the target count value, triggering a clear signal by the instruction completion flag of the last received parallel instruction unit to clear both the target count value and the current count value in the counter comparator.

[0097] like Figure 7 The diagram shown is a hardware structure schematic of a computer device for each component of the general management and testing platform provided by the present invention.

[0098] For example Figure 7 Taking the device shown as an example, the device includes a processor 301 and a memory 302.

[0099] Processor 301 and memory 302 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0100] Memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods of each component of the general management test platform in the embodiments of this application. Processor 301 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in memory 302, thereby implementing the methods of each component of the general management test platform.

[0101] Memory 302 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by using the methods of the various components of the general management test platform. Furthermore, memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 302 may optionally include memory remotely located relative to processor 301, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0102] The computer instructions 303 corresponding to the methods of each component of one or more general management test platforms are stored in memory 302. When executed by processor 301, the methods of each component of the general management test platform in any of the above method embodiments are executed.

[0103] Any embodiment of the computer device that executes the methods for each component of the aforementioned general management test platform can achieve the same or similar effects as any of the aforementioned method embodiments.

[0104] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs a method for executing various components of a general management test platform.

[0105] like Figure 8 The diagram shown is a schematic representation of an embodiment of the computer storage medium for the components of the general management and testing platform provided by the present invention. Figure 8 Taking the computer storage medium shown as an example, the computer-readable storage medium 401 stores a computer program 402 that, when executed by a processor, performs the above method.

[0106] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program for the methods of each component of the general management test platform can be stored in a computer-readable storage medium. When executed, the program can include the processes of the embodiments of the above methods. The storage medium for the program can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The above computer program embodiments can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0107] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0108] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0109] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0110] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0111] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for managing the components of a general-purpose testing platform, characterized in that, Includes the following steps: Set the mapping relationship between the instruction unit and the predefined basic stimulus, and set the parallel trigger flag in the instruction unit; The incentive reorganization management module reorganizes the basic incentives according to the verification scenario and sends the reorganized incentives to each test component in sequence. In response to the completion of the execution of the basic stimulus mapped by the current instruction unit by the tested component, the instruction completion flag is fed back to the stimulus reorganization management module and the basic stimulus mapped by the next instruction unit is executed; as well as In response to the incentive reorganization management module detecting that the parallel trigger flag of the instruction unit is valid, the basic incentives mapped by the instruction unit are executed directly in parallel, ignoring the order restriction; The step of reorganizing basic incentives according to the verification scenario through the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: numbering and storing predefined basic incentives for each basic function of the design under test, and encapsulating them in the incentive reorganization management module to form an incentive pool; writing the incentive number of the current instruction unit into the incentive number memory, and notifying the incentive pool to send the incentive corresponding to the incentive number to the corresponding incentive distribution channel; The basic stimuli for directly executing the instruction units in parallel without regard to order include: activating the counter comparator in response to the parsing block resolving to a valid parallel flag for the current instruction unit; and requesting the counter comparator to increment the current count value in the counter comparator upon receiving a corresponding instruction completion flag for each parallel instruction unit; and resetting both the target count value and the current count value in the counter comparator to zero in response to the current count value being incremented to equal the target count value by triggering a clear signal through the instruction completion flag of the last received parallel instruction unit.

2. The method according to claim 1, characterized in that, The mapping relationship between the setting instruction unit and the predefined basic stimulus includes: The predefined basic stimulus is bound to the distribution channel of the instruction unit.

3. The method according to claim 2, characterized in that, The step of reorganizing the basic incentives according to the verification scenario through the incentive reorganization management module and sending the reorganized incentives to each test component in sequence includes: Based on the mapping relationship, different stimuli are arranged in a specified format to form an instruction unit queue, and the corresponding stimuli in the instruction unit queue are distributed to different test components according to the preset destination.

4. A system for managing the components of a general-purpose testing platform, characterized in that, include: The configuration module configures the mapping relationship between the instruction unit and the predefined basic stimulus, and sets the parallel trigger flag in the instruction unit; The sending module is configured to reorganize the basic incentives according to the verification scenario through the incentive reorganization management module and send the reorganized incentives to each test component in sequence. The feedback module is configured to, in response to the completion of the basic stimulus mapped to the tested component by the current instruction unit, send an instruction completion flag to the stimulus reconfiguration management module and execute the basic stimulus mapped to the next instruction unit; and The parallel module is configured to, in response to the stimulus reorganization management module detecting that the parallel trigger flag of the instruction unit is valid, directly execute the basic stimulus mapped by the instruction unit in parallel, ignoring the order restriction; The sending module is also configured to perform various basic functions for the design under test, number and store predefined basic stimuli, encapsulate them in the stimuli reorganization management module to form an stimuli pool; write the stimuli number of the current instruction unit into the stimuli number memory, and notify the stimuli pool to send the stimuli corresponding to the stimuli number to the corresponding stimuli distribution channel; The parallel module is further configured to activate the counter comparator in response to the parsing block resolving to the current instruction unit's parallel flag being valid; and to send a request to the counter comparator to increment the current count value in the counter comparator upon receiving a corresponding instruction completion flag belonging to a parallel instruction unit; and to clear both the target count value and the current count value in the counter comparator to zero in response to the current count value being incremented to equal the target count value by triggering a clear signal through the instruction completion flag of the last received parallel instruction unit.

5. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-3.

6. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-3.

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