A FPGA development method and FPGA programming architecture

Abstract

The present invention discloses an FPGA development method and FPGA programming architecture. In the present invention, FPGA programming is divided into general services and extended services based on service type. General service functions are designed in EDA software using a hardware description language, and hardware package files are generated. Extended services are designed in a graphical design tool, and graphically designed IP or netlists are generated. The graphically designed IP or netlists are imported into the EDA software project containing the hardware package files, and synthesis, layout and routing are performed, and a bitstream file is generated. Using a hardware description language to design general service functions in the EDA software and designing the extended services in the graphical design tool reduces the difficulty of FPGA programming and facilitates secondary product development.

Description

Technical Field

[0001] The present invention relates to an FPGA development method and an FPGA program design architecture. Background Art

[0002] Field Programmable Gate Array (FPGA) devices are a type of semi-custom circuit within application-specific integrated circuits (ASICs). They are programmable logic arrays that effectively address the limited gate count of existing devices. The basic structure of an FPGA includes programmable input and output units, configurable logic blocks, a digital clock management module, embedded block RAM, routing resources, an embedded dedicated hard core, and underlying embedded functional units. Due to their rich routing resources, reprogrammability, high integration, and low investment, FPGAs have been widely used in digital circuit design.

[0003] The inventors have discovered that there are at least the following problems when designing FPGA programs: algorithms can generally be implemented directly on FPGA platforms using hardware description languages, but for most algorithms, especially those requiring floating-point operations, this method is difficult, cumbersome, and labor-intensive. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide an FPGA development method and an FPGA programming architecture, which reduce the difficulty of FPGA programming and are also conducive to secondary development of products.

[0005] To solve the above technical problems, an embodiment of the present invention provides an FPGA development method, including dividing FPGA program design into general services and extended services according to service types; designing general service functions in EDA software using a hardware description language and obtaining a hardware package file; designing extended services in a graphical design tool and generating a graphically designed IP or netlist; importing the graphically designed IP or netlist into an EDA software project containing the hardware package file, performing synthesis, layout and routing, and generating a bitstream file.

[0006] An embodiment of the present invention also provides an FPGA programming architecture, including: a hardware design module for designing general business functions in EDA software using a hardware description language and obtaining a hardware packaging file; a business function design module for designing extended business in a graphical design tool and generating a graphically designed IP or netlist; wherein general business and extended business are divisions of FPGA programming based on business types; an integration module for importing the graphically designed IP or netlist into an EDA software project containing a hardware packaging file, and performing synthesis, layout and routing, and generating a bitstream file.

[0007] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the above-mentioned FPGA development method.

[0008] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program implements the above-mentioned FPGA development method when executed by a processor.

[0009] Compared to the prior art, the embodiments of the present invention divide FPGA programming into general services and extended services. General services have a certain degree of universality, while extended services are implemented on the basis of general services and usually require the support of computing algorithms. General service functions are designed in EDA software using hardware description languages, and the extended services are designed in graphical design tools. Designers only need to understand the relevant algorithms for the extended services to design and implement them graphically, which lowers the design threshold. In addition, the FPGA programming is divided, and hardware packaging is completed after the general service is debugged normally. Subsequently, only the extended service development and debugging need to be carried out separately, without the need to repeatedly develop and debug the general service part, which facilitates secondary development of the product.

[0010] In addition, the general business functions are designed in the EDA software using a hardware description language, and a hardware packaging file is obtained, including: designing the timing logic of each interface using a hardware description language in the EDA software environment; performing behavioral simulation on the timing logic design of each interface; after the behavioral simulation is normal, packaging the timing logic design of each interface in the form of encapsulated IP or netlist to obtain a hardware packaging file.

[0011] In addition, after the behavioral simulation is normal, it also includes: hardware testing of the timing logic design of each interface; after the hardware test is normal, the timing logic design of each interface is packaged in the form of encapsulated IP or netlist to obtain a hardware packaging file.

[0012] In addition, an extended service is designed in a graphical design tool, and a graphically designed IP or netlist is generated, including: designing the extended service in a graphically connected manner of basic modules in the graphical design tool according to the interface signals and timing logic of the hardware package file; performing offline simulation on the graphical design; and generating the graphically designed IP or netlist in the graphical design tool after the offline simulation is normal.

[0013] In addition, performing offline simulation on the graphical design includes: designing a test stimulus waveform in a graphical environment, and performing offline simulation on the graphical design using the test stimulus waveform.

[0014] In addition, EDA software includes at least Vivado; graphical design tools include at least System Generator.

[0015] In addition, the general service includes at least the timing logic of each interface; the extended service includes at least the logical interconnection of each interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments, and the pictures in the drawings do not constitute proportional limitations.

[0017] Figure 1 is a flow chart of an FPGA development method according to an embodiment of the present invention;

[0018] Figure 2 is a flow chart of a general service encapsulation design according to an embodiment of the present invention;

[0019] Figure 3 is a flow chart of extended service development according to an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of an FPGA programming architecture according to an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of another FPGA programming architecture according to an embodiment of the present invention;

[0022] Figure 6 FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the embodiments of the present invention to help readers better understand the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0024] The following embodiments are divided for the convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.

[0025] The embodiment of the present invention relates to a FPGA development method, such as Figure 1 As shown, including:

[0026] Step 101 : Divide FPGA program design into general services and extended services according to service types.

[0027] Specifically, general services can be hardware-related functions, such as the timing logic of various interfaces. Extended services can be other specific service-related functions other than hardware-related functions, such as algorithm- or computation-related functions. The above FPGA program design partitioning strategy is only one specific partitioning method. In actual applications, FPGA program design can be partitioned using different partitioning strategies. Simply ensuring that services that are difficult to implement using hardware description languages ​​can be designed using graphical design tools can reduce the design difficulty.

[0028] Step 102: Design general business functions in EDA software using hardware description language and obtain hardware packaging files.

[0029] The specific general business package design process is as follows Figure 2 As shown in the figure, based on a general hardware PCB design, each hardware interface is identified. The timing logic for each hardware interface is designed using a hardware description language within the EDA software environment. Behavioral simulation is then performed on each interface logic design. Once the behavioral simulation is successful, the timing logic design for each hardware interface is tested in hardware. After confirming that the hardware tests for each interface are normal, the hardware interface design is packaged in the EDA software using IP or netlists. The hardware package file is then output, along with the necessary interface signal definitions and timing requirements.

[0030] EDA software can be Vivado, which is one of the main development tools. It is an integrated design environment released by FPGA manufacturer Xilinx in 2012. It supports multiple data input methods, embedded synthesizer and simulator, and can complete the entire development process from new project creation, design input, analysis and synthesis, constraint input to design implementation, and finally generate bitstream and download it to FPGA.

[0031] Step 103: Design the extended service in a graphical design tool and generate a graphically designed IP or netlist.

[0032] Specific expansion business development process such as Figure 3 As shown in the figure, based on the underlying hardware package interface signals and timing, as well as specific business function requirements, the design is performed by graphically connecting basic modules in a graphical design tool. During and after the design process, the necessary test stimulus waveforms can be designed in the graphical environment and offline simulation can be performed on the graphical design. Once the offline simulation is confirmed to be normal, the graphical design is generated into an IP or netlist in the graphical design tool.

[0033] A graphical design tool can be System Generator, a DSP design tool that runs within Simulink. It uses the Xilinx DSP Blockset for Simulink to generate a highly optimized netlist of DSP building blocks. The Xilinx DSP Blockset can be accessed through the Simulink Library Browser, which can be launched from the standard MATLAB toolbar. Over 90 DSP building blocks are available for building DSP systems, including FIR filters, FFTs, FEC cores, embedded processing cores, memories, arithmetic blocks, logic blocks, and bit-wise blocks. Each block is cycle-accurate and bit-accurate, and can be individually configured for latency, area and speed performance optimization, number of I / O ports, quantization, and rounding.

[0034] Because Simulink is built on MATLAB, System Generator can use the full MATLAB language for input signal generation and output analysis. You can use the From-Workspace and To-Workspace blocks in the Simulink Source and Sink library to read input signals from MATLAB variables (From-Workspace) or store partial signal results in MATLAB variables (To-Workspace). Furthermore, you can set many System Generator parameters through MATLAB variables. This allows you to implement complex design customization simply by updating the MATLAB script containing all these variables (you can assign MATLAB functions to the model and call them before opening it, or even before or after the simulation starts).

[0035] Step 104 , importing the graphically designed IP or netlist into the EDA software project containing the hardware package file, and performing synthesis, layout and routing, and generating a bitstream file.

[0036] Specifically, the IP or netlist file output by the graphical design tool (System Generator) can be imported into the EDA software (Vivado) project containing the hardware package file to form a complete design. Synthesis, placement and routing, and bitstream file generation are then performed using the EDA software (Vivado). Finally, the overall design is tested on hardware. If any issues are found during the test, the graphical design in the graphical design tool (System Generator) needs to be adjusted accordingly. Once the hardware test is confirmed to be normal, the overall design and debugging are complete.

[0037] It should be noted that the EDA software in the present invention is not limited to Vivado, and the graphical design tool is not limited to SystemGenerator, and can be adjusted according to the development environment and the specific application field of FPGA.

[0038] Compared to the prior art, the embodiments of the present invention divide FPGA programming into general services and extended services. General services have a certain degree of universality, while extended services are implemented on the basis of general services and usually require the support of computing algorithms. General service functions are designed in EDA software using hardware description languages, and the extended services are designed in graphical design tools. Designers only need to understand the relevant algorithms for the extended services to design and implement them graphically, which lowers the design threshold. In addition, the FPGA programming is divided, and hardware packaging is completed after the general service is debugged normally. Subsequently, only the extended service development and debugging need to be carried out separately, without the need to repeatedly develop and debug the general service part, which facilitates secondary development of the product.

[0039] In addition, the FPGA programming architecture of the present invention is specifically described by taking a general hardware platform in the field of power electronics real-time simulation as an example. Figure 4 As shown, at the underlying hardware interface logic layer, hardware description languages ​​are used in EDA software to design and encapsulate the interface logic (such as PCIe, analog output AO, analog input AI, digital input DI, digital output DO, and Aurora interface). Subsequent functional development, such as specific power electronic converter topologies and the logical interconnections with various interfaces, can be designed in a graphical environment. For example, in the communications field, for general hardware platforms, signal modulation and demodulation and related processing algorithms can be designed in a graphical environment. In the financial field, for example, real-time data processing algorithms can be designed in a graphical environment.

[0040] For ease of understanding, the above examples illustrate specific implementations of the FPGA programming architecture of the present invention in several different fields. However, the above examples do not specifically limit the specific application fields of the present invention or the programs designed using a graphical environment in the present invention. The present invention is applicable to any field where FPGAs are used. Within the application field, algorithms that are difficult to program using hardware description languages ​​can be designed using graphical environments to reduce their design difficulty.

[0041] The steps of the various methods above are divided only for the purpose of clear description. During implementation, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0042] An embodiment of the present invention also relates to an FPGA programming architecture, comprising: a hardware design module for designing general business functions in EDA software using a hardware description language and obtaining a hardware packaging file; a business function design module for designing extended business in a graphical design tool and generating a graphically designed IP or netlist; wherein general business and extended business are divisions of FPGA programming based on business types; and an integration module for importing the graphically designed IP or netlist into an EDA software project containing a hardware packaging file, and performing synthesis, layout and routing, and generating a bitstream file.

[0043] FPGA programming architecture is as follows Figure 5 As shown, based on the general hardware PCB design, the logic of the underlying hardware interface is designed in sequence in EDA software (such as Vivado), including interface logic A, interface logic B, interface logic C, interface logic D, interface logic E, etc., and the signals and timing of each interface are reasonably planned, which serves as the design interface of the graphical design environment (such as System Generator). In this way, the design related to the hardware can be encapsulated. At the same time, the function development related to the specific business can be carried out in a graphical design environment. The designer only needs to understand the relevant algorithms of the extended business and can design and implement them in a graphical way, which lowers the design threshold. In addition, the FPGA program design is divided, and the hardware encapsulation is completed after the general business debugging is normal. Subsequently, only the extended business development and debugging need to be carried out separately, without the need to repeatedly develop and debug the general business part, which facilitates the secondary development of the product.

[0044] It is not difficult to find that this embodiment is associated with the method embodiment, and this embodiment can be implemented in conjunction with the method embodiment. The relevant technical details mentioned in the method embodiment are still valid in this embodiment, and to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the method embodiment.

[0045] It is worth noting that all modules involved in this embodiment are logical modules. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovations of the present invention, this embodiment does not include units that are not closely related to solving the technical problems proposed by the present invention. However, this does not mean that other units do not exist in this embodiment.

[0046] The embodiment of the present invention also relates to an electronic device, such as Figure 6 As shown, it includes at least one processor 601; and a memory 602 that is communicatively connected to the at least one processor 601; wherein the memory 602 stores instructions that can be executed by the at least one processor 601, and the instructions are executed by the at least one processor 601 to enable the at least one processor 601 to execute the FPGA development method in the above embodiment.

[0047] The memory 602 and processor 601 are connected using a bus. The bus can include any number of interconnected buses and bridges, connecting various circuits of one or more processors 601 and memory 602. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits. These are all well known in the art and are therefore not described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor 601 is transmitted over a wireless medium via an antenna. Furthermore, the antenna receives data and transmits it to the processor 601.

[0048] The processor 601 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. The memory 602 can be used to store data used by the processor 601 when performing operations.

[0049] The present invention also relates to a computer-readable storage medium storing a computer program, which implements the above method embodiment when executed by a processor.

[0050] That is, those skilled in the art will understand that all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program, which is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0051] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A FPGA development method, characterized in that: include: FPGA programming is divided into general services and extended services according to service types; general services are hardware functions, including the timing logic of each interface; extended services are other service functions other than the hardware functions, including algorithm functions or calculation functions; Designing the general business functions in EDA software using hardware description language and obtaining hardware packaging files; Designing the extended service in a graphical design tool and generating a graphically designed IP or netlist; The graphically designed IP or netlist is imported into the EDA software project containing the hardware package file, and synthesis, layout and routing are performed, and a bitstream file is generated.

2. The FPGA development method according to claim 1, wherein: The general business functions are designed in EDA software using a hardware description language, and a hardware package file is obtained, including: Design the timing logic of each interface using hardware description language in the EDA software environment; Performing behavioral simulation on the sequential logic design of each interface; After the behavior simulation is normal, the sequential logic design of each interface is encapsulated in the form of IP encapsulation or netlist to obtain a hardware encapsulation file.

3. The FPGA development method according to claim 2, wherein: After the behavior simulation is normal, the method further includes: Performing hardware testing on the sequential logic design of each interface; After the hardware is actually tested to be normal, the sequential logic design of each interface is packaged in the form of IP or netlist to obtain a hardware packaging file.

4. The FPGA development method according to claim 2, wherein: The step of designing the extended service in a graphical design tool and generating a graphically designed IP or netlist includes: Designing the extended service by graphically connecting basic modules in a graphical design tool according to the interface signals of the hardware package file and the timing logic; Perform offline simulation of graphical designs; After the offline simulation is normal, the IP or netlist of the graphical design is generated in the graphical design tool.

5. The FPGA development method according to claim 4, wherein: The offline simulation of the graphical design includes: A test stimulus waveform is designed in a graphical environment, and the graphical design is simulated offline using the test stimulus waveform.

6. The FPGA development method according to claim 1, wherein: The EDA software at least includes Vivado; the graphical design tool at least includes System Generator.

7. An FPGA programming architecture, characterized in that: include: The hardware design module is used to design general business functions in EDA software using hardware description language and obtain hardware packaging files; A service function design module is used to design extended services in a graphical design tool and generate IP or netlists for the graphical design. The general services and extended services are the divisions of FPGA programming based on service types. General services are hardware functions, including the timing logic of each interface. Extended services are other service functions other than the hardware functions, including algorithmic functions or computational functions. The integration module is used to import the IP or netlist of the graphical design into the EDA software project containing the hardware packaging file, and perform synthesis, layout and routing, and generate a bitstream file.

8. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the FPGA development method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the FPGA development method according to any one of claims 1 to 6 is implemented.

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