Pixel Circuit, Row Driving Circuit and Driving Method of an Active Electroluminescent Display

Abstract

The present invention discloses a pixel circuit, a row driving circuit and a driving method for an active electroluminescent display. The pixel circuit includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a driving transistor, an organic light-emitting diode, a storage capacitor and a coupling capacitor. The present invention also discloses a driving method for the pixel circuit. For the first frame, the programming goes through the initialization, threshold voltage latching, data loading and organic light-emitting diode light-emitting stages. For the second to Nth frames, the driving process only goes through the data loading and organic light-emitting diode light-emitting stages. The present invention also discloses a row driving circuit corresponding to the scanning switch and the light-emitting control signal of the pixel driving circuit. The present invention can not only compensate for the display non-uniformity caused by the threshold voltage drift of the driving transistor, but also greatly reduce the switching power consumption of the transistor, and the larger N is, the more obvious the reduced dynamic power consumption is.

Description

Technical Field

[0001] The present invention relates to the field of pixel driving of active electroluminescent displays, and particularly relates to a pixel circuit, a row driving circuit and a driving method for an active electroluminescent display. Background Art

[0002] AMOLED display technology has the advantages of being thin, light, fast response speed, low power consumption, high contrast, high luminous brightness, etc., and has been widely used in portable electronic products such as mobile phones. With the development of display technology, consumers have higher and higher requirements for display performance, especially the display refresh rate. A high refresh rate can bring a better experience to consumers. AMOLED displays also have the advantage of fast response speed and are suitable for use on high refresh rate display panels.

[0003] However, for portable electronic products such as mobile phones, due to the slow progress of current battery energy density technology, it is difficult to increase the battery capacity. To improve the user experience (videos, games, etc.), a high refresh rate is adopted. In addition, to save power consumption, the low leakage characteristics of oxide TFTs are utilized to achieve a wide frequency application of 1 - 120Hz and realize the switching between high and low frequencies. This is the traditional LTPO (LTPS + Oxide) technology. However, there is a high power consumption under high refresh operation, which is an industry pain point of energy consumption anxiety.

[0004] The AMOLED pixel driving circuit is composed of thin film transistors (TFTs). Due to the manufacturing process and device characteristics of TFTs, the characteristics of TFTs at different positions in the display panel are different. After the same device is powered on, its characteristics will also shift. The shift of TFT characteristics will cause the OLED display brightness to change, resulting in uneven display. Therefore, compensating the characteristics of TFTs through compensation design can reduce the unevenness of AMOLED displays. Currently, common compensation methods include external compensation and internal compensation. External compensation is to collect the working current of each pixel at a specific data voltage through an external chip, compare it with the standard working current, and perform compensation by changing the input of the data voltage. Internal compensation is to collect the threshold voltage of the driving transistor through the design of the pixel circuit and compensate it to improve the uniformity of AMOLED displays.

[0005] The existing LTPO pixel circuit has four working stages: I (initialization stage), C (compensation stage), D (data writing stage), and E (light emitting stage). Each pixel needs to go through these four stages in each frame time, and each stage will consume a certain amount of dynamic power consumption. In the high refresh rate display mode, more working stages need to be experienced per unit time, which will bring higher power consumption. Therefore, it is necessary to design a new LTPO pixel circuit and driving method that can both compensate for the non-uniformity of TFTs and reduce the AMOLED dynamic power consumption. Summary of the Invention

[0006] In order to overcome the above-mentioned disadvantages and deficiencies of the prior art, the first object of the present invention is to provide a pixel circuit and a driving method for an active electroluminescent display;

[0007] The second object of the present invention is to provide a row driving circuit and a driving method for providing a scanning control signal for the pixel circuit;

[0008] The third object of the present invention is to provide a row driving circuit and a driving method for providing a light emission control signal for the pixel circuit.

[0009] The first object of the present invention is achieved by the following technical solutions:

[0010] A pixel circuit for an active electroluminescent display includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a driving transistor, an organic light emitting diode, a storage capacitor, and a coupling capacitor;

[0011] The drain of the first switching transistor is connected to the data line Data, the source of the first switching transistor is connected to the first electrode plate of the storage capacitor, the first electrode plate of the coupling capacitor, and the source of the second switching transistor, and the gate of the first switching transistor is connected to the data scan control line Scan;

[0012] The drain of the second switching transistor is connected to the power supply VDD, and the gate of the second switching transistor is connected to the first scan control line;

[0013] The drain of the third switching transistor is connected to the ground VSS, the source of the third switching transistor is connected to the second electrode plate of the coupling capacitor, the source of the fourth switching transistor, and the gate of the driving transistor, and the gate of the third switching transistor is connected to the second scan control line;

[0014] The drain of the fourth switching transistor is connected to the source of the fifth switching transistor and the drain of the driving transistor, and the gate of the fourth switching transistor is connected to the third scan control line;

[0015] The drain of the fifth switching transistor is connected to the drain of the sixth switching transistor and the anode of the OLED, and the gate of the fifth switching transistor is connected to the light emission scan control line;

[0016] The source of the sixth switching transistor is connected to the ground, and the gate of the sixth switching transistor is connected to the light emission scan control line;

[0017] The cathode of the OLED is grounded.

[0018] A driving method for the pixel circuit divides the display time of the pixel circuit into multiple large cycles, and each large cycle includes N frame cycles;

[0019] The driving of the first frame in the N frame cycles includes an initialization stage, a threshold voltage latching stage, a data loading stage, and a light emitting stage;

[0020] For the second to the Nth frames, the driving method includes a data loading stage and a light emitting stage.

[0021] Furthermore, the driving of the first frame in the N frame cycles includes an initialization stage, a threshold voltage latching stage, a data loading stage, and a light emitting stage;

[0022] Specifically:

[0023] Initialization stage: The third scan control line S3 and the data scan control line Scan of the nth row of pixels are given low levels, and the first switching transistor and the fourth switching transistor are turned off; the first scan control line S1, the second scan control line S2, and the light emitting scan control line of the nth row of pixels are given high levels, the second switching transistor, the third switching transistor, and the sixth switching transistor are turned on, the fifth switching transistor is turned off, the first plate of the storage capacitor is charged to the power supply voltage, the second plate of the coupling capacitor is discharged to the ground voltage, and the OLED anode is connected to the ground;

[0024] Threshold voltage latching stage: The second scan control line S2 and the data scan control line Scan of the nth row of pixels are given low levels, and the first switching transistor and the third switching transistor are turned off; the first scan control line, the third scan control line, and the light emitting scan control line EM of the nth row of pixels are given high levels, the second switching transistor, the fourth switching transistor, and the sixth switching transistor are turned on, the fifth switching transistor is turned off, the first plate of the storage capacitor maintains the power supply voltage, and the second plate of the coupling capacitor is charged to the sum of the power supply voltage and the threshold voltage of the driving transistor through the driving transistor, realizing the threshold voltage latching of the driving transistor;

[0025] Data loading stage: The first scan control line, the second scan control line, and the third scan control line of the nth row of pixels are given low levels, and the second switching transistor, the third switching transistor, and the fourth switching transistor are turned off; the data scan control line and the light emitting scan control line EM of the nth row of pixels are given high levels, the first switching transistor and the sixth switching transistor are turned on, the fifth switching transistor is turned off, and the data line loads the data voltage of the nth row of pixels;

[0026] Emission stage: The first scan control line, the second scan control line, the third scan control line, the data scan control line, and the emission scan control line of the n-th row of pixels are set to low level. The first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the sixth switching transistor are turned off, and the fifth switching transistor is turned on; the OLED starts to emit light.

[0027] Furthermore, for the 2nd to Nth frames, the driving method includes a data loading stage and an emission stage, specifically:

[0028] Data loading stage: The first scan control line, the second scan control line, and the third scan control line of the n-th row of pixels are set to low level. The second switching transistor, the third switching transistor, and the fourth switching transistor are turned off; the data scan control line and the emission scan control line of the n-th row of pixels are set to high level. The first switching transistor and the sixth switching transistor are turned on, and the fifth switching transistor is turned off. The data line loads the data voltage of the n-th row of pixels;

[0029] Emission stage: The first scan control line, the second scan control line, the third scan control line, the data scan control line, and the emission scan control line of the n-th row of pixels are set to low level. The first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the sixth switching transistor are turned off, and the fifth switching transistor is turned on; the OLED starts to emit light.

[0030] The second object of the present invention is achieved through the following technical solutions:

[0031] A row driving circuit is used to drive the first scan control line, the second scan control line, the third scan control line, and the data scan control line in the pixel circuit. In the first frame, the first scan control signal, the second scan control signal, the third scan control signal, and the data scan control signal are output. In the 2nd to Nth frames, only the data scan control signal is output;

[0032] It includes: an input stage, an inversion stage, a data scan output stage, and a compensation scan output stage. The control signals of the row driving circuit include a first clock control line, a second clock control line, an input control line, a power enable control line, a data scan control line, a data scan enable control line, and a first scan enable control line.

[0033] Further, the input stage is composed of a first scan switch transistor and a second scan switch transistor. The drain of the first scan switch transistor is connected to the drain of the second scan switch transistor, the first plate of the scan storage capacitor, the gates of the third scan switch transistor and the fourth scan switch transistor. The source of the first scan switch transistor is connected to the input control line, the gate of the first scan switch transistor is connected to the second clock control line. The source of the second scan switch transistor is connected to the drain of the seventh scan switch transistor, the gate of the first driving transistor and the first plate of the bootstrap capacitor. The gate of the second scan switch transistor is connected to the first clock control line;

[0034] The reverse stage is composed of a third scan switch transistor, a fourth scan switch transistor, a seventh scan switch transistor and a scan storage capacitor. The drain of the third scan switch transistor is connected to the drain of the fourth scan switch transistor, the gate of the seventh scan switch transistor, the gates of the second driving transistor, the third driving transistor and the fourth driving transistor. The source of the third scan switch transistor is connected to the power supply, the source of the fourth scan switch transistor is connected to the ground, the source of the seventh scan switch transistor is connected to the ground, and the second plate of the scan storage capacitor is connected to the ground;

[0035] The data scan output stage is composed of a first driving transistor, a second driving transistor and a bootstrap capacitor. The drain of the first driving transistor is connected to the second clock control line, the source of the first driving transistor is connected to the data scan control line Scan. The source of the second driving transistor is connected to the ground, and the gate of the second driving transistor is connected to the drain of the third scan switch transistor, the drain of the fourth scan switch transistor, the gate of the seventh scan switch transistor, the gate of the third driving transistor and the gate of the fourth scan switch transistor;

[0036] The compensation scan output stage is composed of a fifth scan switch transistor, a sixth scan switch transistor, a third drive transistor, a fourth drive transistor, a fifth drive transistor, and a sixth drive transistor. The drain of the fifth scan switch transistor is connected to the drain of the sixth scan switch transistor, the gates of the fifth drive transistor and the sixth drive transistor. The source of the fifth scan switch transistor is connected to the power supply VDD. The gate of the fifth scan switch transistor is connected to the data scan control line Scan. The source of the sixth scan switch transistor is connected to the ground. The drain of the third drive transistor is connected to the first enable scan control line. The source of the third drive transistor is connected to the power supply enable control line. The source of the fourth drive transistor is connected to the ground. The gate of the fourth drive transistor is connected to the drain of the third scan switch transistor, the drain of the fourth scan switch transistor, the gate of the seventh scan switch transistor, the gate of the second drive transistor, and the gate of the third switch transistor. The drain of the fifth drive transistor is connected to the data scan enable control line. The source of the fifth drive transistor is connected to the power supply enable control line. The gate of the fifth drive transistor is connected to the drain of the fifth scan switch transistor, the drain of the sixth scan switch transistor, and the gate of the sixth drive transistor. The source of the sixth drive transistor is connected to the ground.

[0037] A method for driving the row driving circuit described above, comprising:

[0038] Frame 1: The power supply enable control line is given a low level;

[0039] Including a signal initialization stage, a signal output stage, and a signal reset stage;

[0040] Frames 2 to N: The power supply enable control line is given a high level;

[0041] Including a signal initialization stage, in which the first scan control line outputs a high potential;

[0042] A signal output stage, in which the scan enable control line outputs a high potential;

[0043] A signal reset stage.

[0044] Furthermore, in Frame 1: The power supply enable control line is given a low level; including a signal initialization stage, a signal output stage, and a signal reset stage, specifically:

[0045] Signal input initialization stage: The first clock control line is given a high level, and the second scanning switch transistor is turned on; the second clock control line is given a low level, and the first scanning switch transistor is turned on; the input control line is given a high level, and the drain of the first scanning switch transistor changes from a low potential to a high potential, and the first plate of the scanning storage capacitor is charged to a high potential, the third scanning switch transistor is turned off, the fourth scanning switch transistor is turned on, the drains of the third scanning switch transistor and the fourth switch transistor output a low potential, the seventh scanning switch transistor is turned off, the second driving transistor is turned off, the third driving transistor is turned on, the fourth driving transistor is turned off, and the first scan enable control line outputs a low potential; the first plate of the bootstrap capacitor is charged to a high potential, the first driving transistor is turned on, the data scan control line outputs a low potential, the fifth scanning switch transistor is turned on, the sixth scanning switch transistor is turned off, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output a high potential, the fifth driving transistor is turned off, the sixth scanning switch transistor is turned on, and the data scan enable control line outputs a low potential;

[0046] Signal output stage: The first clock control line is given a low level, and the second scanning switch transistor is turned off; the second clock control line is given a high level, the first scanning switch transistor is turned off, the first plate of the bootstrap capacitor is bootstrapped to an even higher high potential, the data scan control line outputs a high potential, the fifth scanning switch transistor is turned off, the sixth scanning switch transistor is turned on, the drains of the fifth switch transistor and the sixth switch transistor output a low potential, the fifth driving transistor is turned on, the sixth switch transistor is turned off, and the data scan enable control line outputs a low potential.

[0047] Signal reset stage: The first clock control line is given a high level, and the second scanning switch transistor is turned on; the second clock control line is given a low level, the first scanning switch transistor is turned on, the first plate of the storage capacitor discharges to a low level, the third switch transistor is turned on, the fourth switch transistor is turned off, the drains of the third scanning switch transistor and the fourth scanning switch transistor output a high potential, the seventh scanning switch transistor is turned on, the first plate of the bootstrap capacitor discharges to a low level, the third driving transistor is turned off, the fourth driving transistor is turned on, the first scan control line outputs a low potential, the first driving transistor is turned off, the second driving transistor is turned on, the data scan control line outputs a low potential, the fifth scanning switch transistor is turned on, the sixth scanning switch transistor is turned off, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output a high potential, the fifth driving transistor is turned off, the sixth driving transistor is turned on, and the data scan enable control line outputs a low potential.

[0048] Further, for the 2nd to Nth frames: The power enable control line is given a high level; it includes a signal initialization stage, in which the first scan control line outputs a high potential; a signal output stage, in which the scan enable control line outputs a high potential; a signal reset stage, specifically:

[0049] Frames 2 to N: The power enable control line is set to high level;

[0050] Signal input initialization stage: The first clock control line is set to high level, and the second scanning switch transistor is turned on; The second clock control line is set to low level, and the first scanning switch transistor is turned on; The input control line is set to high level, and the drain of the first scanning switch transistor changes from low potential to high potential, and the first plate of the scanning storage capacitor is charged to high potential. The third scanning switch transistor is turned off, the fourth scanning switch transistor is turned on, the drains of the third scanning switch transistor and the fourth scanning switch transistor output low potential, the seventh scanning switch transistor is turned off, the second driving transistor is turned off, the third driving transistor is turned on, the fourth driving transistor is turned off, and the first scanning control line outputs high potential; The first plate of the bootstrap capacitor is charged to high potential, the first driving transistor is turned on, the data scanning control line outputs low potential, the fifth scanning switch transistor is turned on, the sixth scanning switch transistor is turned off, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output high potential, the fifth driving transistor is turned off, the sixth switching transistor is turned on, and the data scanning enable control line outputs low potential;

[0051] Signal output stage: The first clock control line is set to low level, and the second scanning switch transistor is turned off; The second clock control line is set to high level, the first scanning switch transistor is turned off, the first plate of the bootstrap capacitor is bootstrapped to an even higher high potential, the data scanning control line outputs high potential, the fifth scanning switch transistor is turned off, the sixth scanning switch transistor is turned on, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output low potential, the fifth driving transistor is turned on, the sixth scanning switch transistor is turned off, and the data scanning enable control line outputs high potential;

[0052] Signal reset stage: The first clock control line is set to high level, and the second scanning switch transistor is turned on; The second clock control line is set to low level, the first scanning switch transistor is turned on, the first plate of the storage capacitor discharges to low potential, the third scanning switch transistor is turned on, the fourth scanning switch transistor is turned off, the drains of the third scanning switch transistor and the fourth scanning switch transistor output high potential, the seventh scanning switch transistor is turned on, the first plate of the bootstrap capacitor discharges to low potential, the third driving transistor is turned off, the fourth driving transistor is turned on, the first scanning control line outputs low potential, the first driving transistor is turned off, the second driving transistor is turned on, the data scanning control line outputs low potential, the fifth scanning switch transistor is turned on, the sixth scanning switch transistor is turned off, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output high potential, the fifth driving transistor is turned off, the sixth driving transistor is turned on, and the data scanning enable control line outputs low potential.

[0053] The third object of the present invention is achieved by the following technical solutions:

[0054] A row driving circuit is used to provide a light-emitting scanning control signal for the pixel circuit and transmit it to the pixel circuit through a light-emitting scanning control line;

[0055] It includes a first light-emitting switching transistor, a second light-emitting switching transistor, a third light-emitting switching transistor, a fourth light-emitting switching transistor, a fifth light-emitting switching transistor, a first light-emitting driving transistor, a second light-emitting driving transistor, a light-emitting bootstrap capacitor, and a light-emitting storage capacitor.

[0056] Furthermore, the specific connection method is as follows:

[0057] The drain of the first light-emitting switching transistor is connected to the first plate of the light-emitting storage capacitor, the gates of the first light-emitting driving transistor and the second light-emitting driving transistor; the source of the first light-emitting switching transistor is connected to the light-emitting input control line EVIN and the source of the second light-emitting switching transistor; the gate of the first light-emitting switching transistor is connected to the first light-emitting clock control line and the gate of the second light-emitting switching transistor;

[0058] The drain of the second light-emitting switching transistor is connected to the gates of the third light-emitting switching transistor, the fourth light-emitting switching transistor, the drain of the fifth light-emitting switching transistor, and the first plate of the light-emitting bootstrap capacitor; the source of the second light-emitting switching transistor is connected to the light-emitting input control line EVIN;

[0059] The drain of the third light-emitting switching transistor is connected to the drain of the fourth transistor, the second plate of the light-emitting bootstrap capacitor, and the trigger control line COUT; the source of the third light-emitting switching transistor is connected to the second light-emitting clock control line;

[0060] The source of the fourth light-emitting switching transistor is connected to the power supply VDD;

[0061] The source of the fifth light-emitting switching transistor is connected to the power supply VDD; the gate of the fifth light-emitting switching transistor is connected to the drains of the first light-emitting driving transistor, the second light-emitting driving transistor, and the light-emitting control scanning control line;

[0062] The source of the first light-emitting driving transistor is connected to the ground and the second plate of the light-emitting storage capacitor;

[0063] The source of the second light-emitting driving transistor is connected to the power supply VDD.

[0064] A driving method for the described driving circuit includes:

[0065] Initialization stage: The input control line outputs a low potential; the first light-emitting clock control line outputs a low potential, the first light-emitting switch transistor is turned on, the second light-emitting switch transistor is turned on, the first electrode plate of the light-emitting storage capacitor discharges to a low level, the first light-emitting driving transistor is turned off, the second light-emitting driving transistor is turned on, the light-emitting control scan control line outputs a high potential, the light-emitting bootstrap capacitor discharges to a low potential, the third light-emitting switch transistor is turned on, the fourth light-emitting switch transistor is turned off, the second clock control line outputs a high potential, and the trigger control line outputs a high level;

[0066] Trigger signal output stage: The input control line outputs a high potential; the first light-emitting clock control line outputs a high potential, the first light-emitting switch transistor is turned off, and the second light-emitting switch transistor is turned off; the second light-emitting clock control line outputs a low potential, and the trigger control line outputs a low level;

[0067] Reset stage: The first light-emitting clock control line outputs a low potential, the first light-emitting switch transistor is turned on, and the second light-emitting switch transistor is turned on; the input control line outputs a high potential, the light-emitting storage capacitor is charged to a high potential, the first light-emitting driving transistor is turned on, the second light-emitting switch transistor is turned off, the light-emitting control scan control line outputs a low level, and the light-emitting bootstrap capacitor is charged to a high potential; the second light-emitting clock control line outputs a high potential, the third light-emitting switch transistor is turned off, the second light-emitting switch transistor is turned on, the fifth light-emitting switch transistor is turned on, and the trigger control line outputs a high potential.

[0068] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0069] (1) The LTPO pixel circuit of the active organic light-emitting display of the present invention can not only compensate for the display non-uniformity caused by the threshold voltage drift of the driving transistor, but also directly perform data update and then the organic light-emitting diode emits light without going through the two stages of initialization and threshold voltage latching starting from the 2nd to the Nth frames, greatly reducing the switching power consumption of the transistor (a part of the dynamic power consumption), and the larger the N, the more dynamic power consumption is saved;

[0070] (2) The present invention is compatible with the traditional LTPO timing and can be selected to work in the traditional timing mode of the four stages of I / C / D / E;

[0071] (3) The driving circuit of the present invention has only 2 TFTs, reducing VDD and lowering the static power consumption. The driving circuit refers to the path through which the light-emitting current flows, that is, the loop from the power supply VDD to the ground VSS. Specifically, the pixel circuit includes VDD, D1 transistor, T5 transistor, light-emitting diode, and VSS;

[0072] (4) In the light-emitting process E of the present invention, only two switch transistors need to be controlled to switch. In low-frequency applications (for example, when only the light-emitting control of E is retained at 1 Hz);

[0073] (5) The row driving circuit structure and timing corresponding to this pixel circuit are simple, facilitating integration and the implementation of a narrow border design. Description of the Drawings

[0074] Figure 1 is a schematic diagram of an LTPO pixel circuit of the prior art;

[0075] Figure 2 is a pixel circuit diagram of an embodiment of the present invention;

[0076] Figure 3 is Figure 2 the timing diagram of control signals for the first frame and the second frame in a large period of the driving method of the pixel circuit;

[0077] Figure 4 is Figure 2 the timing diagram in multiple large periods of the driving method of the pixel circuit.

[0078] Figure 5 is Figure 2 the schematic diagram of the row driving circuit corresponding to the scan switch signal in

[0079] Figure 6 is Figure 5 the timing diagram corresponding to the scan switch row driving circuit of

[0080] Figure 7 is Figure 2 the schematic diagram of the row driving circuit corresponding to the light emission control signal in

[0081] Figure 8 is Figure 7 the timing diagram corresponding to the light emission control row driving circuit of Detailed Embodiments

[0082] The present invention will be further described in detail below in conjunction with embodiments, but the implementation manners of the present invention are not limited thereto.

[0083] As Figure 1 shown, the schematic diagram of the LTPO pixel circuit of the prior art includes a driving transistor D1, and switching transistors T1, T2, T3, T4, T5, and T6. Among the switching transistors, T1 and T2 are made of oxide TFTs, and their lower leakage current can preserve the critical signal level for a longer time. The other transistors are made of LTPS technology. Although this LTPO pixel circuit can compensate for the difference in TFT Vth and meet the requirement of reducing dynamic power consumption when the circuit operates at a low frequency, however, this LTPO pixel circuit needs to go through four stages, namely I (initialization stage), C (compensation stage), D (data writing stage), and E (light emission stage), in each frame, and each stage will consume a certain amount of dynamic power. Its dynamic power consumption is still relatively high at a high refresh rate.

[0084] A pixel circuit of an active electroluminescent display is disposed at a portion where scan lines in the form of rows providing control signals and batches of signal lines in the form of columns providing data signals cross each other.

[0085] As Figure 2 shown, a pixel circuit of an active electroluminescent display includes a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, a driving transistor D1, a storage capacitor C1, a coupling capacitor C2, a first scan control line S1[i] of the i-th row, a second scan control line S2[i] of the i-th row, a third scan control line S3[i] of the i-th row, a data scan control line Scan[i] of the i-th row, a light emission control line EM[i] of the i-th row, a power supply line VDD, a ground line VSS, a data line V DATA , and an organic light emitting diode OLED.

[0086] Each transistor includes a gate, a source, and a drain;

[0087] The drain of the first switching transistor T1 is connected to the data line V DATA , the source of the first switching transistor T1 is connected to the first electrode plate of the storage capacitor C2, the first electrode plate of the coupling capacitor C1, and the source of the second switching transistor T2, and the gate of the first switching transistor T1 is connected to the data scan control line SCAN[i]; 1 ≤ i ≤ I, where I is the total number of scan lines of the display screen;

[0088] The drain of the second switching transistor T2 is connected to the power supply VDD, the source of the second switching transistor T2 is connected to the source of the first transistor T1, the first electrode plate of the coupling capacitor C1, and the first electrode plate of the storage capacitor C2, and the gate of the second switching transistor T2 is connected to the first scan control line S1[i];

[0089] The drain of the third switching transistor T3 is connected to the ground VSS, the source of the third switching transistor T3 is connected to the second electrode plate of the coupling capacitor C1, the source of the fourth switching transistor T4, and the gate of the driving transistor, and the gate of the third switching transistor T3 is connected to the second scan control line S2[i];

[0090] The drain of the fourth switching transistor T4 is connected to the source of the fifth switching transistor T5 and the drain of the driving transistor D1, the source of the fourth switching transistor T4 is connected to the second electrode plate of the coupling capacitor C1 and the source of the third switching transistor T3, and the gate of the fourth switching transistor T4 is connected to the third scan control line S3[i];

[0091] The drain of the fifth switching transistor T5 is connected to the drain of the sixth switching transistor T6 and the OLED anode. The source of the fifth switching transistor T5 is connected to the drain of the fourth switching transistor T4 and the drain of the driving transistor D1. The gate of the fifth switching transistor T5 is connected to the emission scan control line EM;

[0092] The drain of the sixth switching transistor T6 is connected to the drain of the fifth switching transistor T5 and the OLED anode. The source of the sixth switching transistor T6 is connected to the ground VSS. The gate of the sixth switching transistor T6 is connected to the emission scan control line EM;

[0093] The cathode of the OLED is connected to the ground VSS.

[0094] As Figure 3 shown, a driving method for a pixel circuit of an active organic light-emitting display:

[0095] includes the following steps:

[0096] The programming method for the first frame of each large cycle is as follows:

[0097] (1) I (Initialization): The third scan control line S3 and the data scan control line Scan of the first-row pixels are set to low level, and the first switching transistor T1 and the fourth switching transistor T4 are turned off; the first scan control line S1, the second scan control line S2, and the emission scan control line EM of the first-row pixels are set to high level, the second switching transistor T2, the third switching transistor T3, and the sixth switching transistor T6 are turned on, the fifth switching transistor T5 is turned off, the first plate of the storage capacitor C2, i.e., point A, is charged to the power supply voltage VDD, the second plate of the coupling capacitor C1, i.e., point B, is discharged to the ground voltage VSS, and the OLED anode is connected to the ground.

[0098] (2) C (Threshold voltage latching): The second scan control line S2[i] and the data scan control line Scan[i] of the first-row pixels are set to low level, and the first switching transistor T1 and the third switching transistor T3 are turned off; the first scan control line S1[i], the third scan control line S3[i], and the emission scan control line EM[i] of the i-th row pixels are set to high level, the second switching transistor T2, the fourth switching transistor T4, and the sixth switching transistor T6 are turned on, the fifth switching transistor T5 is turned off, the first plate of the storage capacitor, point A, maintains the power supply voltage VDD, and the second plate of the coupling capacitor, point B, is charged to VDD + Vth through the driving transistor D1, where Vth is the threshold voltage of the driving transistor D1, thereby achieving the threshold voltage latching of the driving transistor D1.

[0099] (3) D (Data Loading): The first scan control line S1[i], the second scan control line S2[i], and the third scan control line S3[i] of the i-th row of pixels are set to low level, and the second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4 are turned off; the data scan control line and the light-emitting scan control line of the i-th row of pixels are set to high level, the first switching transistor T1 and the sixth switching transistor T6 are turned on, the fifth switching transistor T5 is turned off, and the point A of the first electrode plate of the coupling capacitor C1 changes from the power supply voltage to the data voltage Vdata, and the point B of the second electrode plate of the coupling capacitor C1 is coupled to Vdata + Vth.

[0100] (4) E (Light Emitting): The first scan control line S1[i], the second scan control line S2[i], the third scan control line S3[i], the data scan control line Scan[i], and the light-emitting scan control line EM[i] of the i-th row of pixels are set to low level, the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, the fourth switching transistor, and the sixth switching transistor are turned off, and the fifth switching transistor is turned on; the OLED starts to emit light.

[0101] Its current expression is:

[0102] I OLED = β(V gs - V th ) 2

[0103] = β(V th + V data - V DD - V th ) 2

[0104] = β(V data - V DD ) 2

[0105] Where μ n is the electron mobility; C OX is the capacitance of the insulating layer per unit area; W and L are the channel width and length of the driving transistor D1, respectively. It can be seen that the light-emitting current is independent of the threshold voltage of the driving transistor T5, that is, this circuit can compensate for the display non-uniformity caused by the threshold voltage drift of the driving transistor D1.

[0106] The programming method for the 2nd to Nth frames of each large cycle is as follows:

[0107] In each frame, there are only D (Data Loading) and E (Light Emitting).

[0108] During the data loading phase, the first electrode of the coupling capacitor C1 changes from the data voltage Vdata of the previous frame to the new data voltage Vdata’, and the second electrode of the coupling capacitor C1 is coupled to Vdata’ + Vth.

[0109] During the light emitting phase, its current expression is:

[0110] I OLED =β(V gs -V th ) 2

[0111] =β(V th +V data ’-V DD -V th ) 2

[0112] =β(V data ’-V DD ) 2

[0113] Where μ n is the electron mobility; C OX is the capacitance of the insulating layer per unit area; W and L are the channel width and length of the driving transistor D1 respectively. It can be seen that the light emitting current is independent of the threshold voltage of the driving transistor T5, that is, this circuit can compensate for the display non-uniformity caused by the threshold voltage drift of the driving transistor D1.

[0114] For the power consumption of AMOLED, it is divided into dynamic power consumption and static power consumption. Among them, the static power consumption is the current power consumption when the OLED emits light, and the dynamic power consumption is the switching power consumption of the scanning control signal and the charging and discharging power consumption of the capacitors in the pixel circuit. Since there are only I (initialization), C (threshold voltage latching), D (data loading) and E (light emitting) phases in the Nth frame, that is, there are the switching power consumption of all switching transistors and the charging and discharging power consumption of capacitors in the Nth frame, while there are only D (data loading) and E (light emitting) phases in the 2nd to Nth frames, that is, there are only the switching power consumption of transistors T1 and T6 and the charging and discharging power consumption of capacitors in the 2nd to Nth frames. If N is larger, the more dynamic power consumption can be saved.

[0115] This embodiment also provides a row driving circuit, such as Figure 3 、 Figure 4 and Figure 5As shown, it is used to provide the scan control signals required by the above pixel circuit, which are transmitted to the pixel circuit through the scan control lines. This row driver circuit can generate the required first scan control signal, second scan control signal, third scan control signal, and data scan control signal, and match the above driving method to output a driving timing that conforms to the pixel circuit. That is, in the first frame, the first scan control signal, second scan control signal, third scan control signal, and data scan control signal Scan are output, and only the data scan control signal is output from the second frame to the Nth frame;

[0116] This row driver circuit includes an input stage, an inversion stage, a data scan output stage, and a compensation scan output stage. The control signals of the row driver circuit include a first clock control line CLK1, a second clock control line CLK2, an input control line VIN, a power enable control line VDD-EN, a data scan control line Scan, a data scan enable control line Scan_EN, and a first scan enable control line S1_EN.

[0117] The input stage is composed of a first scan switch transistor GT1 and a second scan switch transistor GT2. The drain of the first scan switch transistor GT1 is connected to the drain of the second scan switch transistor GT2, the first plate of the scan storage capacitor GC2, the gate of the third scan switch transistor GT3, and the gate of the fourth scan switch transistor GT4. The source of the first scan switch transistor GT1 is connected to the input control line EVIN, the gate of the first scan switch transistor is connected to the second clock control line CLK2, the source of the second scan switch transistor is connected to the drain of the seventh scan switch transistor GT7, the gate of the first driving transistor GD1, and the first plate of the bootstrap capacitor. The gate of the second scan switch transistor is connected to the first clock control line CLK1;

[0118] The inversion stage is composed of a third scan switch transistor GT3, a fourth scan switch transistor GT4, a seventh scan switch transistor GT7, and a scan storage capacitor GC2. The drain of the third scan switch transistor GT3 is connected to the drain of the fourth scan switch transistor GT4, the gate of the seventh scan switch transistor GT7, the gate of the second driving transistor GD2, the gate of the third driving transistor GD3, and the gate of the fourth driving transistor GD4. The source of the third scan switch transistor GT3 is connected to the power supply, the source of the fourth scan switch transistor GT4 is connected to the ground, the source of the seventh scan switch transistor GT7 is connected to the ground, and the second plate of the scan storage capacitor GC2 is connected to the ground;

[0119] The data scan output stage is composed of a first driving transistor GD1, a second driving transistor GD2, and a bootstrap capacitor GC1. The drain of the first driving transistor is connected to the second clock control line CLK2, the source of the first driving transistor GD1 is connected to the data scan control line Scan, the source of the second driving transistor GD2 is connected to the ground, and the gate of the second driving transistor GD2 is connected to the drains of the third scan switch transistor GT3, the fourth scan switch transistor GT4, the gate of the seventh scan switch transistor GT7, the gates of the third driving transistor GD3 and the fourth scan switch transistor GT4;

[0120] The compensation scan output stage is composed of a fifth scan switch transistor GT5, a sixth scan switch transistor GT6, a third driving transistor GD3, a fourth driving transistor GD4, a fifth driving transistor GD5, and a sixth driving transistor GD6. The drain of the fifth scan switch transistor GT5 is connected to the drains of the sixth scan switch transistor GT6, the gate of the fifth driving transistor GD5, and the gate of the sixth driving transistor GD6. The source of the fifth scan switch transistor is connected to the power supply VDD, the gate of the fifth scan switch transistor GT5 is connected to the data scan control line, the source of the sixth scan switch transistor GT6 is connected to the ground, the drain of the third driving transistor GD3 is connected to the first enable scan control line, the source of the third driving transistor GD3 is connected to the power enable control line, the source of the fourth driving transistor is connected to the ground, the gate of the fourth driving transistor GD4 is connected to the drains of the third scan switch transistor GT3, the fourth scan switch transistor GT4, the gate of the seventh scan switch transistor GT7, the gate of the second driving transistor GD2, and the gate of the third scan switch transistor. The drain of the fifth driving transistor GD5 is connected to the data scan enable control line, the source of the fifth driving transistor GD5 is connected to the power enable control line, the gate of the fifth driving transistor GD5 is connected to the drains of the fifth scan switch transistor, the sixth scan switch transistor GT6, and the sixth driving transistor GD6, and the source of the sixth driving transistor GD6 is connected to the ground.

[0121] As Figure 6 shown, its driving method includes the first frame: the power enable control line is given a high level;

[0122] including a signal initialization stage, a signal output stage, and a signal reset stage;

[0123] The second to Nth frames: the power enable control line is given a low level;

[0124] including a signal initialization stage, in which the first scan control line outputs a high potential;

[0125] A signal output stage, in which the scan enable control line outputs a high potential;

[0126] Signal reset phase.

[0127] Furthermore:

[0128] The first frame: The power enable control line is set to high level; it includes a signal initialization phase, a signal output phase, and a signal reset phase, specifically:

[0129] Signal input initialization phase: The first clock control line is set to high level, and the second scanning switch transistor is turned on; the second clock control line is set to low level, and the first scanning switch transistor is turned on; the input control line is set to high level, and the drain of the first scanning switch transistor changes from low potential to high potential, and the first plate of the scanning storage capacitor is charged to high potential, the third scanning switch transistor is turned off, the fourth scanning switch transistor is turned on, the drains of the third scanning switch transistor and the fourth switch transistor output low potential, the seventh scanning switch transistor is turned off, the second driving transistor is turned off, the third driving transistor is turned on, the fourth driving transistor is turned off, and the first scanning enable control line outputs high potential; the first plate of the bootstrap capacitor is charged to high potential, the first driving transistor is turned on, the data scanning control line outputs low potential, the fifth scanning switch transistor is turned on, the sixth scanning switch transistor is turned off, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output high potential, the fifth driving transistor is turned off, the sixth scanning switch transistor is turned on, and the scanning enable control line outputs low potential;

[0130] Signal output phase: The first clock control line is set to low level, and the second scanning switch transistor is turned off; the second clock control line is set to high level, the first scanning switch transistor is turned off, the first plate of the bootstrap capacitor is bootstrapped to an even higher high potential, the data scanning enable control line outputs high potential, the fifth scanning switch transistor is turned off, the sixth scanning switch transistor is turned on, the drains of the fifth switch transistor and the sixth switch transistor output low potential, the fifth driving transistor is turned on, the sixth switch transistor is turned off, and the scanning enable control line outputs high potential.

[0131] Signal reset phase: The first clock control line is given a high level, and the second scan switch transistor is turned on; the second clock control line is given a low level, the first scan switch transistor is turned on, the first plate of the storage capacitor discharges to a low level, the third switch transistor is turned on, the fourth switch transistor is turned off, the drains of the third scan switch transistor and the fourth scan switch transistor output a high potential, the seventh scan switch transistor is turned on, the first plate of the bootstrap capacitor discharges to a low potential, the third drive transistor is turned off, the fourth drive transistor is turned on, the first scan control line Scan outputs a low potential, the first drive transistor is turned off, the second drive transistor is turned on, the data scan control line outputs a low potential, the fifth scan switch transistor is turned on, the sixth scan switch transistor is turned off, the drains of the fifth scan switch transistor and the sixth scan switch transistor output a high potential, the fifth drive transistor is turned off, the sixth drive transistor is turned on, and the scan enable control line outputs a low potential.

[0132] Frames 2 - N: The power enable control line is given a low level; it includes a signal initialization phase, a signal output phase, and a signal reset phase, specifically:

[0133] Signal input initialization phase: The first clock control line is given a high level, and the second scan switch transistor is turned on; the second clock control line is given a low level, the first scan switch transistor is turned on; the input control line is given a high level, the drain of the first scan switch transistor changes from a low potential to a high potential, the first plate of the scan storage capacitor is charged to a high potential, the third scan switch transistor is turned off, the fourth scan switch transistor is turned on, the drains of the third scan switch transistor and the fourth switch transistor output a low potential, the seventh scan switch transistor is turned off, the second drive transistor is turned off, the third drive transistor is turned on, the fourth drive transistor is turned off, and the first scan enable control line outputs a low potential; the first plate of the bootstrap capacitor is charged to a high potential, the first drive transistor is turned on, the data scan control line outputs a low potential, the fifth scan switch transistor is turned on, the sixth scan switch transistor is turned off, the drains of the fifth scan switch transistor and the sixth scan switch transistor output a high potential, the fifth drive transistor is turned off, the sixth scan switch transistor is turned on, and the scan enable control line outputs a low potential;

[0134] Signal output phase: The first clock control line is given a low level, and the second scan switch transistor is turned off; the second clock control line is given a high level, the first scan switch transistor is turned off, the first plate of the bootstrap capacitor is bootstrapped to an even higher high potential, the data scan enable control line outputs a high potential, the fifth scan switch transistor is turned off, the sixth scan switch transistor is turned on, the drains of the fifth switch transistor and the sixth switch transistor output a low potential, the fifth drive transistor is turned on, the sixth switch transistor is turned off, and the scan enable control line outputs a low potential.

[0135] Signal reset stage: The first clock control line is given a high level, and the second scanning switch transistor is turned on; the second clock control line is given a low level, the first scanning switch transistor is turned on, the first plate of the storage capacitor is discharged to a low level, the third switch transistor is turned on, the fourth switch transistor is turned off, the drains of the third and fourth scanning switch transistors output a high potential, the seventh scanning switch transistor is turned on, the first plate of the bootstrap capacitor is discharged to a low potential, the third driving transistor is turned off, the fourth driving transistor is turned on, the first scanning control line Scan outputs a low potential, the first driving transistor is turned off, the second driving transistor is turned on, the data scanning control line outputs a low potential, the fifth scanning switch transistor is turned on, the sixth scanning switch transistor is turned off, the drains of the fifth and sixth scanning switch transistors output a high potential, the fifth driving transistor is turned off, the sixth driving transistor is turned on, and the scan enable control line outputs a low potential.

[0136] As Figure 7 described, another embodiment of the present invention further provides a light-emitting control row driving circuit for providing the light-emitting control signals required by the above pixel circuit, which are transmitted to the pixel circuit through the scanning control line. This row driving circuit can generate the required light-emitting control scanning control signals and match the above driving method, and output corresponding scanning control signals in each frame;

[0137] This row driving circuit includes a first light-emitting switch transistor ET1, a second light-emitting switch transistor ET2, a third light-emitting switch transistor ET3, a fourth light-emitting switch transistor ET4, a fifth light-emitting switch transistor ET5, a first light-emitting driving transistor ED1, a second light-emitting driving transistor ED2, a light-emitting bootstrap capacitor EC1, and a light-emitting storage capacitor EC2.

[0138] There are two clock signals, namely the first light-emitting clock control line ECLK1 and the second light-emitting clock control line ECLK2; a light-emitting input control line EVIN, a power supply VDD, a trigger control line COUT, and a light-emitting control scanning control line EM.

[0139] Its specific connection method is as follows:

[0140] The drain of the first light-emitting switch transistor is connected to the first plate of the light-emitting storage capacitor, the gates of the first light-emitting driving transistor and the second light-emitting driving transistor; the source of the first light-emitting switch transistor is connected to the light-emitting input control line EVIN and the source of the second light-emitting switch transistor; the gate of the first light-emitting switch transistor is connected to the first light-emitting clock control line and the gate of the second light-emitting switch transistor;

[0141] The drain of the second light-emitting switching transistor is connected to the gates of the third light-emitting switching transistor, the fourth light-emitting switching transistor, the drain of the fifth light-emitting switching transistor, and the first plate of the light-emitting bootstrap capacitor; the source of the second light-emitting switching transistor is connected to the light-emitting input control line EVIN;

[0142] The drain of the third light-emitting switching transistor is connected to the drain of the fourth transistor, the second plate of the light-emitting bootstrap capacitor, and the trigger control line COUT; the source of the third light-emitting switching transistor is connected to the second light-emitting clock control line;

[0143] The source of the fourth light-emitting switching transistor is connected to the power supply VDD;

[0144] The source of the fifth light-emitting switching transistor is connected to the power supply VDD; the gate of the fifth light-emitting switching transistor is connected to the drains of the first light-emitting driving transistor, the second light-emitting driving transistor, and the light-emitting control scanning line EM;

[0145] The source of the first light-emitting driving transistor is connected to the ground and the second plate of the light-emitting storage capacitor;

[0146] The source of the second light-emitting driving transistor is connected to the power supply VDD.

[0147] As Figure 8 shown, the driving method includes:

[0148] Initialization stage: The input control line outputs a low potential; the first light-emitting clock control line outputs a low potential, the first light-emitting switching transistor is turned on, the second light-emitting switching transistor is turned on, the first plate of the light-emitting storage capacitor is discharged to a low level, the first light-emitting driving transistor is turned off, the second light-emitting driving transistor is turned on, the light-emitting control scanning line EM outputs a high potential, the light-emitting bootstrap capacitor is discharged to a low potential, the third light-emitting switching transistor is turned on, the fourth light-emitting switching transistor is turned off, the second clock control line outputs a high potential, and the trigger control line COUT outputs a high level;

[0149] Trigger signal output stage: The input control line outputs a high potential; the first light-emitting clock control line outputs a high potential, the first light-emitting switching transistor is turned off, the second light-emitting switching transistor is turned off; the second light-emitting clock control line outputs a low potential, and the trigger control line outputs a low level;

[0150] Reset stage: The first light-emitting clock control line outputs a low potential, the first light-emitting switch transistor is turned on, and the second light-emitting switch transistor is turned on; the input control line outputs a high potential, the light-emitting storage capacitor is charged to a high potential, the first light-emitting driving transistor is turned on, the second light-emitting switch transistor is turned off, the light-emitting control scan control line outputs a low level, and the light-emitting bootstrap capacitor is charged to a high potential; the second light-emitting clock control line outputs a high potential, the third light-emitting switch transistor is turned off, the second light-emitting switch transistor is turned on, the fifth light-emitting switch transistor is turned on, and the trigger control line outputs a high potential.

[0151] The connection manners of the above pixel circuit, scan line driving circuit, and light-emitting control line driving circuit are as follows: The nth row of pixel circuits requires the first scan control line, the second scan control line, the third scan control line, the light-emitting scan control line, and the data scan control line. Among them, the first scan control line of the pixel circuit is provided by the first scan control line of the (n - 1)th row driving circuit, the second scan control line of the pixel circuit is provided by the scan enable control line of the (n - 2)th row driving circuit, the third scan control line of the pixel circuit is provided by the scan enable control line of the (n - 1)th row driving circuit, the light-emitting scan control line of the pixel circuit is provided by the light-emitting control line driving circuit of the nth row, and the data scan control line of the pixel circuit is provided by the data scan control line of the nth row driving circuit.

[0152] The above embodiments are the preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the described embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A pixel circuit of an active electroluminescent display, characterized in that, It includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a driving transistor, an organic light-emitting diode, a storage capacitor, and a coupling capacitor; The drain of the first switching transistor is connected to the data line Data, the source of the first switching transistor is connected to the first electrode plate of the storage capacitor, the first electrode plate of the coupling capacitor, and the source of the second switching transistor, and the gate of the first switching transistor is connected to the data scan control line Scan; The drain of the second switching transistor is connected to the power supply VDD, and the gate of the second switching transistor is connected to the first scan control line; The drain of the third switching transistor is connected to the ground VSS, the source of the third switching transistor is connected to the second electrode plate of the coupling capacitor, the source of the fourth switching transistor, and the gate of the driving transistor, and the gate of the third switching transistor is connected to the second scan control line; The drain of the fourth switching transistor is connected to the source of the fifth switching transistor and the drain of the driving transistor, and the gate of the fourth switching transistor is connected to the third scan control line; The drain of the fifth switching transistor is connected to the drain of the sixth switching transistor and the anode of the OLED, and the gate of the fifth switching transistor is connected to the light-emitting scan control line; The source of the sixth switching transistor is connected to the ground, and the gate of the sixth switching transistor is connected to the light-emitting scan control line; The cathode of the OLED is grounded.

2. A driving method for the pixel circuit according to claim 1, characterized in that, The display time of the pixel circuit is divided into multiple large cycles, and each large cycle includes N frame cycles; The driving of the first frame in the N frame cycles includes an initialization stage, a threshold voltage latching stage, a data loading stage, and a light-emitting stage; For the 2nd to the Nth frames, the driving method includes a data loading stage and a light-emitting stage.

3. The driving method according to claim 2, characterized in that The driving of the first frame in the N frame cycles includes an initialization stage, a threshold voltage latching stage, a data loading stage, and a light-emitting stage; Specifically: Initialization stage: The third scan control line and the data scan control line Scan of the pixels in the nth row are set to low level, and the first switching transistor and the fourth switching transistor are turned off; the first scan control line, the second scan control line, and the light-emitting scan control line of the pixels in the nth row are set to high level, the second switching transistor, the third switching transistor, and the sixth switching transistor are turned on, the fifth switching transistor is turned off, the first electrode plate of the storage capacitor is charged to the power supply voltage, the second electrode plate of the coupling capacitor is discharged to the ground voltage, and the anode of the OLED is connected to the ground; Threshold voltage latching stage: The second scan control line and the data scan control line of the pixels in the nth row are set to low level, and the first switching transistor and the third switching transistor are turned off; the first scan control line, the third scan control line, and the light-emitting scan control line of the pixels in the nth row are set to high level, the second switching transistor, the fourth switching transistor, and the sixth switching transistor are turned on, the fifth switching transistor is turned off, the first electrode plate of the storage capacitor maintains the power supply voltage, and the second electrode plate of the coupling capacitor is charged to the sum of the power supply voltage and the threshold voltage of the driving transistor through the driving transistor, realizing the threshold voltage latching of the driving transistor; Data loading stage: The first scan control line, the second scan control line, and the third scan control line of the n-th row of pixels are set to low level, and the second switching transistor, the third switching transistor, and the fourth switching transistor are turned off; the data scan control line and the light-emitting scan control line of the n-th row of pixels are set to high level, the first switching transistor and the sixth switching transistor are turned on, the fifth switching transistor is turned off, and the data line loads the data voltage of the n-th row of pixels. Light-emitting stage: The first scan control line, the second scan control line, the third scan control line, the data scan control line, and the light-emitting scan control line of the n-th row of pixels are set to low level, the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the sixth switching transistor are turned off, and the fifth switching transistor is turned on. The OLED starts to emit light.

4. The driving method according to claim 2, characterized in that, For the 2nd to Nth frames, the driving method includes a data loading stage and a light-emitting stage, specifically: Data loading stage: The first scan control line, the second scan control line, and the third scan control line of the n-th row of pixels are set to low level, and the second switching transistor, the third switching transistor, and the fourth switching transistor are turned off; the data scan control line and the light-emitting scan control line of the n-th row of pixels are set to high level, the first switching transistor and the sixth switching transistor are turned on, the fifth switching transistor is turned off, and the data line loads the data voltage of the n-th row of pixels. Light-emitting stage: The first scan control line, the second scan control line, the third scan control line, the data scan control line, and the light-emitting scan control line of the n-th row of pixels are set to low level, the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the sixth switching transistor are turned off, and the fifth switching transistor is turned on. The OLED starts to emit light.

5. A row driving circuit, characterized in that, For driving the first scan control line, the second scan control line, the third scan control line, and the data scan control line in the pixel circuit as claimed in claim 1, the first scan control signal, the second scan control signal, the third scan control signal, and the data scan control signal are output in the first frame, and only the data scan control signal is output in the 2nd to Nth frames. It includes: an input stage, a reverse stage, a data scan output stage, and a compensation scan output stage. The control signals of the row driving circuit include a first clock control line, a second clock control line, an input control line, a power enable control line, a data scan control line, a data scan enable control line, and a first scan enable control line. The input stage is composed of a first scan switching transistor and a second scan switching transistor. The drain of the first scan switching transistor is connected to the drain of the second scan switching transistor, the first plate of the scan storage capacitor, the gates of the third scan switching transistor and the fourth scan switching transistor. The source of the first scan switching transistor is connected to the input control line, the gate of the first scan switching transistor is connected to the second clock control line, the source of the second scan switching transistor is connected to the drain of the seventh scan switching transistor, the gate of the first driving transistor, and the first plate of the bootstrap capacitor. The gate of the second scan switching transistor is connected to the first clock control line. The reverse stage is composed of a third scan switch transistor, a fourth scan switch transistor, a seventh scan switch transistor, and a scan storage capacitor. The drain of the third scan switch transistor is connected to the drain of the fourth scan switch transistor, the gate of the seventh scan switch transistor, the gates of the second drive transistor, the third drive transistor, and the fourth drive transistor. The source of the third scan switch transistor is connected to the power supply. The source of the fourth scan switch transistor is connected to the ground. The source of the seventh scan switch transistor is connected to the ground. The second plate of the scan storage capacitor is connected to the ground; The data scan output stage is composed of a first drive transistor, a second drive transistor, and a bootstrap capacitor. The drain of the first drive transistor is connected to the second clock control line. The source of the first drive transistor is connected to the data scan control line. The source of the second drive transistor is connected to the ground. The gate of the second drive transistor is connected to the drain of the third scan switch transistor, the drain of the fourth scan switch transistor, the gate of the seventh scan switch transistor, the gate of the third drive transistor, and the gate of the fourth scan switch transistor; The compensation scan output stage is composed of a fifth scan switch transistor, a sixth scan switch transistor, a third drive transistor, a fourth drive transistor, a fifth drive transistor, and a sixth drive transistor. The drain of the fifth scan switch transistor is connected to the drain of the sixth scan switch transistor, the gate of the fifth drive transistor, and the gate of the sixth drive transistor. The source of the fifth scan switch transistor is connected to the power supply. The gate of the fifth scan switch transistor is connected to the data scan control line. The source of the sixth scan switch transistor is connected to the ground. The drain of the third drive transistor is connected to the first enable scan control line. The source of the third drive transistor is connected to the power supply enable control line. The source of the fourth drive transistor is connected to the ground. The gate of the fourth drive transistor is connected to the drain of the third scan switch transistor, the drain of the fourth scan switch transistor, the gate of the seventh scan switch transistor, the gate of the second drive transistor, and the gate of the third switch transistor. The drain of the fifth drive transistor is connected to the data scan enable control line. The source of the fifth drive transistor is connected to the power supply enable control line. The gate of the fifth drive transistor is connected to the drain of the fifth scan switch transistor, the drain of the sixth scan switch transistor, and the gate of the sixth drive transistor. The source of the sixth drive transistor is connected to the ground.

6. A method for driving the row driving circuit according to claim 5, characterized in that, Including: Frame 1: The power supply enable control line is given a high level; Including a signal initialization stage, in which the first scan control line outputs a high potential; A signal output stage, in which the scan enable control line outputs a high potential; A signal reset stage; Frames 2 to N: The power supply enable control line is given a high level; Including a signal initialization stage, a signal output stage, and a signal reset stage.

7. The method according to claim 6, characterized in that, Frame 1: The power supply enable control line is given a high level; including a signal initialization stage, a signal output stage, and a signal reset stage. Specifically: Signal input initialization stage: The first clock control line is given a high level, and the second scan switch transistor is turned on; the second clock control line is given a low level, and the first scan switch transistor is turned on; the input control line is given a high level, and the drain of the first scan switch transistor changes from a low potential to a high potential, and the first plate of the scan storage capacitor is charged to a high potential, the third scan switch transistor is turned off, the fourth scan switch transistor is turned on, the drains of the third scan switch transistor and the fourth switch transistor output a low potential, the seventh scan switch transistor is turned off, the second drive transistor is turned off, the third drive transistor is turned on, the fourth drive transistor is turned off, and the first scan enable control line outputs a high potential; the first plate of the bootstrap capacitor is charged to a high potential, the first drive transistor is turned on, the data scan control line outputs a low potential, the fifth scan switch transistor is turned on, the sixth scan switch transistor is turned off, the drains of the fifth scan switch transistor and the sixth scan switch transistor output a high potential, the fifth drive transistor is turned off, the sixth scan switch transistor is turned on, and the scan enable control line outputs a low potential; Signal output stage: The first clock control line is given a low level, and the second scan switch transistor is turned off; the second clock control line is given a high level, the first scan switch transistor is turned off, the first plate of the bootstrap capacitor is bootstrapped to an even higher high potential, the data scan control line outputs a high potential, the fifth scan switch transistor is turned off, the sixth scan switch transistor is turned on, the drains of the fifth switch transistor and the sixth switch transistor output a low potential, the fifth drive transistor is turned on, the sixth switch transistor is turned off, and the scan enable control line outputs a high potential; Signal reset stage: The first clock control line is given a high level, and the second scan switch transistor is turned on; The second clock control line is given a low level, the first scan switch transistor is turned on, the first plate of the storage capacitor discharges to a low level, the third switch transistor is turned on, the fourth switch transistor is turned off, the drains of the third scan switch transistor and the fourth scan switch transistor output a high potential, the seventh scan switch transistor is turned on, the first plate of the bootstrap capacitor discharges to a low level, the third drive transistor is turned off, the fourth drive transistor is turned on, the first scan control line outputs a low potential, the first drive transistor is turned off, the second drive transistor is turned on, the data scan control line outputs a low potential, the fifth scan switch transistor is turned on, the sixth scan switch transistor is turned off, the drains of the fifth scan switch transistor and the sixth scan switch transistor output a high potential, the fifth drive transistor is turned off, the sixth drive transistor is turned on, and the scan enable control line outputs a low potential.

8. The method according to claim 6, characterized in that, Frames 2 to N: The power enable control line is given a low level; including the signal input initialization stage, where the first scan control line outputs a high potential; the signal output stage, where the scan enable control line outputs a high potential; the signal reset stage, specifically: Frames 2 to N: The power enable control line is given a high level; Signal input initialization stage: The first clock control line is given a high level, and the second scanning switch transistor is turned on; the second clock control line is given a low level, and the first scanning switch transistor is turned on; the input control line is given a high level, the drain of the first scanning switch transistor changes from a low potential to a high potential, the first plate of the scanning storage capacitor is charged to a high potential, the third scanning switch transistor is turned off, the fourth scanning switch transistor is turned on, the drains of the third scanning switch transistor and the fourth scanning switch transistor output a low potential, the seventh scanning switch transistor is turned off, the second driving transistor is turned off, the third driving transistor is turned on, the fourth driving transistor is turned off, and the first scanning control line outputs a low potential; the first plate of the bootstrap capacitor is charged to a high potential, the first driving transistor is turned on, the data scanning control line outputs a low potential, the fifth scanning switch transistor is turned on, the sixth scanning switch transistor is turned off, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output a high potential, the fifth driving transistor is turned off, the sixth switching transistor is turned on, and the scan enable control line outputs a low potential; Signal output stage: The first clock control line is given a low level, and the second scanning switch transistor is turned off; the second clock control line is given a high level, the first scanning switch transistor is turned off, the first plate of the bootstrap capacitor is bootstrapped to an even higher high potential, the data scanning control line outputs a high potential, the fifth scanning switch transistor is turned off, the sixth scanning switch transistor is turned on, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output a low potential, the fifth driving transistor is turned on, the sixth scanning switch transistor is turned off, and the scan enable control line outputs a low potential; Signal reset stage: The first clock control line is given a high level, and the second scanning switch transistor is turned on; The second clock control line is given a low level, the first scanning switch transistor is turned on, the first plate of the storage capacitor is discharged to a low level, the third scanning switch transistor is turned on, the fourth scanning switch transistor is turned off, the drains of the third scanning switch transistor and the fourth scanning switch transistor output a high potential, the seventh scanning switch transistor is turned on, the first plate of the bootstrap capacitor is discharged to a low level, the third driving transistor is turned off, the fourth driving transistor is turned on, the first scanning control line outputs a low potential, the first driving transistor is turned off, the second driving transistor is turned on, the data scanning control line outputs a low potential, the fifth scanning switch transistor is turned on, the sixth scanning switch transistor is turned off, the drains of the fifth scanning switch transistor and the sixth scanning switch transistor output a high potential, the fifth driving transistor is turned off, the sixth driving transistor is turned on, and the scan enable control line outputs a low potential.

9. A row driving circuit, characterized in that For providing the light-emitting scan control signal of the pixel circuit as described in claim 1, and transmitting it to the pixel circuit through the light-emitting scan control line; It includes a first light-emitting switch transistor, a second light-emitting switch transistor, a third light-emitting switch transistor, a fourth light-emitting switch transistor, a fifth light-emitting switch transistor, a first light-emitting driving transistor, a second light-emitting driving transistor, a light-emitting bootstrap capacitor, and a light-emitting storage capacitor; The specific connection method is as follows: The drain of the first light-emitting switch transistor is connected to the first plate of the light-emitting storage capacitor, the gates of the first light-emitting driving transistor and the second light-emitting driving transistor; the source of the first light-emitting switch transistor is connected to the light-emitting input control line and the source of the second light-emitting switch transistor; the gate of the first light-emitting switch transistor is connected to the first light-emitting clock control line and the gate of the second light-emitting switch transistor; The drain of the second light-emitting switch transistor is connected to the gates of the third light-emitting switch transistor, the fourth light-emitting switch transistor, the drain of the fifth light-emitting switch transistor and the first plate of the light-emitting bootstrap capacitor; the source of the second light-emitting switch transistor is connected to the light-emitting input control line; The drain of the third light-emitting switch transistor is connected to the drain of the fourth transistor, the second plate of the light-emitting bootstrap capacitor and the trigger control line COUT; The source of the third light-emitting switch transistor is connected to the second light-emitting clock control line; The source of the fourth light-emitting switch transistor is connected to the power supply VDD; The source of the fifth light-emitting switch transistor is connected to the power supply VDD; The gate of the fifth light-emitting switch transistor is connected to the drain of the first light-emitting driving transistor, the drain of the second light-emitting driving transistor and the light-emitting control scan control line; The source of the first light-emitting driving transistor is connected to the ground and the second plate of the light-emitting storage capacitor; The source of the second light-emitting driving transistor is connected to the power supply.

10. A method for driving a row driving circuit as claimed in claim 9, characterized in that, Including: Initialization stage: The input control line outputs a low potential; the first light-emitting clock control line outputs a low potential, the first light-emitting switch transistor is turned on, the second light-emitting switch transistor is turned on, the first plate of the light-emitting storage capacitor discharges to a low level, the first light-emitting driving transistor is turned off, the second light-emitting driving transistor is turned on, the light-emitting control scan control line outputs a high potential, the light-emitting bootstrap capacitor discharges to a low potential, the third light-emitting switch transistor is turned on, the fourth light-emitting switch transistor is turned off, the second clock control line outputs a high potential, and the trigger control line outputs a high level; Trigger signal output stage: The input control line outputs a high potential; the first light-emitting clock control line outputs a high potential, the first light-emitting switch transistor is turned off, and the second light-emitting switch transistor is turned off; The second light-emitting clock control line outputs a low potential, and the trigger control line outputs a low level; Reset stage: The first light-emitting clock control line outputs a low potential, the first light-emitting switch transistor is turned on, and the second light-emitting switch transistor is turned on; The input control line outputs a high potential, the light-emitting storage capacitor is charged to a high potential, the first light-emitting driving transistor is turned on, the second light-emitting switch transistor is turned off, the light-emitting control scan control line outputs a low potential, and the light-emitting bootstrap capacitor is charged to a high potential; The second light-emitting clock control line outputs a high potential, the third light-emitting switch transistor is turned off, the second light-emitting switch transistor is turned on, the fifth light-emitting switch transistor is turned on, and the trigger control line outputs a high potential.

Images