6T SRAM cell transistor threshold voltage on-chip measurement circuit, measurement method, and chip

Abstract

The present invention discloses an on-chip measurement circuit, measurement method, and chip for the threshold voltage of a 6T SRAM cell transistor. The circuit comprises a 6T SRAM array cell, an analog switch, and a threshold voltage determination circuit. The threshold voltage determination circuit is connected to two bit lines of the 6T SRAM array cell via two analog switches. The threshold voltage determination circuit includes a bit line current replication circuit connected to the other side of the analog switch connected to the bit line of the cell under test, for replicating the charge and discharge current of the transistor under test; a constant current generation circuit for generating an adjustable current positively correlated with the aspect ratio of the transistor under test; a current comparison circuit connected to the bit line current replication circuit and the constant current generation circuit via current mirrors; and a dynamic voltage comparator whose positive and negative terminals are connected to an off-chip voltage source and a voltage output terminal of the current comparison circuit, respectively.

Description

Technical Field

[0001] The present invention relates to the field of on-chip measurement technology, and in particular to an on-chip measurement circuit, a measurement method and a chip for measuring the threshold voltage of a 6T SRAM unit transistor. Background Art

[0002] Static random access memory (SRAM) is a critical component of SoC systems, typically occupying 30% of the chip area. Its manufacturing process is among the most demanding in integrated circuits. As process geometries shrink and SoC power supply voltages decrease, random transistor threshold voltage variations caused by manufacturing variations are a major factor in reducing SRAM stability. Measuring transistor threshold voltage variations in actual SRAM array environments can reveal the impact of lithography and process technology on SRAM performance.

[0003] Traditional 6T SRAM transistor threshold voltage measurement schemes use a direct measurement method. The specific test structure and method involves connecting all four terminals of all transistors in a memory cell to voltage setting and monitoring terminals, as well as a high-precision current measurement device, via analog switches. By controlling the voltage at each terminal of the transistor under test and observing the charge and discharge current, the Id-Vg curve of each transistor is measured. The threshold voltage of each transistor is then determined using the constant current method. While this measurement structure is simple and direct, it requires adjustments to the compact SRAM layout to connect the internal storage nodes of each memory cell, which affects the accuracy of the measurement results. Furthermore, this method requires a large number of analog switches, which consumes a lot of area and is not suitable for threshold voltage measurement in large-scale SRAM arrays. Furthermore, since transistor subthreshold currents are in the nanoampere range, the accuracy of the external current measurement device is very high, which increases testing costs. Improved large-scale SRAM transistor threshold voltage test structures abandon direct access to internal nodes and instead indirectly control internal node voltages through bit lines and word lines. On-chip threshold voltage quantization circuitry is also added. However, this method still modifies the compact SRAM IP layout, and the ADC quantization circuit is complex to implement and has limited accuracy. Summary of the Invention

[0004] The present invention aims to address the deficiencies in the prior art and proposes an on-chip measurement circuit, a measurement method and a chip for the threshold voltage of a 6T SRAM cell transistor.

[0005] The object of the present invention is achieved through the following technical solutions:

[0006] A first aspect of an embodiment of the present invention provides a 6T SRAM cell transistor threshold voltage measurement circuit, comprising:

[0007] 6T SRAM array cell,

[0008] analog switches,

[0009] A threshold voltage determination circuit is connected to two bit lines of a 6T SRAM array unit via two analog switches. The threshold voltage determination circuit includes a bit line current replication circuit connected to the other side of the analog switch connected to the bit line of the unit under test and used to replicate the charge and discharge current of the transistor under test; a constant current generation circuit used to generate an adjustable current positively correlated with the width-to-length ratio of the transistor under test; a current comparison circuit connected to the bit line current replication circuit and the constant current generation circuit via current mirrors; and a dynamic voltage comparator having its positive and negative terminals connected to an off-chip voltage source and a voltage output terminal of the current comparison circuit, respectively.

[0010] Furthermore, the bit line current replication circuit includes:

[0011] a first PMOS transistor having a drain configured to be connected to one end of an analog switch connected to a bit line, a source configured to be connected to a power supply terminal, and a gate configured to be connected to its drain;

[0012] a second PMOS transistor, a source of which is configured to be connected to the power supply terminal, and a gate of which is configured to be connected to the gate of the first PMOS transistor;

[0013] a first NMOS transistor having a drain coupled to the drain of the second PMOS transistor to form a first node, and a gate configured to be connected to the drain;

[0014] a second NMOS transistor, a drain of which is coupled to the source of the first NMOS transistor, and a source of which is configured to be coupled to a ground terminal;

[0015] The first operational amplifier has an output terminal configured to be connected to the gate of the second NMOS transistor, one input terminal configured to be coupled to the first node, and the other input terminal connected to an off-chip voltage source.

[0016] Furthermore, the constant current generating circuit includes:

[0017] a first resistor, either end of which is connected to a power supply terminal;

[0018] a third PMOS transistor, a source of which is coupled to the other end of the first resistor to form a second node;

[0019] a second operational amplifier, an output terminal of which is connected to the gate of the third PMOS transistor, one input terminal of which is connected to the second node, and the other input terminal of which is connected to an off-chip voltage source;

[0020] a third NMOS transistor, having a drain configured to be connected to the drain of the third PMOS transistor, a source coupled to the ground terminal, and a gate configured to be connected to the drain;

[0021] a fourth NMOS transistor, a gate of which is configured to be connected to the gate of the third NMOS transistor, and a source of which is coupled to the ground terminal;

[0022] a fourth PMOS transistor, having a drain coupled to the drain of the fourth NMOS transistor to form a third node, and a gate connected to the third node;

[0023] a fifth PMOS transistor, having a source coupled to the power supply terminal and a drain connected to the source of the fourth PMOS transistor;

[0024] The third operational amplifier has its output terminal connected to the gate of the fifth PMOS transistor, one input terminal connected to the third node, and the other input terminal connected to one terminal of the first operational amplifier connected to an off-chip voltage source.

[0025] Furthermore, the current comparison circuit includes:

[0026] a sixth PMOS transistor, having a source connected to the power supply terminal and a gate connected to the output terminal of the third operational amplifier;

[0027] a seventh PMOS transistor, whose source is connected to the drain of the sixth PMOS transistor and whose gate is connected to the third node;

[0028] a fifth NMOS transistor, a drain of which is coupled to the drain of the seventh PMOS transistor to form a fourth node, and a gate of which is connected to the first node;

[0029] A sixth NMOS transistor has a drain connected to the source of the fifth NMOS transistor, a gate connected to the output terminal of the first operational amplifier, and a source coupled to the ground terminal.

[0030] Furthermore, the positive input terminal of the dynamic voltage comparator is connected to the fourth node, the negative input terminal is connected to one terminal of the first operational amplifier connected to an off-chip voltage source, and the output terminal is connected to an off-chip oscilloscope.

[0031] A second aspect of an embodiment of the present invention provides a 6T SRAM cell transistor threshold voltage measurement method, which is implemented by the above-mentioned 6T SRAM cell transistor threshold voltage measurement circuit, including:

[0032] Step a: All analog switches connecting the 6T SRAM memory cell to the voltage source and the voltmeter are closed, and the switches connecting the two bit lines of the 6T SRAM memory cell to the threshold voltage determination circuit remain open;

[0033] Step b: controlling the gate, drain, and source voltages of the transistor under test, cutting off the positive feedback characteristics of the cross-coupled inverter, and causing the drain current of the transistor under test to flow entirely through the bit line;

[0034] Step c: disconnecting the switch connecting the memory cell bit line to the voltage source, closing the switch connecting the bit line to the threshold voltage determination circuit, and adjusting the external voltage source connected to the input terminal of the second operational amplifier in the constant current generating circuit so that the current flowing through the first resistor is equal to the aspect ratio of the transistor to be tested multiplied by ten to the power of -7 amperes;

[0035] Step d: copying the drain current of the transistor to be tested and the constant current generated in step c to the pull-up and pull-down networks of the current comparison circuit for comparison, and outputting the comparison result via the dynamic voltage comparator;

[0036] Step e: Change the gate voltage of the transistor to be tested so that the transistor to be tested gradually enters the saturation region from the cutoff region, and repeat the above steps until the output level of the dynamic voltage comparator is observed to be flipped. It is determined that the absolute value of the difference between the gate and source voltages applied to the transistor to be tested at this time is the threshold voltage of the transistor to be tested.

[0037] Furthermore, when the transistor to be tested is a load transistor, the method includes:

[0038] In step b, the voltage source connected to the word line is adjusted to a high level, the voltage source connected to the power supply terminal and the ground terminal of the memory cell is adjusted to a high level, and the voltage source connected to the bit line on the side of the transistor to be tested is adjusted to a level of 80% of the high level;

[0039] In step e, the gate voltage of the transistor to be tested is indirectly controlled by adjusting a voltage source connected to a bit line that is away from the transistor to be tested.

[0040] Furthermore, when the transistor to be tested is a pull-down transistor, the method includes:

[0041] In step b, the voltage source connected to the word line is adjusted to a high level, the voltage source connected to the power supply terminal and the ground terminal of the memory cell is adjusted to a low level, and the voltage source connected to the bit line on the side of the transistor to be tested is adjusted to a level of 20% of the high level;

[0042] In step e, the gate voltage of the transistor to be tested is indirectly controlled by adjusting a voltage source connected to a bit line that is away from the transistor to be tested.

[0043] Furthermore, when the transistor to be tested is a transmission transistor, the method includes:

[0044] In the preset stage in step b, the voltage source connected to the power supply terminal of the memory cell is adjusted to a high level, the voltage source connected to the ground terminal of the memory cell is adjusted to a low level, the voltage source connected to the word line is adjusted to a high level, the voltage source connected to the bit line on one side of the transistor to be tested is adjusted to a low level, and the voltage source connected to the bit line on the other side is adjusted to a high level;

[0045] During the measurement phase in step b, the voltage source connected to the bit line on the other side of the tube to be tested is kept at a high level, and the voltage source connected to the bit line on one side of the tube to be tested is adjusted to 20% of the high level;

[0046] In step e, the gate voltage of the pass transistor is controlled by adjusting a voltage source connected to the word line.

[0047] A third aspect of an embodiment of the present invention provides a large-scale 6T SRAM array cell transistor threshold voltage measurement chip, comprising the above-mentioned measurement circuit, an analog multiplexer connected to the bit lines and word lines, an address decoder for generating analog multiplexer selection signals, and a timing controller.

[0048] Compared with the prior art, the present invention has the following advantages: the present invention can control and monitor the bit line and word line voltages while maintaining the compact SRAM layout structure, so that the drain current of the transistor under test flows entirely through the bit line, and compares the current with the generated constant current to determine the threshold voltage of all transistors under test in the 6T SRAM array structure. Furthermore, the threshold voltage value can be determined on-chip without the need for an external high-precision current measurement device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A circuit diagram showing an embodiment of the present invention is shown;

[0050] Figure 2 A schematic diagram showing a bit line charging current replication circuit in an embodiment of the present invention;

[0051] Figure 3 A schematic diagram showing a conventional two-stage operational amplifier circuit in an embodiment of the present invention;

[0052] Figure 4 A schematic diagram of a dynamic voltage comparator circuit in an embodiment of the present invention is shown;

[0053] Figure 5 A schematic diagram illustrating a load transistor measurement method according to an embodiment of the present invention;

[0054] Figure 6 A schematic diagram illustrating a pull-down transistor measurement method according to an embodiment of the present invention;

[0055] Figure 7 A schematic diagram illustrating a transmission tube measurement method in an embodiment of the present invention;

[0056] Figure 8 A 6T SRAM array unit transistor subthreshold voltage measurement system provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0057] The present invention will be described in detail below with reference to the accompanying drawings. Unless there is any conflict, the features of the following embodiments and implementations may be combined with each other.

[0058] like Figure 1 As shown, the present invention provides a 6T SRAM cell transistor threshold voltage measurement circuit, comprising:

[0059] 6T SRAM array cell 100,

[0060] Analog switches S0-S11,

[0061] A threshold voltage determination circuit 103 is connected to two bit lines of a 6T SRAM array cell via two analog switches S10 and S11. The threshold voltage determination circuit includes a bit line current replication circuit 101 connected to the other side of the analog switch connected to the bit line of the cell under test and used to replicate the charge and discharge current of the transistor under test; a constant current generation circuit 102 used to generate an adjustable current positively correlated with the aspect ratio of the transistor under test; a current comparison circuit 110 connected to the bit line current replication circuit and the constant current generation circuit via current mirrors; and a dynamic voltage comparator 104 whose positive and negative terminals are connected to an off-chip voltage source and a voltage output terminal of the current comparison circuit, respectively.

[0062] The 6T SRAM cell transistor threshold voltage measurement circuit proposed in the present invention can accurately measure the threshold voltages of all transistors in a 6T SRAM array structure without changing the compact SRAM layout structure, and can determine the threshold voltage value on-chip without the need for an external high-precision current measurement device.

[0063] The 6T SRAM array cell utilizes a compact layout, with each column of memory cells sharing two bit lines and each row sharing one word line. All memory cells share a common power supply and ground. The two bit lines, one word line, power supply, and ground of the memory cell under test are connected to a voltage source and a voltmeter, respectively, via two analog switches. Voltage setting and monitoring are performed off-chip. The two bit lines of the memory cell under test are also connected to a threshold voltage generation circuit via two analog switches.

[0064] The analog switch is composed of an inverter and two parallel transistor transmission gates.

[0065] It should be further explained that the drain current of the M2-M6 transistors discharged from the bit line is copied using the following method: Figure 1The illustrated bitline current replication circuit 101 comprises transistors M7-M10 and a first operational amplifier A1. The gate-drain connection of the first PMOS transistor M7 is connected to the drain of the second PMOS transistor M8, forming a PMOS current mirror. This mirrors the discharge current of the bitline to the branch containing transistors M8-M10 in equal proportion. Specifically, the first PMOS transistor M7 in the bitline current replication circuit is configured with its gate and drain connected and connected to one end of an analog switch connected to the bitline, and its source is connected to a power supply terminal. The source of the second PMOS transistor M8 is connected to the power supply terminal, and its gate is connected to the gate of the first PMOS transistor M7. The gate of the first NMOS transistor M9 is coupled to the drain of the second PMOS transistor M8, forming a first node. The drain of the second NMOS transistor M9 is coupled to the source of the first NMOS transistor M10, and its source is coupled to the ground terminal. The output terminal of the first operational amplifier A1 is configured to be connected to the gate of the second NMOS transistor M10 , the positive input terminal thereof is configured to be coupled to the first node 105 , and the negative input terminal thereof is connected to an off-chip voltage source.

[0066] The drain current of the M1-M2 transistor that charges the bit line is copied using Figure 2The bitline current replication circuit shown in the figure is specifically composed of transistors M20-M27 and an operational amplifier A4. The gate-drain connection of the seventh NMOS transistor M20 and the shared gate of the eighth NMOS transistor M21 form an NMOS current mirror, which proportionally replicates the charging current of the bitline to the branch containing transistors M21-M23. Simultaneously, a cascode current mirror formed by transistors M22-M25 replicates the current proportionally to the branch containing transistors M24-M27. Specifically, the gate and drain of the seventh NMOS transistor M20 are connected and connected to one end of the analog switch connected to the bitline, and its source is connected to a ground terminal. The source of the eighth NMOS transistor M21 is connected to a ground terminal, and its gate is connected to the gate of the seventh NMOS transistor M20. The eighth PMOS transistor M23 is configured with its gate and drain connected and then connected to the drain of the eighth NMOS transistor M21. The ninth PMOS transistor M22 is configured with its gate and drain connected and then connected to the source of the eighth PMOS transistor M23, with its source connected to the power supply terminal. The tenth PMOS transistor M24 is configured with its gate connected to the ninth PMOS transistor M22 and its source connected to the ground terminal. The eleventh PMOS transistor M25 is configured with its source connected to the drain of the tenth PMOS transistor M24 and its gate connected to the gate of the eighth PMOS transistor M23. The ninth NMOS transistor M26 is configured with its gate and drain connected and then connected to the drain of the eleventh PMOS transistor M25. The tenth NMOS transistor M27 is configured with its drain connected to the source of the ninth NMOS transistor M26 and its source connected to the ground terminal. The fourth operational amplifier A4 is configured with its positive input terminal connected to the drain of the ninth NMOS transistor M26, its negative input terminal connected to an off-chip voltage source, and its output terminal connected to the gate of the tenth NMOS transistor M27.

[0067] Specifically, the constant current generating circuit 102 comprises a 20k ohm resistor RZ, transistors M11-M17, and a second operational amplifier A2 and a third operational amplifier A3. One end of the first resistor RZ is connected to a power supply terminal, and the other end is connected to the source of the third PMOS transistor M11, forming a second node 106. The output of the second operational amplifier A2 is connected to the gate of the third PMOS transistor M11, its positive input is connected to the second node 106, and its negative input is connected to an off-chip voltage source. The drain of the third NMOS transistor M12 is connected to the drain of the third PMOS transistor M11, its source is coupled to the ground terminal, and its gate is configured to be connected to the drain. The gate of the fourth NMOS transistor M13 is configured to be connected to the gate of the third NMOS transistor M12, and its source is coupled to the ground terminal. The drain of the fourth PMOS transistor M14 is coupled to the drain of the fourth NMOS transistor M13, forming a third node 107, and its gate is connected to the third node 107. The fifth PMOS transistor M15 has its source coupled to the power supply terminal and its drain connected to the source of the fourth PMOS transistor M14. The output terminal of the third operational amplifier A3 is connected to the gate of the fifth PMOS transistor M15, one of its input terminals is connected to the third node 107, and the other input terminal is connected to one terminal of the first operational amplifier A1 connected to the off-chip voltage source. In this example, by adjusting the external voltage value V SET Make the generated current equal to transistor V GS =V TH The subthreshold current at this time can be defined as Ion = (W / L) * 10 according to the constant current method. -7 , W / L is the width-to-length ratio of the transistor to be tested.

[0068] In particular, the constant current generating circuit 102 may also be replaced by an SMU current source.

[0069] The current comparison circuit 110 is comprised of transistors M16-M19. The pull-up network formed by M16 and M17 is used to replicate the constant current generated by the constant current generation circuit 102, while the pull-down network formed by M18 and M19 is used to replicate the bit line current. Specifically, the sixth PMOS transistor M16 in the current comparison circuit 110 has its source connected to the power supply terminal and its gate connected to the output terminal of the third operational amplifier A3. The seventh PMOS transistor M17 has its source connected to the drain of the sixth PMOS transistor M16 and its gate connected to the third node 107. The drain of the fifth NMOS transistor M18 is coupled to the drain of the seventh PMOS transistor M17, thereby forming a fourth node 108, and its gate is connected to the first node 105. The drain of the sixth NMOS transistor M19 is connected to the source of the fifth NMOS transistor M18, its gate is connected to the output terminal of the first operational amplifier A1, and its source is coupled to the ground terminal.

[0070] The positive input terminal of the dynamic voltage comparator 104 is connected to the fourth node, the negative input terminal is connected to one terminal of the first operational amplifier connected to an off-chip voltage source, and the output terminal is connected to an off-chip oscilloscope.

[0071] Figure 3 FIG. 1 shows a conventional two-stage operational amplifier. As long as the gain of the operational amplifier is large enough, the output terminal will amplify the voltage difference between the two input terminals many times. However, the bit line current or constant current flowing through the transistor is limited, and its gate voltage will not exceed the range from the power supply (VDD) to the ground (GND). Therefore, the operational amplifier will force the voltages of the two input terminals to be almost equal, that is, the voltages of the first node 105 and the third node 107 will follow V CM The voltage value of the second node 106 changes and the voltage of the second node 106 follows V SET The voltage value varies.

[0072] Due to the feedback effect of the second operational amplifier A2, the voltage of the second node 106 is forced to be approximately equal to V SET Therefore, the current flowing through the third PMOS transistor M11 is a constant current, and the current value is The generated constant current and the copied bit line current are respectively copied to the pull-up network formed by M16-M17 and the pull-down network formed by M18-M19 through the cascode current mirror. When the two currents are equal, the voltage of the fourth node 108 is exactly equal to V due to the modulation effect of the operational amplifiers A1 and A3. CM Otherwise, it will fluctuate based on the current comparison result. If the current flowing through the pull-down network is greater, the voltage value of output node 108 will be pulled down to balance the current. This allows the current comparison result to be determined by the high or low output level of the dynamic voltage comparator. The absolute value of the voltage difference between the gate and source of the transistor under test when the comparator output level flips is determined to be the threshold voltage of the transistor. The dynamic voltage comparator circuit is based on A 1.9μW 4.4fJ / Conversion-step 10b 1MS / s Charge-Redistribution ADC (ISSCC, 2008). Figure 4 shown.

[0073] Figure 1 A 6T SRAM memory cell 100 to be tested is shown in the figure. Its bit lines BL / BLB, word lines WL, memory cell common power supply terminal VD, and ground terminal VS are connected to the voltage setting terminal (FORCE) and monitoring terminal (SENSE) respectively through analog switches S0-S9. By controlling the conduction and off-state of analog switches S10 and S11, whether to connect to the threshold voltage determination circuit is selected to realize the threshold voltage measurement of the transistor to be tested.

[0074] An embodiment of the present invention provides a method for measuring the threshold voltage of transistors in a 6T SRAM array. The method adjusts the source, drain, and gate voltages of each transistor by controlling the bitline and wordline voltages, as well as the power supply and ground voltages shared by the memory cells, maintaining a small constant voltage difference between the drain and source of the transistor under test. The gate voltage is scanned to cause the entire leakage current of the transistor under test to flow through the bitline, generating a charge and discharge current. This current is then compared with the current generated by the constant current generation circuit via a bitline current replication circuit. If the bitline current is higher than the generated constant current, the voltage of the fourth node is lower than the external voltage source connected to the first and third operational amplifiers, and the dynamic voltage comparator outputs a low level; otherwise, it outputs a high level. The gate voltage is scanned and compared multiple times until the comparator output level flips, at which point the absolute value of the voltage difference between the gate and source of the transistor under test is determined to be the threshold voltage of the transistor.

[0075] The specific steps for measuring the threshold voltage of each transistor M1-M6 in the 6T SRAM memory cell 100 to be tested are as follows. In this embodiment, the load transistor M1, the pull-down transistor M3, and the transmission transistor M5 are taken as examples. Due to the complete symmetry of the cell, the measurement methods for the other three transistors are the same.

[0076] Example 1: Measuring the threshold voltage of load tube M1

[0077] Step 1: Close switches S0-S9, and keep switches S10 and S11 open.

[0078] Step 2: If Figure 5 As shown, by connecting FORCE_WL to a high level, the gate voltage of M5 / M6 remains high. DD , to ensure that the transmission tubes M5 and M6 are turned on; connect FORCE_VS to a high level to cut off the positive feedback characteristics of the cross-coupled inverter composed of M1-M4, and prevent the drain current ID1 of M1 from flowing through the M3 tube; connect FORCE_VD to a high level V DD ,FORCE_BL is slightly smaller than V DD Level voltage V DD -ΔV, the voltage of the drain node Q of M1 is controlled through the transmission tube M5, so that the source-drain voltage of M1 is equal to ΔV.

[0079] Step 3: Adjust V in the constant current generating circuit 102 SET Voltage value, so Where W1 represents the gate width of the transistor M1 to be tested, and L1 represents the gate length of M1. CM Connect to 1 / 2V DD level voltage source, use Figure 3 The bit line current replica circuit replaces Figure 2 The bit line current replica circuit in .

[0080] Step 4: Open switch S1 and close S11 to make FORSE_BLB go from 0-V DD DC scanning is performed to control the voltage of the gate node QB of M1 through the transmission transistor M6. At this time, the drain current of M1 flows completely through the bit line BL and passes through the threshold voltage determination circuit 103 and I constant Compare and record the dynamic comparator output results corresponding to each FORCE_BLB voltage value until the comparator output level flips to determine the high level V DD The difference between the voltage value applied by FORCE_BLB and the voltage value applied by FORCE_BLB is the threshold voltage of the transistor M1.

[0081] Example 2: Measuring the Threshold Voltage of Pull-Down Transistor M3

[0082] Step 1: Close switches S0-S9, and keep switches S10 and S11 open.

[0083] Step 2: If Figure 6 As shown, by connecting FORCE_WL to a high level, the gate voltage of M5 / M6 remains high. DD , to ensure that the transmission tubes M5 and M6 are turned on; connect FORCE_VD to the low level V SS Cut off the positive feedback characteristics of the cross-coupled inverters and prevent I D3 Flows through M1 tube; connects FORCE_VS to low level V SS , FORCE_BL is slightly higher than V SS Voltage source V SS +ΔV, controls the voltage of the drain node Q of M3 through the transmission tube M5, so that the drain-source voltage of M3 is ΔV.

[0084] Step 3: Adjust V in the constant current generating circuit 102 SET Voltage value, so Where W3 represents the gate width of the transistor M3 to be tested, and L3 represents the gate length of M3. CM接 1 / 2V DD level voltage source, use Figure 2 The bit line current replica circuit in .

[0085] Step 4: Open switch S1 and close S11 to make FORSE_BLB go from 0-V DD DC scanning is performed to control the voltage of the gate node QB of M3 through the transmission transistor M6. At this time, the drain current of M3 flows completely through the bit line BL and passes through the threshold voltage determination circuit 103 and I constantCompare and record the dynamic comparator output result corresponding to each FORCE_BLB voltage value until the comparator output level flips to determine whether the FORCE_BLB applied voltage value at this time is consistent with the low level V SS The difference is the threshold voltage of transistor M3.

[0086] Example 3: Measuring the threshold voltage of the transmission transistor M5

[0087] Step 1: Close switches S0-S9, and keep switches S10 and S11 open.

[0088] Step 2: If Figure 7 As shown, in the first stage, FORCE_BL is connected to the low level V SS , FORCE_BLB, FORCE_WL and FORCE_VD are all connected to the high level V DD , FORCE_VS is connected to low level V SS , write "0" to the storage unit, that is, keep the node Q at a low level V SS , node QB is high level V DD In the second stage, keep FORCE_BLB high so that node Q remains low, and connect FORCE_BL to a voltage slightly higher than V SS The level V SS +ΔV, making the drain-source voltage of M5 equal to ΔV.

[0089] Step 3: Adjust V in the constant current generating circuit 102 SET Voltage value, so Where W5 represents the gate width of the transistor M5 to be tested, and L5 represents the gate length of M5. CM Connect to 1 / 2V DD level voltage source, use Figure 2 The bit line current replica circuit in .

[0090] Step 4: Open switch S1 and close S11 to make FORSE_WL go from 0-V DD进 The gate voltage of M5 is controlled by the DC scan. At this time, the drain current of M5 flows completely through the bit line BL and determines the threshold voltage of the circuit 103 and I constant Compare and record the dynamic comparator output result corresponding to each FORCE_WL voltage value until the comparator output level flips to determine whether the FORCE_WL applied voltage value at this time is consistent with the low level V SS The difference is the threshold voltage of transistor M5.

[0091] Figure 8This paper shows a system architecture suitable for measuring the threshold voltage of transistors in large-scale 6T SRAM array cells. By decoding address signals, the bit line and word line analog multiplexers are controlled to sequentially select the memory cells to be measured. The threshold voltage measurement method for each transistor in each memory cell is as described above. The FPGA automatically provides address signals, and a script controls the bias provided by an external voltage source. The voltmeter and oscilloscope measurements are automatically recorded.

[0092] At the same time, an embodiment of the present invention provides a large-scale 6T SRAM array unit transistor threshold voltage measurement chip, including the above-mentioned 6T SRAM array unit transistor threshold voltage measurement circuit, an analog multiplexer connecting the bit lines and word lines, an address decoder for generating analog multiplexer selection signals, and a timing controller.

[0093] In summary, the present invention addresses the shortcomings of 6T SRAM cell transistor threshold voltage measurement methods by providing an on-chip SRAM cell transistor threshold voltage measurement circuit and method. This measurement circuit and method require no modifications to the compact SRAM array layout provided by the fabricator, making them suitable for measuring transistor threshold voltages in large-scale SRAM arrays while ensuring the measurement environment is consistent with their actual operating environment. Furthermore, this measurement method can accurately measure the threshold voltages of all transistors in an SRAM array cell without requiring an external high-precision current measurement device.

[0094] The above embodiments are intended only to illustrate the design concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. The scope of protection of the present invention is not limited to the above embodiments. Therefore, any equivalent changes or modifications made based on the principles and design concepts disclosed in the present invention are within the scope of protection of the present invention.

Claims

1. A 6T SRAM cell transistor threshold voltage measurement circuit, characterized in that: include: 6T SRAM array cell, analog switches, A threshold voltage determination circuit is connected to two bit lines of a 6T SRAM array unit via two analog switches. The threshold voltage determination circuit includes a bit line current replication circuit connected to the other side of the analog switch connected to the bit line of the unit under test and used to replicate the charge and discharge current of the transistor under test; a constant current generation circuit used to generate an adjustable current positively correlated with the width-to-length ratio of the transistor under test; a current comparison circuit connected to the bit line current replication circuit and the constant current generation circuit via current mirrors; and a dynamic voltage comparator having its positive and negative terminals connected to an off-chip voltage source and a voltage output terminal of the current comparison circuit, respectively.

2. The 6T SRAM cell transistor threshold voltage measurement circuit according to claim 1, characterized in that: The bit line current replication circuit includes: a first PMOS transistor having a drain configured to be connected to one end of an analog switch connected to a bit line, a source configured to be connected to a power supply terminal, and a gate configured to be connected to its drain; a second PMOS transistor, a source of which is configured to be connected to the power supply terminal, and a gate of which is configured to be connected to the gate of the first PMOS transistor; a first NMOS transistor having a drain coupled to the drain of the second PMOS transistor to form a first node, and a gate configured to be connected to the drain; a second NMOS transistor, a drain of which is coupled to the source of the first NMOS transistor, and a source of which is configured to be coupled to a ground terminal; The first operational amplifier has an output terminal configured to be connected to the gate of the second NMOS transistor, one input terminal configured to be coupled to the first node, and the other input terminal connected to an off-chip voltage source.

3. The 6T SRAM cell transistor threshold voltage measurement circuit according to claim 2, characterized in that: The constant current generating circuit comprises: a first resistor, either end of which is connected to a power supply terminal; a third PMOS transistor, a source of which is coupled to the other end of the first resistor to form a second node; a second operational amplifier, an output terminal of which is connected to the gate of the third PMOS transistor, one input terminal of which is connected to the second node, and the other input terminal of which is connected to an off-chip voltage source; a third NMOS transistor, having a drain configured to be connected to the drain of the third PMOS transistor, a source coupled to the ground terminal, and a gate configured to be connected to the drain; a fourth NMOS transistor, a gate of which is configured to be connected to the gate of the third NMOS transistor, and a source of which is coupled to the ground terminal; a fourth PMOS transistor, having a drain coupled to the drain of the fourth NMOS transistor to form a third node, and a gate connected to the third node; a fifth PMOS transistor, having a source coupled to the power supply terminal and a drain connected to the source of the fourth PMOS transistor; The third operational amplifier has its output terminal connected to the gate of the fifth PMOS transistor, one input terminal connected to the third node, and the other input terminal connected to one terminal of the first operational amplifier connected to an off-chip voltage source.

4. The 6T SRAM cell transistor threshold voltage measurement circuit according to claim 3, characterized in that: The current comparison circuit comprises: a sixth PMOS transistor, having a source connected to the power supply terminal and a gate connected to the output terminal of the third operational amplifier; a seventh PMOS transistor, whose source is connected to the drain of the sixth PMOS transistor and whose gate is connected to the third node; a fifth NMOS transistor, a drain of which is coupled to the drain of the seventh PMOS transistor to form a fourth node, and a gate of which is connected to the first node; A sixth NMOS transistor has a drain connected to the source of the fifth NMOS transistor, a gate connected to the output terminal of the first operational amplifier, and a source coupled to the ground terminal.

5. The 6T SRAM cell transistor threshold voltage measurement circuit according to claim 4, characterized in that: The positive input terminal of the dynamic voltage comparator is connected to the fourth node, the negative input terminal is connected to one end of the first operational amplifier connected to an off-chip voltage source, and the output terminal is connected to an off-chip oscilloscope.

6. A 6T SRAM cell transistor threshold voltage measurement method, implemented based on the 6T SRAM cell transistor threshold voltage measurement circuit according to any one of claims 3 to 5, characterized in that: include: Step a: All analog switches connecting the 6T SRAM memory cell to the voltage source and the voltmeter are closed, and the switches connecting the two bit lines of the 6T SRAM memory cell to the threshold voltage determination circuit remain open; Step b: controlling the gate, drain, and source voltages of the transistor under test, cutting off the positive feedback characteristics of the cross-coupled inverter, and causing the drain current of the transistor under test to flow entirely through the bit line; Step c: disconnecting the switch connecting the memory cell bit line to the voltage source, closing the switch connecting the bit line to the threshold voltage determination circuit, and adjusting the external voltage source connected to the input terminal of the second operational amplifier in the constant current generating circuit so that the current flowing through the first resistor is equal to the aspect ratio of the transistor to be tested multiplied by ten to the power of -7 amperes; Step d: copying the drain current of the transistor to be tested and the constant current generated in step c to the pull-up and pull-down networks of the current comparison circuit for comparison, and outputting the comparison result via the dynamic voltage comparator; Step e: Change the gate voltage of the transistor to be tested so that the transistor to be tested gradually enters the saturation region from the cutoff region, and repeat the above steps until the output level of the dynamic voltage comparator is observed to be flipped. It is determined that the absolute value of the difference between the gate and source voltages applied to the transistor to be tested at this time is the threshold voltage of the transistor to be tested.

7. The method for measuring the threshold voltage of a 6T SRAM cell transistor according to claim 6, wherein: When the transistor to be tested is a load transistor, it includes: In step b, the voltage source connected to the word line is adjusted to a high level, the voltage source connected to the power supply terminal and the ground terminal of the memory cell is adjusted to a high level, and the voltage source connected to the bit line on the side of the transistor to be tested is adjusted to 80% of the high level; In step e, the gate voltage of the transistor to be tested is indirectly controlled by adjusting a voltage source connected to a bit line that is away from the transistor to be tested.

8. The method for measuring the threshold voltage of a 6T SRAM cell transistor according to claim 6, wherein: When the transistor to be tested is a pull-down transistor, it includes: In step b, the voltage source connected to the word line is adjusted to a high level, the voltage source connected to the power supply terminal and the ground terminal of the memory cell is adjusted to a low level, and the voltage source connected to the bit line on the side of the transistor to be tested is adjusted to a level of 20% of the high level; In step e, the gate voltage of the transistor to be tested is indirectly controlled by adjusting a voltage source connected to a bit line that is away from the transistor to be tested.

9. The method for measuring the threshold voltage of a 6T SRAM cell transistor according to claim 6, wherein: When the transistor to be tested is a transmission transistor, it includes: In the preset stage in step b, the voltage source connected to the power supply terminal of the memory cell is adjusted to a high level, the voltage source connected to the ground terminal of the memory cell is adjusted to a low level, the voltage source connected to the word line is adjusted to a high level, the voltage source connected to the bit line on one side of the transistor to be tested is adjusted to a low level, and the voltage source connected to the bit line on the other side is adjusted to a high level; During the measurement phase in step b, the voltage source connected to the bit line on the other side of the tube to be tested is kept at a high level, and the voltage source connected to the bit line on one side of the tube to be tested is adjusted to 20% of the high level; In step e, the gate voltage of the pass transistor is controlled by adjusting a voltage source connected to the word line.

10. A large-scale 6T SRAM array unit transistor threshold voltage measurement chip, characterized in that: The device comprises the measuring circuit according to any one of claims 1 to 5, an analog multiplexer connected with a bit line and a word line, an address decoder for generating a selection signal of the analog multiplexer, and a timing controller.

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