Multilayer ceramic capacitor and mounting structure of multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor and its mounting structure are provided to suppress the generation of "humming" without significantly compromising thinness (miniaturization) and high capacitance. The multilayer ceramic capacitor comprises a stack of multiple dielectric layers and multiple internal electrode layers. When an internal electrode layer disposed on a first main surface is designated as a first main surface internal electrode layer, and an internal electrode layer disposed on a second main surface is designated as a second main surface internal electrode layer, a first solid solution layer containing a second metal different from the first metal component is formed at the interface between the first main surface internal electrode layer and the dielectric layer, and a second solid solution layer containing the second metal is formed at the interface between the second main surface internal electrode layer and the dielectric layer. The concentration of the second metal in the second solid solution layer is higher than the concentration of the second metal in the first solid solution layer.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor and a mounting structure of the laminated ceramic capacitor. Background Art

[0002] A laminated ceramic capacitor is known, which comprises a laminated body having a plurality of dielectric layers and a plurality of internal electrode layers stacked together including ceramic materials, and an external electrode arranged on an end face of the laminated body. The laminated body comprises an inner layer portion including a portion of a plurality of dielectric layers and a plurality of internal conductor layers, and a first outer layer portion and a second outer layer portion which are arranged to sandwich the inner layer portion and each include a portion other than a portion of the plurality of dielectric layers, the first outer layer portion being arranged on the first main surface side, and the second outer layer portion being arranged on the second main surface side. In such a laminated ceramic capacitor, further miniaturization (thinning) and high capacitance are required, and as a material for the dielectric layer, a ferroelectric material with a relatively high dielectric constant is sometimes used.

[0003] However, such a dielectric layer has piezoelectricity and electrostriction, and therefore generates stress and mechanical strain when an electric field is applied. Such stress and mechanical strain become vibrations and are transmitted to the substrate on which the multilayer ceramic capacitor is mounted. In this way, the entire substrate becomes a sound reflection surface, generating vibration sound that becomes noise, the so-called "buzzing".

[0004] In order to suppress the occurrence of this "buzzing", a laminated ceramic capacitor is known in which the thickness of the lower outer layer portion is made thicker than the thickness of the upper outer layer portion to suppress the transmission of vibration from the laminated ceramic capacitor to the substrate (see Patent Documents 1 to 3).

[0005] Prior Art Literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2013-251522

[0008] Patent Document 2: Japanese Patent Application Publication No. 2015-65414

[0009] Patent Document 3: Japanese Patent Application Publication No. 2019-145684 Summary of the invention

[0010] Problem that the invention aims to solve

[0011] However, if the thickness of the lower outer layer portion is increased, either the thinning (downsizing) or the increasing of the capacitance of the multilayer ceramic capacitor will be greatly impaired.

[0012] An object of the present invention is to provide a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor that suppress the occurrence of "buzzing" without significantly compromising thinning (miniaturization) and increasing capacitance.

[0013] Means used to solve problems

[0014] The inventors of the present application have conducted intensive studies and have obtained the following new knowledge: the generation of "buzzing" can be suppressed without significantly increasing the thickness of the lower outer layer by adjusting the coverage of the main component metal of the lower internal electrode layer.

[0015] Thus, the laminated ceramic capacitor of the present invention comprises: a laminated body, which is laminated with a plurality of dielectric layers and a plurality of internal electrode layers including ceramic materials, and has a first main surface and a second main surface opposite to each other in a lamination direction, two side surfaces opposite to each other in a width direction intersecting the lamination direction, and two end surfaces opposite to each other in a length direction intersecting the lamination direction and the width direction; and two external electrodes, which are respectively arranged on the two end surfaces of the laminated body. The plurality of internal electrode layers respectively include a first metal as a main component. When the internal electrode layer arranged on the first main surface side among the plurality of internal electrode layers is set as a first main surface side internal electrode layer, and the internal electrode layer arranged on the second main surface side among the plurality of internal electrode layers is set as a second main surface side internal electrode layer, a first solid solution layer in which a second metal different from the first metal is solid-dissolved is formed at an interface between the first main surface side internal electrode layer and the dielectric layer, and a second solid solution layer in which the second metal is solid-dissolved is formed at an interface between the second main surface side internal electrode layer and the dielectric layer. The concentration of the second metal in the second solid solution layer is higher than the concentration of the second metal in the first solid solution layer.

[0016] In addition, a mounting structure of a multilayer ceramic capacitor according to the present invention includes a circuit board and the multilayer ceramic capacitor described above. The multilayer ceramic capacitor is mounted on the circuit board such that the second main surface faces the circuit board.

[0017] Effects of the Invention

[0018] According to the present invention, the occurrence of "buzzing" can be suppressed without significantly impairing the thinning (miniaturization) and increasing the capacitance of a multilayer ceramic capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 1 is a perspective view showing a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor according to the present embodiment.

[0020] Figure 2 yes Figure 1 A cross-sectional view (LT cross-sectional view) taken along line II-II of a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor shown.

[0021] Figure 3 yes Figure 1FIG. 1 is a cross-sectional view (WT cross-sectional view) taken along line III-III of a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor.

[0022] Figure 4 yes Figure 2 An enlarged cross-sectional view of an internal electrode layer of a laminated body in a laminated ceramic capacitor shown.

[0023] Figure 5 It is a cross-sectional view (LT cross section) of a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor according to a modification of the present embodiment.

[0024] Figure 6 It is a cross-sectional view (WT cross section) of a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor according to a modification of the present embodiment.

[0025] Description of Reference Numerals

[0026] 1. Multilayer ceramic capacitor;

[0027] 10 laminate;

[0028] 20 dielectric layer;

[0029] 30 internal electrode layer;

[0030] 301 first main surface side internal electrode layer;

[0031] 302 second main surface side internal electrode layer;

[0032] 301A first solid solution layer;

[0033] 302A second solid solution layer;

[0034] 31 first internal electrode layer;

[0035] 311 a first opposing electrode portion;

[0036] 312 first extraction electrode portion;

[0037] 313 diffusion layer;

[0038] 32 second internal electrode layer;

[0039] 321 second opposing electrode portion;

[0040] 322 second extraction electrode portion;

[0041] 323 diffusion layer;

[0042] 40 external electrodes;

[0043] 41 a first external electrode;

[0044] 415 first base electrode layer;

[0045] 416 first coating layer;

[0046] 42 second external electrode;

[0047] 425 second base electrode layer;

[0048] 426 second coating layer;

[0049] 100 inner part;

[0050] 101 first outer part;

[0051] 102 second outer part;

[0052] L30: electrode opposing part;

[0053] LG1 first end gap;

[0054] LG2 second end gap;

[0055] W30: electrode opposing part;

[0056] WG1 first side gap;

[0057] WG2 second side gap;

[0058] L length direction;

[0059] T stacking direction;

[0060] W width direction;

[0061] LS1 first end face;

[0062] LS2 second end face;

[0063] TS1 first main surface;

[0064] TS2 second main surface;

[0065] WS1 first side;

[0066] WS2 Second side. DETAILED DESCRIPTION

[0067] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. It should be noted that the same reference numerals are given to the same or corresponding parts in each drawing.

[0068] <Multilayer Ceramic Capacitors>

[0069] Figure 1 1 is a perspective view showing a multilayer ceramic capacitor according to the present embodiment. Figure 2 yes Figure 1 The II-II line cross-sectional view of the multilayer ceramic capacitor shown in FIG. Figure 3 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line III-III shown in FIG. Figure 1 to Figure 3 The illustrated multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 . The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0070] exist Figure 1 to Figure 3 , an XYZ orthogonal coordinate system is shown. The X direction is the length direction L of the laminated ceramic capacitor 1 and the laminated body 10, the Y direction is the width direction W of the laminated ceramic capacitor 1 and the laminated body 10, and the Z direction is the stacking direction T of the laminated ceramic capacitor 1 and the laminated body 10. Thus, Figure 2 The section shown is also called the LT section. Figure 3 The section shown is also referred to as the WT section.

[0071] It should be noted that the longitudinal direction L, the width direction W, and the stacking direction T are not necessarily orthogonal to each other, and may be intersecting to each other.

[0072] The stacked body 10 has a substantially rectangular parallelepiped shape and has first and second main surfaces TS1 and TS2 facing each other in the stacking direction T, first and second side surfaces WS1 and WS2 facing each other in the width direction W, and first and second end surfaces LS1 and LS2 facing each other in the longitudinal direction L.

[0073] It is preferable to give roundness to the corners and ridges of the laminate 10. The corner is a portion where three surfaces of the laminate 10 intersect, and the ridge is a portion where two surfaces of the laminate 10 intersect.

[0074] like Figure 2 and Figure 3 As shown, the laminate 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 laminated in a lamination direction T. In addition, the laminate 10 includes an inner layer portion 100 in the lamination direction T, and a first outer layer portion 101 and a second outer layer portion 102 disposed to sandwich the inner layer portion 100 .

[0075] The inner layer portion 100 includes a part of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged to face each other via the dielectric layer 20. The inner layer portion 100 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0076] The first outer layer portion 101 is arranged on the first main surface TS1 side of the stacked body 10, and the second outer layer portion 102 is arranged on the second main surface TS2 side of the stacked body 10. More specifically, the first outer layer portion 101 is arranged between the internal electrode layer 30 closest to the first main surface TS1 among the plurality of internal electrode layers 30 and the first main surface TS1, and the second outer layer portion 102 is arranged between the internal electrode layer 30 closest to the second main surface TS2 among the plurality of internal electrode layers 30 and the second main surface TS2. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, and each include a portion other than a portion used for the inner layer portion 100 among the plurality of dielectric layers 20. The first outer layer portion 101 and the second outer layer portion 102 are portions that function as protective layers for the inner layer portion 100.

[0077] As the material of the dielectric layer 20, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component can be used. In addition, as the material of the dielectric layer 20, Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds can also be added as auxiliary components.

[0078] The thickness of the dielectric layer 20 is not particularly limited, but is preferably 0.40 μm or more and 0.50 μm or less, and more preferably 0.40 μm or more and 0.45 μm or less. The number of dielectric layers 20 is not particularly limited, but is preferably 100 or more and 2000 or less, for example. It should be noted that the number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer and the number of dielectric layers in the outer layer.

[0079] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the stacking direction T of the stacked body 10.

[0080] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312 , and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .

[0081] The opposing electrode portion 311 and the opposing electrode portion 321 are opposed to each other via the dielectric layer 20 in the stacking direction T of the stacked body 10. The shapes of the opposing electrode portion 311 and the opposing electrode portion 321 are not particularly limited, and may be, for example, substantially rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are portions that generate electrostatic capacitance and substantially function as capacitors.

[0082] The lead electrode portion 312 extends from the counter electrode portion 311 toward the first end surface LS1 of the stacked body 10 and is exposed at the first end surface LS1. The lead electrode portion 322 extends from the counter electrode portion 321 toward the second end surface LS2 of the stacked body 10 and is exposed at the second end surface LS2. The shapes of the lead electrode portions 312 and 322 are not particularly limited, and may be, for example, substantially rectangular.

[0083] Thus, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap exists between the first internal electrode layer 31 and the second end surface LS2 of the stack 10, that is, the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap exists between the second internal electrode layer 32 and the first end surface LS1 of the stack 10, that is, the first external electrode 41.

[0084] The first internal electrode layer 31 and the second internal electrode layer 32 include metal Ni as a main component. In addition, the first internal electrode layer 31 and the second internal electrode layer 32 may include at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals such as Ag-Pd alloys as a main component, or may include at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals such as Ag-Pd alloys as a component other than the main component. In addition, the first internal electrode layer 31 and the second internal electrode layer 32 may include particles of a dielectric having the same composition system as the ceramic included in the dielectric layer 20 as a component other than the main component. It should be noted that in this specification, the metal of the main component is defined as the metal component with the highest weight %.

[0085] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 0.30 μm or more and 0.40 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 10 or more and 1000 or less.

[0086] like Figure 3As shown, the stack 10 has an electrode opposing portion W30 in which the internal electrode layer 30 is opposed in the width direction W, and a first side gap portion WG1 and a second side gap portion WG2 configured to sandwich the electrode opposing portion W30. The first side gap portion WG1 is located between the electrode opposing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode opposing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end portion on the first side surface WS1 side of the internal electrode layer 30 and the first side surface WS1, and the second side gap portion WG2 is located between the end portion on the second side surface WS2 side of the internal electrode layer 30 and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap portion WG1 and the second side gap portion WG2 are portions that function as protective layers of the internal electrode layer 30. It should be noted that the first side gap portion WG1 and the second side gap portion WG2 are also referred to as W gaps.

[0087] like Figure 2 As shown, the stacked body 10 has an electrode opposing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 are opposed to each other in the length direction L, a first end gap portion LG1, and a second end gap portion LG2. The first end gap portion LG1 is located between the electrode opposing portion L30 and the first end surface LS1, and the second end gap portion LG2 is located between the electrode opposing portion L30 and the second end surface LS2. More specifically, the first end gap portion LG1 is located between the end portion of the second internal electrode layer 32 on the first end surface LS1 side and the first end surface LS1, and the second end gap portion LG2 is located between the end portion of the first internal electrode layer 31 on the second end surface LS2 side and the second end surface LS2. The first end gap portion LG1 does not include the second internal electrode layer 32, but includes the first internal electrode layer 31 and the dielectric layer 20, and the second end gap portion LG2 does not include the first internal electrode layer 31, but includes the second internal electrode layer 32 and the dielectric layer 20. The first end gap LG1 is a portion that functions as an electrode lead-out portion of the first internal electrode layer 31 to the first end surface LS1, and the second end gap LG2 is a portion that functions as an electrode lead-out portion of the second internal electrode layer 32 to the second end surface LS2. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0088] It should be noted that the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32 are located at the electrode opposing portion L30. In addition, the lead electrode portion 312 of the first internal electrode layer 31 is located at the first end gap portion LG1, and the lead electrode portion 322 of the second internal electrode layer 32 is located at the second end gap portion LG2.

[0089] The dimensions of the stacked body 10 are not particularly limited, but preferably, for example, the length in the longitudinal direction L is 0.05 mm to 1.00 mm, the width in the width direction W is 0.10 mm to 0.50 mm, and the thickness in the stacking direction T is 0.10 mm to 0.50 mm.

[0090] It should be noted that in the laminate 10, when the dimension in the length direction L is set to L1, the dimension in the width direction W is set to W1, and the dimension in the stacking direction T is set to T1, L1>T1>W1 may be satisfied. Thus, a laminated ceramic capacitor having a height (thickness) that satisfies the specified L1 and W1 and increases T1 can be obtained, and miniaturization and high capacitance can be achieved.

[0091] It should be noted that, as a method for measuring the thickness of the dielectric layer 20 and the internal electrode layer 30, for example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding using a scanning electron microscope is cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the longitudinal direction, or an average value of the measured values ​​at multiple locations in the stacking direction.

[0092] Similarly, as a method for measuring the thickness of the laminate 10, for example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding, or the WT cross section near the center in the length direction of the laminate exposed by grinding using a scanning electron microscope is cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the length direction or the width direction.

[0093] Similarly, as a method for measuring the length of the laminate 10, for example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding with a scanning electron microscope is mentioned. In addition, each value may be an average value of the measured values ​​at a plurality of locations in the lamination direction.

[0094] Similarly, as a method for measuring the width of the laminate 10, for example, a method of observing a WT cross section near the longitudinal center of the laminate exposed by grinding with a scanning electron microscope is given. In addition, each value may be an average value of measured values ​​at a plurality of locations in the lamination direction.

[0095] The external electrode 40 includes a first external electrode 41 and a second external electrode 42 .

[0096] The first external electrode 41 is disposed on the first end surface LS1 of the stack 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may also extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. In addition, the first external electrode 41 may also extend from the first end surface LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0097] The second external electrode 42 is arranged on the second end surface LS2 of the stack 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may also extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2. In addition, the second external electrode 42 may also extend from the second end surface LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0098] The first external electrode 41 includes a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 includes a second base electrode layer 425 and a second plating layer 426. It should be noted that the first external electrode 41 may include only the first plating layer 416, and the second external electrode 42 may include only the second plating layer 426.

[0099] The first base electrode layer 415 and the second base electrode layer 425 may also be sintered layers including metal and glass. As glass, a glass component including at least one selected from B, Si, Ba, Mg, Al or Li is cited. As a specific example, borosilicate glass can be used. As a metal, Cu is included as a main component. In addition, as a metal, for example, at least one selected from metals such as Ni, Ag, Pd or Au or alloys such as Ag-Pd alloys may be included as a main component, and at least one selected from metals such as Ni, Ag, Pd or Au or alloys such as Ag-Pd alloys may be included as a component other than the main component.

[0100] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate by an impregnation method and firing it. It should be noted that the fired layer can be fired after the internal electrode layer is fired, or it can be fired at the same time as the internal electrode layer. In addition, the fired layer can also be a plurality of layers.

[0101] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be resin layers including conductive particles and a thermosetting resin. The resin layer may be formed on the above-mentioned fired layer, or may be formed directly on the laminate without forming a fired layer.

[0102] The resin layer is a layer obtained by applying a conductive paste including conductive particles and a thermosetting resin to a laminate by a coating method and firing the laminate. It should be noted that the resin layer can be fired after the internal electrode layer is fired, or it can be fired simultaneously with the internal electrode layer. In addition, the resin layer can also be a plurality of layers.

[0103] The thickness of each of the first foundation electrode layer 415 and the second foundation electrode layer 425 which are fired layers or resin layers is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0104] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be thin film layers of 1 μm or less in thickness formed by a thin film forming method such as sputtering or vapor deposition and in which metal particles are deposited.

[0105] The first plating layer 416 covers at least a portion of the first base electrode layer 415, and the second plating layer 426 covers at least a portion of the second base electrode layer 425. The first plating layer 416 and the second plating layer 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0106] The first plating layer 416 and the second plating layer 426 may also be formed of multiple layers. Preferably, they are a double-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being corroded by the solder when the ceramic electronic component is mounted, and the Sn plating layer can improve the wettability of the solder when the ceramic electronic component is mounted, so that it can be easily mounted.

[0107] The thickness of each of the first plating layer 416 and the second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0108] like Figure 1 to Figure 3 As shown in FIG. 1 , as a mounting structure of the multilayer ceramic capacitor 1 , the multilayer ceramic capacitor 1 is mounted on the circuit board CB such that the second main surface TS2 faces the circuit board CB.

[0109] 《Internal electrode layer》

[0110] Next, the internal electrode layers 30 , namely, the first internal electrode layers 31 and the second internal electrode layers 32 will be further described. Figure 4 yes Figure 2 An enlarged cross-sectional view of an internal electrode layer of a laminated body in a laminated ceramic capacitor shown in FIG. Figure 4As shown, the internal electrode layer 30, i.e., the first internal electrode layer 31 and the second internal electrode layer 32, which is arranged on the first main surface TS1 side than the center of the stacking direction T of the stack 10 is set as the first main surface side internal electrode layer 301, and the internal electrode layer 30, i.e., the first internal electrode layer 31 and the second internal electrode layer 32, which is arranged on the second main surface TS2 side than the center of the stacking direction T of the stack 10 is set as the second main surface side internal electrode layer 302.

[0111] A first solid solution layer 301A is formed at the interface between the first main surface side internal electrode layer 301 and the dielectric layer 20, and a secondary component metal such as Sn is dissolved in the first solid solution layer 301A, which is different from the primary component metal such as Ni. On the other hand, a second solid solution layer 302A is formed at the interface between the second main surface side internal electrode layer 302 and the dielectric layer 20, and a secondary component metal such as Sn is dissolved in the second solid solution layer 302A. The metal dissolved in the first solid solution layer 301A and the second solid solution layer 302A may be at least one metal selected from Sn, In, Ga, Zn, Bi, Pb, Fe, V, Y and Cu.

[0112] The concentration (content) of the secondary component metal such as Sn in the second solid solution layer 302A is higher than the concentration (content) of the secondary component metal such as Sn in the first solid solution layer 301A. In the internal electrode layer, a high concentration (content) of the secondary component metal such as Sn means a low concentration (content) of the main component metal such as Ni, that is, the coverage of the main component metal such as Ni is low.

[0113] By setting the second main surface TS2 side where the internal electrode layer with a low coverage of the main component metal such as Ni is arranged as the circuit substrate CB side and mounting the multilayer ceramic capacitor 1 on the circuit substrate CB, the generation of "buzzing" can be suppressed. Therefore, there is no need to thicken the second outer layer 102, so more internal electrode layers 30 can be arranged, and the multilayer ceramic capacitor 1 can be made thinner (smaller) and higher in capacitance.

[0114] The content (molar ratio) of the secondary component metal such as Sn in the first solid solution layer 301A is preferably 0.2 mol% or more and 0.8 mol% or less relative to 100 mol of the main component metal such as Ni. In contrast, the content (molar ratio) of the secondary component metal such as Sn in the second solid solution layer 302A is higher than the first solid solution layer 301A and is 1.5 mol% or more and 2.5 mol% or less relative to 100 mol of the main component metal such as Ni. It should be noted that the ratio of the first main surface side internal electrode layer 301 having the first solid solution layer 301A to the total number of internal electrode layers 30 is preferably 60% or more, and on the other hand, the ratio of the second main surface side internal electrode layer 302 having the second solid solution layer 302A to the total number of internal electrode layers 30 is preferably 40% or less.

[0115] Here, in order to achieve thinning (miniaturization) and increasing the capacitance of the multilayer ceramic capacitor 1, for example, thinning the dielectric layer 20 may be considered. However, thinning the dielectric layer 20 increases the electric field strength applied to each layer, and the life, that is, the reliability, of the multilayer ceramic capacitor 1 may be reduced.

[0116] In this regard, when the first solid solution layer 301A and the second solid solution layer 302A of the accessory component metal such as Sn are formed at the interface between the internal electrode layer 30 and the dielectric layer 20, the insulation is improved at the interface between the first solid solution layer 301A and the second solid solution layer 302A and the dielectric layer 20, and an increase in the electric field intensity can be suppressed in the dielectric layer 20. Therefore, a decrease in the life, that is, the reliability, of the multilayer ceramic capacitor 1 can be suppressed.

[0117] When the content of the secondary component metal such as Sn in the second solid solution layer 302A (and the first solid solution layer 301A) is less than 1.5 mol%, the effect of containing the secondary component metal such as Sn is small. On the other hand, when the content of the secondary component metal such as Sn in the first solid solution layer 301A (and the second solid solution layer 302A) exceeds 2.5 mol%, the melting point of the internal electrode layer 30 decreases, and sometimes the main component metal such as Ni of the internal electrode layer 30 is sphericalized. When the main component metal such as Ni is sphericalized, the internal electrode layer 30 becomes coarse locally, the dielectric layer 20 becomes thin locally, and the electric field strength increases locally, and the effect of containing the secondary component metal such as Sn is offset.

[0118] As a method for determining the mol% (molar ratio) of the content of the secondary component metal such as Sn in the first solid solution layer 301A relative to 100 mol of the primary component metal such as Ni in the first main surface side internal electrode layer 301, and the mol% (molar ratio) of the secondary component metal such as Sn in the second solid solution layer 302A relative to 100 mol of the primary component metal such as Ni in the second main surface side internal electrode layer 302, TEM analysis is cited. The internal electrode layer arranged in the stacking direction is divided into three regions, and 10 points of the internal electrode layer in the central part of each region are measured along the in-plane direction at a position 10 nm inward from the interface by TEM analysis, and the average is used as the molar ratio.

[0119] The thickness of the first solid solution layer 301A is preferably not less than 1 nm and not more than 20 nm. On the other hand, the thickness of the second solid solution layer 302A is preferably not less than 1 nm and not more than 20 nm.

[0120] As a method for measuring the thickness of the first solid solution layer 301A and the second solid solution layer 302A, similarly to the method for measuring the thickness of the dielectric layer 20 and the internal electrode layer 30 described above, for example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding is cited. As a measuring device, for example, wavelength dispersive X-ray analysis (WDX) or energy dispersive X-ray analysis (EDX), and a scanning electron microscope (SEM) or a transmission electron microscope (TEM) are cited. For the first solid solution layer 301A, the region where the content (molar ratio) of the secondary component metal such as Sn relative to 100 mol of the main component metal such as Ni is 0.2 mol% or more and 0.8 mol% or less is set as the thickness, and for the second solid solution layer 302A, the region where the content (molar ratio) of the secondary component metal such as Sn relative to 100 mol of the main component metal such as Ni is 1.5 mol% or more and 2.5 mol% or less is set as the thickness.

[0121] <Manufacturing method>

[0122] Next, a method for manufacturing the above-mentioned multilayer ceramic capacitor 1 is described. First, a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Sn is contained in the dielectric sheet. For example, an insulator sheet containing dielectric particles of a core-shell structure with Sn coated on the surface is used. The content of Sn in the dielectric sheet is different between the dielectric sheet adjacent to the internal electrode layer 301 on the first main surface side and the dielectric sheet adjacent to the internal electrode layer 302 on the second main surface side. In addition, a binder and a solvent are contained in the dielectric sheet and the conductive paste. As the binder and the solvent, known materials can be used.

[0123] Next, the conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. Screen printing, gravure printing, or the like can be used as a method for forming the internal electrode pattern.

[0124] Next, a predetermined number of dielectric sheets for the second outer layer 102 on which the internal electrode pattern is not printed are stacked. On the dielectric sheet for the second outer layer 102, dielectric sheets for the inner layer 100 on which the internal electrode pattern is printed are sequentially stacked. On the dielectric sheet for the inner layer 100, a predetermined number of dielectric sheets for the first outer layer 101 on which the internal electrode pattern is not printed are stacked. In this way, a stacked sheet is produced.

[0125] Next, the laminated sheets are pressed in the stacking direction by isostatic pressing or the like to produce a laminated block. Next, the laminated block is cut into a predetermined size to produce laminated small pieces. At this time, the corners and ridges of the laminated small pieces are rounded by roller grinding or the like.

[0126] Next, the stacked small pieces are fired to produce the stacked body 10. The firing temperature also depends on the material of the dielectric or the internal electrode, but is preferably 900°C or higher and 1400°C or lower.

[0127] At this time, a solid solution layer in which Sn originating from the dielectric layer 20 is segregated and dissolved is formed at the interface between the internal electrode layer 30 and the dielectric layer 20. For example, as described above, the content of Sn is made different between the dielectric sheet adjacent to the internal electrode layer 301 on the first main surface side and the dielectric sheet adjacent to the internal electrode layer 302 on the second main surface side, thereby forming a first solid solution layer 301A in which Sn originating from the dielectric layer 20 is segregated and dissolved at the interface between the internal electrode layer 301 on the first main surface side and the dielectric layer 20, and forming a second solid solution layer 302A in which Sn originating from the dielectric layer 20 is segregated and dissolved at the interface between the internal electrode layer 302 on the second main surface side and the dielectric layer 20.

[0128] Next, the first end surface LS1 of the stacked body 10 is dipped in a conductive paste as an electrode material for the base electrode layer by using a dipping method, thereby applying a conductive paste for the first base electrode layer 415 to the first end surface LS1. Similarly, the second end surface LS2 of the stacked body 10 is dipped in a conductive paste as an electrode material for the base electrode layer by using a dipping method, thereby applying a conductive paste for the second base electrode layer 425 to the second end surface LS2. Thereafter, these conductive pastes are fired to form the first base electrode layer 415 and the second base electrode layer 425 as fired layers. The firing temperature is preferably 600° C. or higher and 900° C. or lower.

[0129] It should be noted that, as described above, a conductive paste including conductive particles and a thermosetting resin can be applied by a coating method and then fired to form the first base electrode layer 415 and the second base electrode layer 425 as resin layers, or the first base electrode layer 415 and the second base electrode layer 425 can be formed as thin films by a thin film forming method such as sputtering or evaporation.

[0130] Then, the first plating layer 416 is formed on the surface of the first foundation electrode layer 415 to form the first external electrode 41, and the second plating layer 426 is formed on the surface of the second foundation electrode layer 425 to form the second external electrode 42. Through the above steps, the above-mentioned multilayer ceramic capacitor 1 is obtained.

[0131] As described above, according to the multilayer ceramic capacitor 1 of the present embodiment, the first solid solution layer 301A in which a subcomponent metal such as Sn different from the main component metal such as Ni is dissolved is formed in the first main surface side internal electrode layer 301 arranged on the first main surface TS1 side, and the second solid solution layer 302A in which a subcomponent metal such as Sn different from the main component metal such as Ni is dissolved is formed in the second main surface side internal electrode layer 302 arranged on the second main surface TS2 side, and the concentration (content) of the subcomponent metal such as Sn in the second solid solution layer 302A is higher than the concentration (content) of the subcomponent metal such as Sn in the first solid solution layer 301A. In the internal electrode layer, the high concentration (content) of the subcomponent metal such as Sn means that the concentration (content) of the main component metal such as Ni is low, that is, the coverage of the main component metal such as Ni is low.

[0132] By setting the second main surface TS2 side where the internal electrode layer with a low coverage of the main component metal such as Ni is arranged as the circuit substrate CB side and mounting the multilayer ceramic capacitor 1 on the circuit substrate CB, the generation of "buzzing" can be suppressed. Therefore, there is no need to thicken the second outer layer 102, so more internal electrode layers 30 can be arranged, and the multilayer ceramic capacitor 1 can be made thinner (miniaturized) and have a higher capacitance. Therefore, the generation of "buzzing" can be suppressed without compromising the thinning (miniaturization) and high capacitance of the multilayer ceramic capacitor 1.

[0133] The embodiments of the present invention have been described above, but the present invention is not limited to the above-mentioned embodiments, and various changes and deformations can be made. For example, in the above-mentioned embodiments, a laminated ceramic capacitor in which the boundary between the first main surface side internal electrode layer 301 and the second main surface side internal electrode layer 302 is near the center of the stacking direction T of the laminate 10 is illustrated. However, the present invention is not limited to this, and the boundary between the first main surface side internal electrode layer 301 and the second main surface side internal electrode layer 302 may also be biased toward the first main surface TS1 side, or may be biased toward the second main surface TS2 side. Alternatively, an internal electrode layer different from these internal electrode layers may be arranged between the first main surface side internal electrode layer 301 and the second main surface side internal electrode layer 302. For example, a method may be adopted in which the concentration (content) of accessory metals such as Sn in the inherent layer of the internal electrode layer is gradually increased in two or more stages from the first main surface TS1 toward the second main surface TS2, or a method may be adopted in which a solid solution layer in which accessory metals such as Sn are dissolved is not formed in the internal electrode layer between the internal electrode layer 301 on the first main surface side and the internal electrode layer 302 on the second main surface side.

[0134] In the above-mentioned embodiment, a multilayer ceramic capacitor is exemplified in which the thickness of the second outer layer portion 102 is substantially the same as the thickness of the first outer layer portion 101. However, the present invention is not limited thereto, and other embodiments may be used. Figure 5 and Figure 6 As shown, the thickness of the second outer layer 102 is thicker than the thickness of the first outer layer 101. In other words, the distance between the internal electrode layer 30 closest to the second main surface TS2 and the second main surface TS2 may be greater than the distance between the internal electrode layer 30 closest to the first main surface TS1 and the first main surface TS1. In this modification, compared with the above-mentioned embodiment, the effect of thinning (miniaturization) and high capacitance becomes lower, but the effect of suppressing the generation of "buzzing" is higher. Therefore, in this modification, the generation of "buzzing" can be further suppressed without significantly damaging the thinning (miniaturization) and high capacitance of the stacked ceramic capacitor 1.

[0135] The thickness of the first outer layer 101 and the second outer layer 102 may be measured in the same manner as the thickness of the dielectric layer 20 and the internal electrode layer 30. For example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding using a scanning electron microscope is given. In addition, each value may be an average value of the measured values ​​at a plurality of locations in the longitudinal direction.

[0136] In addition, as a manufacturing method of a laminated ceramic capacitor, a process of subsequently providing a dielectric with side gaps in the side surfaces WS1 and WS2 in the width direction W of the laminated body 10 may be applied. In this case, in the laminated ceramic capacitor, the ends of both sides of the internal electrode layer in the width direction W are aligned (for example, aligned within an error of 5 μm).

Claims

1. A multilayer ceramic capacitor comprising: A laminated body having a plurality of dielectric layers and a plurality of internal electrode layers formed of a ceramic material, the laminated body having a first main surface and a second main surface opposite to each other in a lamination direction, two side surfaces opposite to each other in a width direction intersecting the lamination direction, and two end surfaces opposite to each other in a length direction intersecting the lamination direction and the width direction; and two external electrodes, which are respectively arranged on the two end surfaces of the stacked body, The plurality of internal electrode layers each include a first metal as a main component, When the internal electrode layers arranged on the first main surface side among the plurality of internal electrode layers are set as first main surface side internal electrode layers, and the internal electrode layers arranged on the second main surface side among the plurality of internal electrode layers are set as second main surface side internal electrode layers, A first solid solution layer in which a second metal different from the first metal is dissolved is formed at an interface between the first main surface side internal electrode layer and the dielectric layer. A second solid solution layer in which the second metal is dissolved is formed at an interface between the second main surface side internal electrode layer and the dielectric layer. A concentration of the second metal in the second solid solution layer is higher than a concentration of the second metal in the first solid solution layer.

2. The multilayer ceramic capacitor according to claim 1, wherein The content of the second metal in the first solid solution layer is 0.2 mol % or more and 0.8 mol % or less relative to 100 mol of the first metal, A content of the second metal in the second solid solution layer is 1.5 mol % or more and 2.5 mol % or less relative to 100 mol of the first metal.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: In the stacked body, when the dimension in the longitudinal direction is L1, the dimension in the width direction is W1, and the dimension in the stacking direction is T1, L1>T1>W1.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The laminated body has: an inner layer portion including a portion of the plurality of dielectric layers and the plurality of internal electrode layers; and a first outer layer portion and a second outer layer portion, each of which is arranged to sandwich the inner layer portion and includes a portion other than the portion of the plurality of dielectric layers, the first outer layer portion being arranged on the first main surface side, and the second outer layer portion being arranged on the second main surface side, The second outer layer portion is thicker than the first outer layer portion.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The first metal is Ni.

6. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The second metal is Sn, In, Ga, Zn, Bi, Pb, Fe, V, Y or Cu.

7. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The thickness of the first solid solution layer is greater than or equal to 1 nm and less than or equal to 20 nm. The second solid solution layer has a thickness of 1 nm or more and 20 nm or less.

8. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The ratio of the first main surface side internal electrode layer to the plurality of internal electrode layers is 60% or more, The ratio of the second main surface side internal electrode layer to the plurality of internal electrode layers is 40% or less.

9. A mounting structure of a multilayer ceramic capacitor, comprising: a circuit board; and The multilayer ceramic capacitor according to any one of claims 1 to 8, The multilayer ceramic capacitor is mounted on the circuit substrate such that the second main surface faces the circuit substrate.

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