Ferroelectric field effect transistor, method of making the same and ferroelectric memory

Abstract

The present application relates to a ferroelectric field effect transistor, a preparation method thereof and a ferroelectric memory. The preparation method of the ferroelectric field effect transistor comprises the following steps: forming an oxide semiconductor layer on a substrate, the oxide semiconductor layer comprising a channel region and source and drain regions located on both sides of the channel region; forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer; forming a metal reaction layer to cover the source and drain regions and the top gate; annealing in an oxidizing atmosphere at 300-600 DEG C to induce the ferroelectric material layer to form a ferroelectric phase, to obtain a ferroelectric dielectric layer, and to cause the oxygen elements of the source and drain regions to be deprived by the metal reaction layer, to obtain a conductorized source region and a conductorized drain region; and to cause the metal reaction layer to spontaneously oxidize, to obtain a passivation layer; and forming a source electrode and a drain electrode in the passivation layer. The method realizes the functions of inducing the ferroelectric material layer to form a ferroelectric phase, conductorizing the source and drain regions and depositing a passivation layer through one annealing, and a high-performance and high-durability device is prepared.

Description

Technical Field

[0001] The present invention relates to the technical field of memory, and in particular to a ferroelectric field effect transistor, a preparation method thereof, and a ferroelectric memory. Background Art

[0002] Ferroelectric Field-Effect Transistor (FeFET) is a single-transistor memory that uses a ferroelectric thin film as the gate dielectric layer. Its working principle is to use the different remnant polarization states of the ferroelectric thin film under an applied voltage to adjust the surface state of the semiconductor, thereby changing the conduction state between the source and drain to distinguish between the two logic states of "0" and "1", thereby realizing the function of non-volatile information storage.

[0003] FeFETs have the advantages of simple structure, low power consumption, non-destructive readout, compatibility with complementary metal oxide semiconductor (CMOS) processes, and the ability to implement integrated circuit processes. They have very broad application prospects in next-generation high-density storage technologies. In the past few years, FeFETs based on oxide semiconductor channel layers have made great progress, but there are still problems with low device performance and poor durability, which limit the commercial application of FeFETs. Summary of the Invention

[0004] Based on this, it is necessary to provide a ferroelectric field effect transistor with high device performance and good durability, a preparation method thereof, and a ferroelectric memory.

[0005] The above-mentioned object of the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a method for preparing a ferroelectric field effect transistor, comprising the following steps:

[0007] forming an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer includes a channel region and a source region and a drain region located on both sides of the channel region;

[0008] forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer;

[0009] forming a metal reaction layer to cover the source region, the drain region and the top gate;

[0010] Annealing at 300° C. to 600° C. in an oxidizing atmosphere to induce the ferroelectric material layer to form a ferroelectric phase to obtain a ferroelectric dielectric layer, and causing the oxygen elements in the source region and the drain region to be captured by the metal reaction layer to obtain a conductive source region and a conductive drain region, and causing the metal reaction layer to spontaneously oxidize to obtain a passivation layer;

[0011] A source electrode and a drain electrode are formed in the passivation layer.

[0012] In one embodiment, the oxidizing atmosphere includes one or more of oxygen, air and ozone.

[0013] In one embodiment, the oxidizing atmosphere satisfies one or more of the following conditions:

[0014] 1) The volume fraction of oxygen is ≥10%;

[0015] 2) The volume fraction of ozone is ≥0.02%;

[0016] 3) The pressure of the oxidizing atmosphere is 0.1 atm to 1 atm.

[0017] In one embodiment, the annealing satisfies one or more of the following conditions:

[0018] 1) Annealing time is 20s to 600s;

[0019] 2) The heating rate is 10℃ / s to 30℃ / s;

[0020] 3) The cooling rate is 1℃ / s~10℃ / s.

[0021] In one embodiment, the oxide semiconductor layer satisfies one or more of the following conditions:

[0022] 1) The oxide semiconductor layer is an indium-based oxide semiconductor layer;

[0023] 2) The thickness of the oxide semiconductor layer is 5 nm to 50 nm.

[0024] In one embodiment, the metal reaction layer satisfies one or more of the following conditions:

[0025] 1) The metal reaction layer is a titanium reaction layer and / or an aluminum reaction layer;

[0026] 2) The thickness of the metal reaction layer is 2nm to 10nm.

[0027] In one embodiment, the ferroelectric material layer satisfies one or more of the following conditions:

[0028] 1) The ferroelectric material includes one or more of doped hafnium oxide, strontium bismuth tantalate, lead zirconate titanate, barium titanate, bismuth ferrite, cadmium pyroniobate, and zinc metastannate;

[0029] 2) The thickness of the ferroelectric material layer is 3 nm to 50 nm.

[0030] In one embodiment, the ferroelectric field effect transistor satisfies one or more of the following conditions:

[0031] 1) The material of the top gate, the source electrode, and the drain electrode includes one or more of tungsten, titanium, copper, aluminum, platinum, nickel, molybdenum, titanium nitride, tungsten nitride, tantalum nitride, titanium aluminum nitride, titanium carbide, tungsten disilicide, indium tin oxide, and molybdenum-titanium alloy;

[0032] 2) The thickness of the top gate, the source electrode and the drain electrode is 20 nm to 100 nm.

[0033] In a second aspect, the present invention provides a ferroelectric field effect transistor, which is manufactured using the above-mentioned method for manufacturing a ferroelectric field effect transistor.

[0034] According to a third aspect of the present invention, a ferroelectric memory is provided, which includes the ferroelectric field effect transistor described above.

[0035] The ferroelectric field-effect transistor prepared by the present invention adopts a top-gate self-aligned structure. The top gate is located above the channel region of the oxide semiconductor layer, which can serve as a mask to effectively protect the channel region and prevent etching damage to the channel region during different process steps. In addition, there is no overlap between the top gate and the source and drain electrodes, avoiding the generation of parasitic capacitance and its interference with device performance, thereby improving the reliability and durability of the device. Furthermore, annealing at 300°C to 600°C in an oxidizing atmosphere can promote the phase transformation of the ferroelectric material layer under the action of high temperature and the mechanical clamping action of the top gate and the oxide semiconductor layer, promoting the formation of ferroelectricity, thereby obtaining a ferroelectric dielectric layer with ferroelectric properties. At the same time, oxygen elements in the source and drain regions are captured by the metal reaction layer, forming oxygen vacancies within the source and drain regions, thereby increasing the carrier concentrations in the source and drain regions, thereby obtaining conductive source and drain regions. This, in turn, allows ohmic contacts to be formed between the source and the conductive source regions, and between the drain and the conductive drain regions, resulting in a ferroelectric field-effect transistor with higher carrier mobility and lower operating voltage. Furthermore, the metal reaction layer will spontaneously oxidize to form a metal oxide film, forming a passivation layer with excellent water and oxygen blocking properties, which is beneficial for improving the reliability and durability of the device. Thus, the present invention can simultaneously achieve the three functions of inducing the ferroelectric material layer to form a ferroelectric phase, promoting the conductive nature of the source and drain regions, and depositing the passivation layer through a single annealing step, thereby producing a ferroelectric field-effect transistor with high device performance and excellent durability, and having the advantages of simple process, ease of implementation, and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a flow chart of a method for preparing a ferroelectric field effect transistor in one embodiment;

[0037] Figure 2 Schematic diagram of the structure of the device after step S2 is completed in one embodiment;

[0038] Figure 3 Schematic diagram of the structure of the device after step S3 is completed in one embodiment;

[0039] Figure 4 Schematic diagram of the structure of the device after step S4 is completed in one embodiment;

[0040] Figure 5 Schematic diagram of the structure of the device after step S5 is completed in one embodiment;

[0041] Figure 6 Schematic diagram of the structure of the device after step S6 is completed in one embodiment;

[0042] Figure 7 Schematic diagram of the working principle of a ferroelectric field effect transistor in one embodiment.

[0043] Figure numerals: substrate 10, buffer layer 20, oxide semiconductor layer 30, channel region 31, source region 32, drain region 33, conductive source region 34, conductive drain region 35, ferroelectric material layer 41, ferroelectric dielectric layer 42, top gate 51, metal reaction layer 61, passivation layer 62, source 71, drain 72. DETAILED DESCRIPTION

[0044] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] Oxide semiconductors are a type of oxide formed from metals and oxygen that exhibit semiconductor properties. For FeFETs based on oxide semiconductor layers, their gate voltage-induced current, field-effect mobility, and switching characteristics are all affected by the source / drain contact characteristics. Therefore, selecting appropriate source / drain contact materials or achieving a good connection between the oxide semiconductor layer and the source / drain is crucial for achieving high-performance FeFET devices. Currently, a Schottky barrier exists between the oxide semiconductor layer and the source / drain of FeFET devices, resulting in high contact resistance and reduced performance.

[0047] In traditional thin-film transistor (TFT) devices, to improve the connection between the source / drain and the oxide semiconductor layer, conductive processes such as hydrogen doping, ion implantation, aluminum reaction, and plasma are typically used to increase the conductivity of the oxide semiconductor layer. However, when using hydrogen doping or ion implantation, doping elements such as H, B, P, and As easily diffuse within the oxide semiconductor layer, causing regions that should not be conductive to become conductive to varying degrees, reducing the width uniformity of the channel region and thus causing instability in device performance. Although the aluminum reaction method does not cause diffusion of conductive regions, its application in FeFET devices requires two anneals: one to induce the aluminum film to react with the oxide semiconductor layer, and one to induce the ferroelectric material layer to form a ferroelectric phase. The conditions of the two anneals differ significantly, affecting both the oxide semiconductor layer and the ferroelectric material layer to varying degrees, leading to degradation of device performance. For the plasma method, after the conductorization process, not only is rapid annealing required to induce the formation of a ferroelectric phase, but a passivation layer that isolates water and oxygen must also be deposited. For example, a silicon nitride passivation layer or a silicon oxynitride passivation layer is formed by plasma enhanced chemical vapor deposition (PECVD). However, the growth of these passivation layers will also induce the diffusion of hydrogen elements in the oxide semiconductor layer, which not only affects the electrical properties of the device, but also increases the process complexity and production cost of the entire device.

[0048] Based on this, the first aspect of the present invention provides a method for preparing a ferroelectric field effect transistor, comprising the following steps:

[0049] forming an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer includes a channel region and a source region and a drain region located on both sides of the channel region;

[0050] forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer;

[0051] forming a metal reaction layer to cover the source region, the drain region and the top gate;

[0052] In an oxidizing atmosphere, rapid annealing is performed at 300° C. to 600° C. to induce the ferroelectric material layer to form a ferroelectric phase to obtain a ferroelectric dielectric layer, and oxygen elements in the source region and the drain region are captured by the metal reaction layer to obtain a conductive source region and a conductive drain region, and the metal reaction layer is spontaneously oxidized to obtain a passivation layer;

[0053] A source electrode and a drain electrode are formed in the passivation layer.

[0054] It can be understood that the ferroelectric material layer does not have ferroelectricity, and the ferroelectric dielectric layer has ferroelectricity.

[0055] The ferroelectric field-effect transistor prepared by the present invention adopts a top-gate self-aligned structure. The top gate is located above the channel region of the oxide semiconductor layer, which can serve as a mask to effectively protect the channel region and prevent etching damage to the channel region during different process steps. In addition, there is no overlap between the top gate and the source and drain electrodes, avoiding the generation of parasitic capacitance and its interference with device performance, thereby improving the reliability and durability of the device. Furthermore, annealing at 300°C to 600°C in an oxidizing atmosphere can promote the phase transformation of the ferroelectric material layer under the action of high temperature and the mechanical clamping action of the top gate and the oxide semiconductor layer, promoting the formation of ferroelectricity, thereby obtaining a ferroelectric dielectric layer with ferroelectric properties. At the same time, oxygen elements in the source and drain regions are captured by the metal reaction layer, forming oxygen vacancies within the source and drain regions, thereby increasing the carrier concentrations in the source and drain regions, thereby obtaining conductive source and drain regions. This, in turn, allows ohmic contacts to be formed between the source and the conductive source regions, and between the drain and the conductive drain regions, resulting in a ferroelectric field-effect transistor with higher carrier mobility and lower operating voltage. Furthermore, the metal reaction layer will spontaneously oxidize to form a metal oxide film, forming a passivation layer with excellent water and oxygen blocking properties, which is beneficial for improving the reliability and durability of the device. Thus, the present invention can simultaneously achieve the three functions of inducing the ferroelectric material layer to form a ferroelectric phase, promoting the conductive nature of the source and drain regions, and depositing the passivation layer through a single annealing step, thereby producing a ferroelectric field-effect transistor with high device performance and excellent durability, and having the advantages of simple process, ease of implementation, and low cost.

[0056] See also Figure 1 , which is a flow chart of a method for preparing a ferroelectric field effect transistor in one embodiment, comprising the following steps:

[0057] S1: providing a substrate.

[0058] In some embodiments, the base includes a substrate and a buffer layer on the substrate.

[0059] A buffer layer is formed between the substrate and the oxide semiconductor layer, which can prevent lattice mismatch between the substrate and the oxide semiconductor layer and improve the growth quality of the oxide semiconductor film.

[0060] In some embodiments, the substrate satisfies one or more of the following conditions:

[0061] 1) The substrate is one or more of a silicon substrate, a glass substrate, a metal substrate, and a polymer substrate;

[0062] 2) The buffer layer is a silicon dioxide buffer layer and / or an aluminum oxide buffer layer;

[0063] 3) The thickness of the buffer layer is 1 nm to 300 nm.

[0064] It can be understood that the silicon substrate can be an undoped silicon substrate, a p-type doped silicon substrate or an n-type doped silicon substrate; the glass substrate can be a quartz glass substrate, a borosilicate glass substrate, a soda glass substrate, a potassium glass substrate, a lead glass substrate or an aluminum-magnesium glass substrate; the metal substrate can be a copper foil substrate or an aluminum foil substrate; the polymer substrate can be a polyimide (PI) substrate, a polyethylene terephthalate (PET) substrate, a polycarbonate (PC) substrate or a polymethyl methacrylate (PMMA) substrate.

[0065] In some more preferred embodiments, the substrate is an n-type doped silicon substrate.

[0066] In some specific embodiments, the method for forming the buffer layer includes the following steps: forming a silicon dioxide buffer layer with a thickness of 1 nm to 300 nm on the substrate by a thermal growth oxidation method or a PECVD method.

[0067] In some specific embodiments, the method for forming a buffer layer includes the following steps: depositing an aluminum oxide film on a substrate by atomic layer deposition (ALD), and then introducing ozone oxidation for 20 minutes to obtain an aluminum oxide buffer layer with a thickness of 1 nm to 5 nm.

[0068] S2: forming an oxide semiconductor layer on the substrate, wherein the oxide semiconductor layer includes a channel region and a source region and a drain region located on both sides of the channel region.

[0069] See also Figure 2 , which is a schematic structural diagram of the device after step S2 is completed in one embodiment, from bottom to top it is a substrate 10, a buffer layer 20 and an oxide semiconductor layer 30, and the oxide semiconductor layer 30 is defined as a channel region 31 and a source region 32 and a drain region 33 located on both sides of the channel region 31.

[0070] In some embodiments, the oxide semiconductor layer 30 satisfies one or more of the following conditions:

[0071] 1) The oxide semiconductor layer 30 is an indium-based oxide semiconductor layer;

[0072] 2) The thickness of the oxide semiconductor layer 30 is 5 nm to 50 nm.

[0073] Indium-based oxide has the advantages of excellent electrical properties, high transmittance, and good uniformity over a large area. In addition, there is no low dielectric constant interface layer formed between the indium-based oxide material and the ferroelectric layer, and there is very little interface charge capture, which can significantly improve the performance of ferroelectric field-effect transistors, reduce power consumption, and reduce process complexity.

[0074] In some more preferred embodiments, the indium-based oxide includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium gallium zinc tin oxide (IGZTO).

[0075] It can be understood that the oxide semiconductor layer 30 can be a single-layer thin film made of one indium-based oxide material among ITO, IZO, IGZO, IGTO, IZTO and IGZTO, or a composite thin film obtained by stacking multiple single-layer thin films.

[0076] In some specific embodiments, the method for forming the oxide semiconductor layer 30 includes the following steps: placing an IGZO target and a substrate in a reaction chamber of a magnetron sputtering apparatus and evacuating the chamber; introducing oxygen and argon gases into the reaction chamber, and then performing magnetron sputtering at room temperature to deposit an IGZO semiconductor layer with a thickness of 5 nm to 50 nm on the substrate; and using a photolithography process to define the oxide semiconductor layer pattern for each device. The molar ratio of indium, gallium, and zinc in the IGZO target is 1:1:1; and the flow rate ratio of oxygen and argon is 1:(1-9).

[0077] S3: forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer.

[0078] See also Figure 3 , which is a schematic structural diagram of the device after step S3 is completed in one embodiment, wherein the ferroelectric material layer 41 is located between the channel region 31 and the top gate 51 .

[0079] In some embodiments, the ferroelectric material layer 41 satisfies one or more of the following conditions:

[0080] 1) The ferroelectric material includes one or more of doped hafnium oxide, strontium bismuth tantalate (SBT), lead zirconate titanate (PZT), barium titanate (BaTiO3), bismuth ferrite (BiFeO3), cadmium pyroniobate (Cd2Nb2O7) and zinc metastannate (ZnSnO3);

[0081] 2) The thickness of the ferroelectric material layer 41 is 3 nm to 50 nm.

[0082] It can be understood that doped hafnium oxide is a hafnium oxide-based material containing doping elements; wherein the doping elements include one or more of carbon (C), nitrogen (N), silicon (Si), magnesium (Mg), aluminum (Al), zirconium (Zr), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), gadolinium (Gd) and lanthanum (La).

[0083] In some more preferred embodiments, the ferroelectric material layer 41 is a doped hafnium oxide layer.

[0084] Doped hafnium oxide can maintain good ferroelectric properties at a very thin thickness (about 10nm), continuing the good compatibility of hafnium oxide with CMOS technology, which is conducive to the miniaturization of devices.

[0085] In some more preferred embodiments, the ferroelectric material layer 41 is hafnium zirconium oxide (HfZrO x ) material layer.

[0086] In some embodiments, HfZrO x The method for forming the material layer includes the following steps: using hafnium tetrachloride (HfCl4) or tetrakis(methylethylamino) hafnium (TEMAHf) as a precursor hafnium source, using tetrakis(methylethylamino) zirconium (TEMAZr) or tetrakis(dimethylamino) zirconium (TDMAZr) as a precursor zirconium source, using water or ozone as a precursor oxygen source, and using nitrogen as a purge gas, performing atomic layer deposition (ALD) at a temperature of 250°C to 400°C to deposit HfZrO with a thickness of 3nm to 50nm on the oxide semiconductor layer 30. x Thin film; use a mask to protect the HfZrO on the channel region 31 x film, and selectively etch away the HfZrO above the source region 32 and the drain region 33 x Thin film, thus obtaining HfZrO x Material layer.

[0087] In some embodiments, the top gate 51 satisfies one or more of the following conditions:

[0088] 1) The material of the top gate 51 includes one or more of tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), nickel (Ni), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium nitride (AlTiN), tungsten nitride (W2N) and molybdenum titanium alloy (MoTi);

[0089] 2) The thickness of the top gate 51 is 20 to 100 nm.

[0090] In some more preferred embodiments, the top gate 51 is a TiN top gate or a TaN top gate.

[0091] In some specific embodiments, the method for forming a TiN top gate includes the following steps: using a Ti target as a sputtering target material, introducing nitrogen and argon with a flow ratio of 1:4 into the reaction chamber after vacuuming, so that the chamber pressure of the reaction chamber is maintained at 0.1Pa~1.0Pa, performing magnetron sputtering at room temperature, and depositing a TiN film with a thickness of 20nm~200nm on the ferroelectric material layer 41; using a mask to protect the ferroelectric material layer 41 and the TiN film on the channel region 31, and using a mixed gas of carbon tetrafluoride (CF4) and carbon trifluoride (CHF3) to selectively etch away the TiN film above the source region 32 and the drain region 33, thereby obtaining a TiN top gate.

[0092] In some specific embodiments, the method for forming a TaN top gate includes the following steps: using a Ta target as a sputtering target, introducing nitrogen and argon with a flow ratio of 1:4 into the reaction chamber after vacuuming, so that the chamber pressure of the reaction chamber is maintained at 0.1Pa~1.0Pa, performing magnetron sputtering at room temperature, and depositing a TaN film with a thickness of 20nm~200nm on the ferroelectric material layer 41; using a mask to protect the ferroelectric material layer 41 and the TaN film on the channel region 31, and using a mixed gas of chlorine (Cl2) and boron trichloride (BCl3) or a mixed gas of carbon tetrafluoride (CF4) and carbon trifluoride (CHF3) to selectively etch away the TaN film above the source region 32 and the drain region 33, thereby obtaining a TaN top gate.

[0093] In some specific embodiments, the method for forming a ferroelectric material layer 41 and a top gate 51 on the channel region 31 includes the following steps: forming a ferroelectric thin film on the oxide semiconductor layer 30 using an ALD method; forming a gate film on the ferroelectric thin film using a magnetron sputtering method; using a mask to protect the ferroelectric film and the gate film on the channel region 31, and selectively etching the ferroelectric film and the electrode film above the source region 32 and the drain region 33, thereby forming a ferroelectric material layer 41 and a top gate 51 on the channel region 31.

[0094] S4: forming a metal reaction layer to cover the source region, the drain region and the top gate.

[0095] See also Figure 4 , which is a schematic diagram of the structure of the device after step S4 is completed in one embodiment.

[0096] In some embodiments, the metal reaction layer 61 satisfies one or more of the following conditions:

[0097] 1) The metal reaction layer 61 is a titanium reaction layer and / or an aluminum reaction layer;

[0098] 2) The thickness of the metal reaction layer 61 is 2 nm to 10 nm.

[0099] The two metal elements Ti and Al can not only capture the oxygen element in the source region 32 and the drain region 33, increase their carrier concentration, reduce their resistivity, and obtain the conductive source region 34 and the conductive drain region 35, but can also spontaneously oxidize during the rapid annealing process to form a titanium dioxide or aluminum oxide passivation layer with good water and oxygen blocking effect, thereby obtaining good ohmic contact between the source / drain, the passivation layer and the conductive source / drain region, and avoid introducing hydrogen to cause diffusion in the conductive area, thereby avoiding causing unevenness in the electrical characteristics of the device.

[0100] In some more preferred embodiments, the metal reaction layer 61 is an aluminum reaction layer.

[0101] In some specific embodiments, the method for forming the metal reaction layer 61 includes the following steps: using an Al target as a sputtering target, introducing argon gas into the reaction chamber after vacuuming, performing magnetron sputtering at room temperature, and depositing an Al reaction layer with a thickness of 2nm to 10nm on the source region 32, the drain region 33 and the top gate 51.

[0102] S5: Annealing at 300°C to 600°C in an oxidizing atmosphere to induce the ferroelectric material layer to form a ferroelectric phase to obtain a ferroelectric dielectric layer, and the oxygen elements in the source region and the drain region are captured by the metal reaction layer to obtain a conductive source region and a conductive drain region, and the metal reaction layer is spontaneously oxidized to obtain a passivation layer.

[0103] See also Figure 5 , which is a schematic diagram of the device structure after step S5 is completed in one embodiment. The ferroelectric material layer 41 on the channel region 31 is induced to form a ferroelectric dielectric layer 42 with ferroelectric properties. Oxygen is removed from the source region 32 and the drain region 33, reducing their resistivity and transforming them into conductive source region 34 and conductive drain region 35. The metal reaction layer 61 spontaneously oxidizes to form a passivation layer 62.

[0104] It is understood that the oxidizing atmosphere is an atmosphere with oxidizing ability, which can be pure oxygen, ozone, and a mixed gas containing oxygen and / or ozone. The mixed gas containing oxygen and / or ozone refers to a gas obtained by mixing at least one of oxygen and ozone with at least one of nitrogen, carbon dioxide, helium, neon, argon, and krypton, for example, air, compressed dry air (CDA), a mixed gas of oxygen and nitrogen, a mixed gas of oxygen and argon, a mixed gas of ozone and nitrogen, and a mixed gas of oxygen, ozone, and nitrogen.

[0105] In some embodiments, the oxidizing atmosphere includes one or more of oxygen, ozone, and air.

[0106] In some embodiments, the oxidizing atmosphere satisfies one or more of the following conditions:

[0107] 1) The volume fraction of oxygen is ≥10%;

[0108] 2) The volume fraction of ozone is ≥ 0.02%;

[0109] 3) The pressure of the oxidizing atmosphere is 0.1 atm to 1 atm.

[0110] In an oxidizing atmosphere, an oxygen volume fraction of 4% to 5% is considered a general oxidizing atmosphere, while an oxygen volume fraction greater than 5% is considered a strong oxidizing atmosphere. During rapid annealing, increasing the volume fraction of oxygen or ozone can enhance the oxidizing ability of the atmosphere, thereby reducing the rapid annealing time. An oxidizing atmosphere pressure of 0.1 atm to 1 atm ensures a high reaction concentration of oxygen and / or ozone, further accelerating the reaction rate and shortening the rapid annealing process.

[0111] In some embodiments, the annealing satisfies one or more of the following conditions:

[0112] 1) Annealing time is 20s to 600s;

[0113] 2) The heating rate is 10℃ / s to 30℃ / s;

[0114] 3) The cooling rate is 1℃ / s~10℃ / s.

[0115] Conventional techniques typically employ an annealing method after coating an Al film on an IGZO semiconductor layer to improve the resistivity of the source and drain regions. However, this annealing is typically performed in a pure nitrogen atmosphere, at a temperature not exceeding 300°C and for at least one hour. This makes it impossible to simultaneously achieve the three functions of conducting the source and drain regions, inducing a phase transformation in the ferroelectric material layer, and spontaneously oxidizing the metal reaction layer in a single annealing step within a very short period of time. In contrast, by regulating annealing conditions such as the annealing temperature, holding time, heating rate, and cooling time, and performing a rapid annealing in an oxidizing atmosphere, the ferroelectric material layer 41 can undergo a rapid phase transformation, resulting in a ferroelectric dielectric layer 42 with excellent ferroelectric properties. This simultaneously ensures that the source and drain regions 32 and 33 are fully conductive, and that the metal reaction layer 61 is completely oxidized to become a passivation layer 62. This also helps eliminate internal defects, improves the quality of each thin film layer, and effectively prevents degradation of device performance.

[0116] S6: forming a source electrode and a drain electrode in the passivation layer.

[0117] See also Figure 6 , which is a schematic diagram of the structure of the device after step S6 is completed in one embodiment.

[0118] In some embodiments, the method of forming the source 71 and the drain 72 in the passivation layer 62 includes the following steps: selectively etching the passivation layer 62 using a mixed gas of chlorine (Cl2) and boron trichloride (BCl3) through a photolithography process to form a source through-hole in the passivation layer 62 on the conductive source region 34, and forming a drain through-hole in the passivation layer 62 on the conductive drain region 35; forming the source 71 in the source through-hole and forming the drain 72 in the drain through-hole by using a magnetron sputtering method or an electron beam evaporation and lift-off method.

[0119] In some embodiments, the source 71 and the drain 72 satisfy one or more of the following conditions:

[0120] 1) The material of the source electrode 71 and the drain electrode 72 includes one or more of tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), nickel (Ni), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (AlTiN), tungsten nitride (W2N), titanium carbide (TiC), tungsten disilicide (WSi2) and indium tin oxide (ITO);

[0121] 2) The thickness of the source electrode 71 and the drain electrode 72 is 20 nm to 100 nm.

[0122] After forming the source electrode 71 and drain electrode 72 in the passivation layer 62 using the above materials, an ohmic contact junction can be formed between the source (drain) electrode / passivation layer / conductorized source (drain) region. On this basis, changing the thickness of the oxide semiconductor layer 30 can achieve a significant adjustment of the device's electrical characteristics, significantly reducing the contact resistance of the ohmic contact junction and improving the ability to inject electrons into the oxide semiconductor layer 30, thereby producing a high-performance FeFET device.

[0123] In some more preferred embodiments, the source electrode 71 and the drain electrode 72 are Ni electrodes.

[0124] In some specific embodiments, the method for forming the source electrode 71 and the drain electrode 72 includes the following steps: forming a 30 nm Ni electrode in the passivation layer 62 using a lift-off process.

[0125] In a second aspect, the present invention provides a ferroelectric field effect transistor, which is manufactured using the above-mentioned method for manufacturing a ferroelectric field effect transistor.

[0126] See also Figure 7 , which is a schematic diagram of the working principle of a ferroelectric field effect transistor in one embodiment. Figure 7In (a), a forward voltage greater than the coercive field of the ferroelectric dielectric layer is applied to the top gate, and the source and drain are grounded at the same time. The ferroelectric dielectric layer is positively polarized, and the direction of the electric field points to the upper surface of the channel region, attracting negative compensation charges to the upper surface of the channel region, causing the channel region to be in an accumulation state. At this time, the device is in a low threshold voltage state, or a "1" logic state. Figure 7 In (b), a reverse voltage greater than the coercive field of the ferroelectric layer is applied to the top gate, causing the ferroelectric layer to become negatively polarized. The electric field is directed toward the bottom surface of the top gate, attracting positive compensation charges to the top surface of the channel region, causing the channel region to enter a depleted state. At this point, the device is in a high threshold voltage state, or a logic state of "0." Through the above-mentioned rapid annealing process in a high temperature and oxygen-rich atmosphere, the metal reaction layer is used to make the source and drain regions conductive, improving the overlap between the source and drain electrodes and the oxide semiconductor layer and significantly reducing the contact resistance, thereby obtaining a ferroelectric field-effect transistor with low operating voltage and high carrier mobility.

[0127] According to a third aspect of the present invention, a ferroelectric memory is provided, which includes the ferroelectric field effect transistor described above.

[0128] Understandably, although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0129] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above-described embodiments merely represent several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art may make several modifications and improvements without departing from the concept of the present invention, and these modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be based on the appended claims, and the description and drawings may be used to interpret the content of the claims.

Claims

1. A method for preparing a ferroelectric field effect transistor, characterized in that: The following steps are involved: forming an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer includes a channel region and a source region and a drain region located on both sides of the channel region; forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer; forming a metal reaction layer to cover the source region, the drain region and the top gate; Annealing at 300° C. to 600° C. in an oxidizing atmosphere to induce the ferroelectric material layer to form a ferroelectric phase to obtain a ferroelectric dielectric layer, and causing the oxygen elements in the source region and the drain region to be captured by the metal reaction layer to obtain a conductive source region and a conductive drain region, and causing the metal reaction layer to spontaneously oxidize to obtain a passivation layer; A source electrode and a drain electrode are formed in the passivation layer.

2. The method for preparing a ferroelectric field effect transistor according to claim 1, wherein: The oxidizing atmosphere includes one or more of oxygen, air and ozone.

3. The method for preparing a ferroelectric field effect transistor according to claim 2, wherein: The oxidizing atmosphere satisfies one or more of the following conditions: 1) The volume fraction of oxygen is ≥10%; 2) The volume fraction of ozone is ≥0.02%; 3) The pressure of the oxidizing atmosphere is 0.1 atm to 1 atm.

4. The method for preparing a ferroelectric field effect transistor according to claim 1, wherein: The annealing satisfies one or more of the following conditions: 1) Annealing time is 20s to 600s; 2) The heating rate is 10℃ / s to 30℃ / s; 3) The cooling rate is 1℃ / s~10℃ / s.

5. The method for preparing a ferroelectric field effect transistor according to any one of claims 1 to 4, wherein: The oxide semiconductor layer satisfies one or more of the following conditions: 1) The oxide semiconductor layer is an indium-based oxide semiconductor layer; 2) The thickness of the oxide semiconductor layer is 5 nm to 50 nm.

6. The method for preparing a ferroelectric field effect transistor according to claim 5, wherein: The metal reaction layer satisfies one or more of the following conditions: 1) The metal reaction layer is a titanium reaction layer and / or an aluminum reaction layer; 2) The thickness of the metal reaction layer is 2nm to 10nm.

7. The method for preparing a ferroelectric field effect transistor according to any one of claims 1 to 4, wherein: The ferroelectric material layer satisfies one or more of the following conditions: 1) The ferroelectric material includes one or more of doped hafnium oxide, strontium bismuth tantalate, lead zirconate titanate, barium titanate, bismuth ferrite, cadmium pyroniobate, and zinc metastannate; 2) The thickness of the ferroelectric material layer is 3 nm to 50 nm.

8. The method for preparing a ferroelectric field effect transistor according to any one of claims 1 to 4, wherein: The ferroelectric field effect transistor satisfies one or more of the following conditions: 1) The material of the top gate, the source electrode, and the drain electrode includes one or more of tungsten, titanium, copper, aluminum, platinum, nickel, molybdenum, titanium nitride, tungsten nitride, tantalum nitride, titanium aluminum nitride, titanium carbide, tungsten disilicide, indium tin oxide, and molybdenum-titanium alloy; 2) The thickness of the top gate, the source electrode and the drain electrode is 20 nm to 100 nm.

9. A ferroelectric field effect transistor, characterized in that: The ferroelectric field effect transistor is prepared by the preparation method of any one of claims 1 to 8.

10. A ferroelectric memory, characterized in that: Comprising the ferroelectric field effect transistor as claimed in claim 9.

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