Folded channel gallium nitride-based field effect transistor and preparation method thereof

Abstract

A folded channel gallium nitride-based field effect transistor and a preparation method thereof, the folded channel gallium nitride-based field effect transistor comprising: a base layer; a multi-heterojunction layer comprising a channel layer and a barrier layer alternately stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer extending from one side of a channel region to at least a portion of a trench on the multi-heterojunction layer; a current collapse suppression structure formed on the other side of the channel region on the multi-heterojunction layer and separated from the gallium nitride control layer by another portion of the trench; a source and a drain respectively contacting two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, the drain contacting a side surface and a portion of an upper surface of the current collapse suppression structure; a gate formed on the heterojunction between the source and the gallium nitride control layer; and a connection structure electrically connecting the source and the gallium nitride control layer through the top of the gate.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a field effect transistor, and more particularly to a folded channel gallium nitride-based field effect transistor and a method for preparing the same. Background Art

[0002] GaN material has a wide bandgap, high electron saturation velocity, high breakdown electric field, good corrosion resistance, radiation resistance, and high thermal conductivity, offering significant advantages under high-frequency, high-power, radiation, and high-temperature conditions. Furthermore, due to the strong spontaneous polarization and piezoelectric polarization effects of the Al(In,Ga)N / GaN heterojunction, it can spontaneously form a high-concentration, high-electron-mobility two-dimensional electron gas (2DEG).

[0003] However, in traditional Al(In,Ga)N / GaN field-effect transistors, a relatively long low-doped N-drift region is required to ensure that the device has a sufficiently high breakdown voltage. Generally, the larger the size of the low-doped N-drift region, the greater the withstand voltage rating, but its on-resistance also increases sharply. Moreover, the on-resistance also increases with voltage, resulting in a decrease in the current rating. In addition, in traditional Al(In,Ga)N / GaN field-effect transistors, increasing the size of the low-doped N-drift region also increases the device area, thereby increasing the device manufacturing cost. Summary of the Invention

[0004] To address the above issues, embodiments of the present disclosure provide a folded-channel gallium nitride-based field-effect transistor and a method for preparing the same, which increases the breakdown voltage of the field-effect transistor and reduces the on-resistance by increasing the size of the drift region in a limited field-effect transistor structure.

[0005] An embodiment of a first aspect of the present disclosure provides a folded channel gallium nitride-based field effect transistor, comprising:

[0006] A base layer, comprising a nitride buffer layer and a gallium nitride semi-insulating layer formed sequentially from bottom to top on a substrate, wherein a channel region including at least one parallel trench is formed on an upper surface of the gallium nitride semi-insulating layer;

[0007] A multi-heterojunction layer, comprising channel layers and barrier layers alternately stacked from bottom to top on the gallium nitride semi-insulating layer, wherein heterojunctions are formed between adjacent barrier layers and channel layers;

[0008] a gallium nitride control layer extending from one side of the channel region to at least a portion of the trench on the multi-heterojunction layer to control charge balance in the channel region corresponding to the field effect transistor in the on and off states;

[0009] A current collapse suppression structure is formed on the multi-heterojunction layer on the other side of the channel region and is separated from the gallium nitride control layer by another portion of the trench. The current collapse suppression structure is adapted to provide hole injection after a high drain voltage stress, thereby effectively releasing electrons trapped near the drain on the channel surface, suppressing the current collapse effect, and improving the dynamic conduction characteristics of the device.

[0010] a source electrode and a drain electrode, respectively contacting two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, wherein the drain electrode contacts a side surface and a portion of an upper surface of the current collapse suppression structure;

[0011] A gate is formed on the multi-heterojunction layer between the source and the gallium nitride control layer;

[0012] The connection structure passes through the top of the gate to electrically connect the source electrode and the gallium nitride control layer.

[0013] According to an embodiment of the present disclosure, in the multi-heterojunction layer, the thickness of each barrier layer is between 1 nm and 50 nm; the thickness of the channel layer is between 5 nm and 500 nm;

[0014] Preferably, the material constituting the barrier layer is one of AlN, AlGaN, AlInN, and AlInGaN.

[0015] According to an embodiment of the present disclosure, the gallium nitride regulation layer and the current collapse suppression structure both include a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top;

[0016] Preferably, the thickness of the lightly doped P-type gallium nitride layer is between 3 nm and 150 nm; the thickness of the heavily doped P-type gallium nitride layer is between 5 nm and 30 nm.

[0017] According to an embodiment of the present disclosure, the cross section of each of the above-mentioned grooves is set to be an inverted trapezoid; the etching angle of the bottom of each of the above-mentioned grooves is set to be between 90 degrees and 180 degrees;

[0018] Preferably, the depth of each of the above-mentioned grooves is 0.1 μm to 5 μm; and the etching angle of each of the above-mentioned grooves is 95° to 175°.

[0019] According to an embodiment of the present disclosure, the material constituting the source electrode and the drain electrode is an ohmic contact metal; the material constituting the gate electrode is a Schottky contact metal;

[0020] Preferably, the ohmic contact metal includes at least one of Ti, Al, Ni and Au;

[0021] The Schottky contact metal includes at least one of Pt, Ti, Al, Ni, and TiN.

[0022] According to an embodiment of the present disclosure, the folded channel gallium nitride-based field effect transistor further includes:

[0023] A gate dielectric, the gate dielectric being disposed between the gate and the multi-heterojunction layer; and on the source, the drain, the gallium nitride control layer, the current collapse suppression structure, and the exposed multi-heterojunction layer;

[0024] The gate dielectric includes one of aluminum oxide, aluminum nitride, silicon oxide and silicon nitride.

[0025] According to an embodiment of the present disclosure, the folded channel gallium nitride-based field effect transistor further includes:

[0026] A passivation dielectric layer is formed on the gate dielectric and the exposed multi-heterojunction layer;

[0027] The material of the passivation dielectric layer is at least one of aluminum oxide, aluminum nitride, silicon oxide and silicon nitride.

[0028] According to an embodiment of the present disclosure, an auxiliary trench matching the shape of the trench is formed in the multi-heterojunction layer.

[0029] A second aspect of the present disclosure provides a method for preparing the folded channel gallium nitride-based field effect transistor, comprising:

[0030] forming a nitride buffer layer and a gallium nitride semi-insulating layer on the substrate in a bottom-up order;

[0031] forming a channel region including at least one trench on the upper surface of the gallium nitride semi-insulating layer by an etching process;

[0032] Depositing an alternating material layer comprising barrier layers and channel layers alternately stacked on the surface having the plurality of grooves, and depositing a gallium nitride doped layer on the alternating material layer;

[0033] performing an etching process on the gallium nitride doped layer to expose a portion of the alternating material layer to obtain the gallium nitride regulation layer, wherein the gallium nitride regulation layer extends to at least a portion of the trench on one side of the channel region; the current collapse suppression structure is formed on the other side of the channel region and is separated from the gallium nitride regulation layer by another portion of the trench;

[0034] performing an etching process on the exposed alternating material layer to expose a portion of the gallium nitride semi-insulating layer on both sides of the alternating material layer to obtain the multi-heterojunction layer;

[0035] Depositing a source electrode and a drain electrode on both sides of the multi-heterojunction layer and on the exposed gallium nitride semi-insulating layer respectively;

[0036] A gate groove is formed on the exposed multi-heterojunction layer by etching;

[0037] Depositing a gate dielectric on the source electrode, the drain electrode, the gallium nitride control layer, the current collapse suppression structure, the gate groove and the exposed multi-heterojunction layer;

[0038] Depositing a gate metal on the gate dielectric in the gate trench;

[0039] Depositing a passivation dielectric layer on the exposed GaN semi-insulating layer, gate metal, and gate dielectric, and forming vias on the passivation dielectric layer at locations aligned with the source, gate, GaN control layer, and drain using an etching process; and

[0040] A connection structure electrically connecting the source electrode and the gallium nitride control layer, a gate connection portion electrically connected to the gate electrode, and a drain connection portion electrically connected to the drain electrode are formed in the via holes.

[0041] According to an embodiment of the present disclosure, there is a barrier layer and a channel layer between the bottom of the gate trench and the gallium nitride semi-insulating layer, and the distance between the bottom of the gate trench and the upper surface of the last barrier layer from top to bottom is 0 to 20 nm; or

[0042] The bottom of the gate groove is located in the last barrier layer from top to bottom, and the distance between the bottom of the gate groove and the lower surface of the last barrier layer from top to bottom is 0-5 nm.

[0043] In the folded-channel GaN-based field-effect transistor (FET) of the disclosed embodiment, the upper surface of the GaN semi-insulating layer is structured to have a channel region comprising at least one parallel trench, and the stacked multiple heterojunction layers are combined with the multiple trenches. This allows the alternating stacks of barrier and channel layers in the channel region to be longitudinally folded, thereby increasing the gate-to-drain spacing, enlarging the drift region size within the FET structure, and improving the FET's breakdown voltage.

[0044] Furthermore, by constructing a multi-layer heterostructure with alternating barrier and channel layers, a multi-layer two-dimensional electron gas (2DEG) is created, ensuring parallel current conduction in the field-effect transistor. Because the 2DEG itself has high carrier mobility, and the presence of multiple trenches in the channel region increases the concentration of the 2DEG, the carrier density within the same cross-section also increases accordingly. Consequently, when the field-effect transistor is turned on, it exhibits high conductivity (i.e., a higher on-state current), and this high carrier density reduces on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0046] Figure 1 Schematically shows a cross-sectional view of a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure;

[0047] Figure 2 The flowchart of the method for preparing a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure is schematically shown;

[0048] Figures 3A to 3K Schematically illustrates a cross-sectional view obtained after executing some steps in a method for manufacturing a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure;

[0049] Figure 4 Schematically shows a cross-sectional view of a multi-heterojunction layer of a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure;

[0050] Figure 5 Schematic cross-sectional views of two examples of gate trenches of a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure are schematically shown.

[0051] In the above drawings, the meanings of the corresponding reference numerals are as follows:

[0052] 1: substrate;

[0053] 2: Nitride buffer layer;

[0054] 3: Gallium nitride semi-insulating layer;

[0055] 4: Multiple heterojunction layers;

[0056] 5: GaN control layer;

[0057] 51: lightly doped P-type gallium nitride layer;

[0058] 52: heavily doped P-type gallium nitride layer;

[0059] 6: Current collapse suppression structure;

[0060] 7: Source;

[0061] 8: drain;

[0062] 9: Gate dielectric;

[0063] 10: Gate;

[0064] 11: passivation dielectric layer;

[0065] 12: Connection structure. DETAILED DESCRIPTION

[0066] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0067] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0068] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0069] When expressions such as "at least one of A, B and C, etc." are used, they should generally be interpreted in accordance with the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0070] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0071] Figure 1 A cross-sectional view of a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure is schematically shown.

[0072] like Figure 1As shown, an exemplary embodiment of the present disclosure provides a folded-channel gallium nitride-based field-effect transistor, comprising: a base layer, a multi-heterojunction layer 4, a gallium nitride control layer 5, a current collapse suppression structure 6, a source electrode 7, a drain electrode 8, a gate electrode 10, and a connection structure 12. The base layer comprises a nitride buffer layer 2 and a gallium nitride semi-insulating layer 3, formed sequentially from bottom to top on a substrate 1. A channel region comprising at least one parallel trench is formed on the upper surface of the gallium nitride semi-insulating layer 3. The multi-heterojunction layer 4 comprises channel layers and barrier layers, alternately stacked from bottom to top on the gallium nitride semi-insulating layer 3. Adjacent barrier and channel layers form heterojunctions. From bottom to top, adjacent channel and barrier layers form a group. The gallium nitride control layer 5 extends from one side of the channel region to at least a portion of the trench on the multi-heterojunction layer 4 to control the charge balance within the channel region corresponding to the on and off states of the field-effect transistor. A current collapse suppression structure 6 is formed on the multi-heterojunction layer 4 on the other side of the channel region and is separated from the auxiliary depletion structure / charge neutralization structure by another portion of the trench. The current collapse suppression structure 6 is adapted to provide hole injection when the drain 8 voltage is high, thereby effectively releasing electrons trapped near the drain on the channel surface, suppressing the current collapse effect, and improving the dynamic conduction characteristics of the device. The source 7 and drain 8 contact the sides of the multi-heterojunction layer 4 on the gallium nitride semi-insulating layer 3, respectively. The drain 8 contacts the side surfaces and a portion of the upper surface of the current collapse suppression structure 6. A gate 10 is formed on the multi-heterojunction layer 4 between the source 7 and the gallium nitride control layer 5. A connection structure 12 passes through the top of the gate 10 to electrically connect the source 7 and the gallium nitride control layer 5. This connection structure 12 is adapted to control the field-effect transistor so that the voltage applied to the corresponding gallium nitride control layer 5 is the same as the voltage of the source 7 when the field-effect transistor is in the off state.

[0073] According to the embodiments of the present disclosure, first, the upper surface of the gallium nitride semi-insulating layer 3 is constructed to have a channel region including at least one parallel extending groove, and secondly, the stacked multi-heterojunction layer 4 is combined with the multi-groove technology, so that multiple groups of channel layers and barrier layers are longitudinally folded along the multi-grooves located in the voltage-resistant region between the gate 10 and the drain 8, thereby increasing the distance from the gate 10 to the drain 8, thereby increasing the size of the drift region (i.e., the distance from the gate 10 to the drain 8) in a limited field-effect transistor structure, and improving the breakdown voltage of the field-effect transistor.

[0074] According to the folded channel gallium nitride-based field effect transistor of the embodiment of the present disclosure, the upper surface of the gallium nitride semi-insulating layer 3 is constructed as a channel region including at least one parallel extending groove, and the stacked multi-heterojunction layer 4 is combined with the multi-grooves. In this way, multiple groups of channel layers and barrier layers are longitudinally folded in the channel region, thereby increasing the distance from the gate 10 to the drain 8, increasing the size of the drift region in the field effect transistor structure, and improving the breakdown voltage of the field effect transistor. By constructing the multi-heterojunction layer 4 into multiple groups of channel layers and barrier layers stacked alternately, a multi-layer two-dimensional electron gas is realized, which can ensure the parallel conduction of current in the field effect transistor. Since the two-dimensional electron gas itself has a high carrier mobility, and the presence of multiple grooves in the channel region can also increase the concentration of the two-dimensional electron gas, the carrier density in the same cross section is also increased accordingly. When the field effect transistor is in the on state, it has high conductivity (i.e., has a larger on-current), and the high carrier density reduces the on-resistance.

[0075] According to the folded channel gallium nitride-based field effect transistor of the embodiment of the present disclosure, by introducing the technology of combining multiple trenches with stacked multiple heterojunction layers 4, the size of the field effect transistor is reduced under the same withstand voltage characteristics, thereby improving the integration of the field effect transistor.

[0076] According to an embodiment of the present disclosure, in the multi-heterojunction layer 4, the thickness of each barrier layer is between 1 nm and 50 nm, for example, 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm; the thickness of the channel layer is between 5 nm and 500 nm, for example, 5 nm, 20 nm, 50 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm;

[0077] According to an embodiment of the present disclosure, the material constituting the channel layer is one of AlN, AlGaN, AlInN, and AlInGaN.

[0078] According to the embodiment of the present disclosure, under the influence of piezoelectric polarization, changes in the thickness of each barrier layer and the Al composition in the barrier layer will cause corresponding changes in the concentration of the two-dimensional electron gas formed in the multi-heterojunction layer 4.

[0079] According to an embodiment of the present disclosure, the gallium nitride regulation layer 5 and the current collapse suppression structure 6 both include a lightly doped P-type gallium nitride layer 51 and a heavily doped P-type gallium nitride layer 52 stacked from bottom to top.

[0080] Preferably, the thickness of the lightly doped P-type gallium nitride layer 51 is between 3 nm and 150 nm, for example, 3 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm; the thickness of the heavily doped P-type gallium nitride layer 52 is between 5 nm and 30 nm, for example, 5 nm, 8 nm, 11 nm, 14 nm, 17 nm, 20 nm, 23 nm, 27 nm, or 30 nm.

[0081] According to the embodiments of the present disclosure, the gallium nitride control layer 5 in this scheme utilizes the mutual depletion of carriers between the P-type doped gallium nitride layer and the channel, as well as charge neutralization (therefore, the gallium nitride control layer 5 is also called an auxiliary depletion structure and a charge neutralization structure), thereby uniformizing the electric field in multiple channels, so that the drift region of the field effect transistor forms a large-scale depletion region, thereby further improving the breakdown voltage; the current collapse suppression structure 6 can provide hole injection after high drain voltage stress, thereby effectively releasing electrons trapped near the drain 8 on the channel surface, suppressing the current collapse effect, and improving the dynamic conduction characteristics of the device.

[0082] According to an embodiment of the present disclosure, the cross-section of each trench is set to an inverted trapezoid; the etching angle of the bottom of each trench is set to between 90 degrees and 180 degrees, for example, it can be 95 degrees, 100 degrees, 105 degrees, 110 degrees, 115 degrees, 120 degrees, 125 degrees, 130 degrees, 135 degrees, 140 degrees, 145, 150 degrees, 160 degrees, and 170 degrees. According to an embodiment of the present disclosure, the depth of each trench is 0.1μm to 5μm, for example, 0.1μm, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, and 5μm; the etching angle of each trench is 95° to 175°, more preferably, 120° to 150°, so as to ensure that the two-dimensional electron gas concentration in the multiple trenches is sufficiently large.

[0083] According to an embodiment of the present disclosure, the material constituting the source electrode 7 and the drain electrode 8 is an ohmic contact metal; the material constituting the gate electrode 10 is a Schottky contact metal. In some embodiments, the ohmic contact metal includes at least one of Ti, Al, Ni, and Au, such as Ti / Al, Ti / Al / Ni / Au, Ti / Al / Ti / Au, etc.; the Schottky contact metal includes at least one of Pt, Ti, Al, Ni, and TiN, such as Ni / Au and Ti / Au, etc.

[0084] According to an embodiment of the present disclosure, the folded channel gallium nitride-based field effect transistor further includes: a gate dielectric 9, which is arranged between the gate 10 and the multi-heterojunction layer 4, the source 7, the drain 8, the gallium nitride regulation layer 5, the current collapse suppression structure 6, and the exposed multi-heterojunction layer 4; the gate dielectric 9 includes one of aluminum oxide, aluminum nitride, silicon oxide and silicon nitride.

[0085] According to an embodiment of the present disclosure, the folded channel gallium nitride base further includes a passivation dielectric layer 11 formed on the gate dielectric 9 and the exposed multi-heterojunction layer 4; the material of the passivation dielectric layer 11 is at least one of aluminum oxide, aluminum nitride, silicon oxide and silicon nitride.

[0086] According to an embodiment of the present disclosure, an auxiliary trench matching the shape of the trench is formed in the multi-heterojunction layer 4 .

[0087] According to the embodiments of the present disclosure, the operating principle of the folded channel gallium nitride-based field-effect transistor is as follows: a multi-layer two-dimensional electron gas is generated using a multi-heterojunction layer 4, and by adjusting the drain voltage, a lateral electric field can be generated in the channel region on the upper surface of the gallium nitride semi-insulating layer 3; under the action of the lateral electric field, the multi-layer two-dimensional electron gas is laterally transported along the multi-heterojunction layer 4, forming a drain 8 to output current; the gate voltage is used to regulate the depth of the potential well in the heterojunction, thereby changing the size of the multi-layer two-dimensional electron gas density, thereby controlling the output current through the drain 8 in the multi-channel.

[0088] Specifically, GaN-based field-effect transistors operate in two states: on (conducting) and off (cutoff). Typically, when the gate voltage (when the source 7 is grounded, the voltage between the gate 10 and the source 7 is generally considered the gate voltage) of a GaN-based field-effect transistor is greater than its threshold voltage (turn-on voltage), the GaN-based field-effect transistor is in the on state; when the gate voltage is less than the threshold voltage, the GaN-based field-effect transistor is in the off state. The threshold voltage of a folded-channel GaN-based field-effect transistor is affected by multiple factors, including the thickness of the barrier layer, the gate trench etch depth, and the gate metal composition.

[0089] When the folded channel GaN-based field-effect transistor is in the on state, that is, when the gate voltage is greater than the threshold voltage, as the drain voltage (when the source 7 is grounded, the voltage between the drain 8 and the source 7 is usually regarded as the drain voltage) increases, the multi-layer two-dimensional electron gas in the multi-channel will saturate at a high speed, causing the on-current of the folded channel GaN-based field-effect transistor to first increase and then saturate as the drain voltage increases, presenting an output curve similar to that of a metal-oxide semiconductor field-effect transistor. In addition, compared with traditional single-channel lateral GaN-based field-effect transistors, the multi-channel structure makes the folded channel GaN-based field-effect transistor have a higher on-current, thereby achieving a lower on-resistance.

[0090] When the folded-channel GaN-based field-effect transistor is in the off state (i.e., when the gate voltage is less than the threshold voltage), as the drain voltage increases, the GaN control layer 5 expands from the gate 10 toward the drain 8. The electric field lines generated by the fixed positive charge are concentrated toward the edge of the gate 10, forming a high electric field peak at the edge of the gate 10. After exceeding the critical electric field, the carriers in the space charge region are accelerated by the electric field, ultimately causing the current to increase rapidly and eventually causing the folded-channel GaN-based field-effect transistor to breakdown.

[0091] Figure 2 The flowchart of the method for preparing a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure is schematically shown.

[0092] like Figure 2 As shown, the method for preparing a folded channel GaN-based field effect transistor includes steps S201 to S210. Figures 3A to 3K The cross-sectional view obtained after some steps in the method for preparing a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure are executed is schematically shown.

[0093] In step S201, see Figure 3A A nitride buffer layer 2 and a gallium nitride semi-insulating layer 3 are sequentially formed on a substrate 1 from bottom to top. Specifically, an aluminum nitride nucleation layer, a gallium nitride buffer layer, and a gallium nitride semi-insulating layer 3 formed by carbon-doped gallium nitride (carbon-doped GaN) are sequentially formed on the substrate 1.

[0094] In step S202, see Figure 3B A channel region including at least one trench is formed on the upper surface of the gallium nitride semi-insulating layer 3 by an etching process.

[0095] In step S203, see Figure 3C , depositing alternating material layers including alternating stacks of channel layers and barrier layers on a surface having a plurality of grooves, and then, see Figure 3D , depositing gallium nitride doped layers on the alternating material layers.

[0096] In step S204, see Figure 3E , performing an etching process on the gallium nitride doped layer to expose a portion of the alternating material layer to obtain a gallium nitride regulation layer and a current collapse suppression structure. The gallium nitride regulation layer extends to at least a portion of the trench current collapse suppression structure on one side of the channel region, and is formed on the other side of the channel region and separated from the gallium nitride regulation layer by another portion of the trench.

[0097] In step S205, continue to see Figure 3E , performing an etching process on the exposed alternating material layer to expose a portion of the gallium nitride semi-insulating layer on both sides of the alternating material layer to obtain a multi-heterojunction layer.

[0098] According to the embodiment of the present disclosure, when executing steps S204 to S205, first refer to Figure 3D , depositing a stack of lightly doped P-type gallium nitride (P--GaN) layers and heavily doped P-type gallium nitride (P+-GaN) layers from bottom to top on the alternating material layers; secondly, see Figure 3E , an etching process (mesa isolation etching) is performed on the alternating material layer on the heavily doped P-type gallium nitride layer 52, thereby indirectly implementing an etching process on the alternating material layer, removing part of the lightly doped P-type gallium nitride layer 51 and the heavily doped P-type gallium nitride layer 52, exposing part of the alternating material layer, and obtaining a gallium nitride regulation layer.

[0099] In step S206, see Figure 3F , a source electrode and a drain electrode are respectively deposited on both sides of the multi-heterojunction layer 4 and on the exposed gallium nitride semi-insulating layer.

[0100] In step S207, see Figure 3G , an etching process is used to obtain a gate groove on the exposed multi-heterojunction layer 4.

[0101] In step S208, see Figure 3H , a gate dielectric is deposited on the source, drain, gallium nitride regulation layer, current collapse suppression structure, gate groove and exposed multi-heterojunction layer 4.

[0102] In step S209, see Figure 3I , a gate metal is deposited on the gate dielectric in the gate trench to form a gate 10.

[0103] According to an embodiment of the present invention, in the field effect transistor finally formed, the trench located between the gate 10 (Gate) and the drain 8 (Drain) forms a voltage-resistant region, and a portion of the surface of the multi-heterojunction layer 4 in the voltage-resistant region between the gate 10 and the drain 8 is covered with a gallium nitride regulation layer 5 (auxiliary depletion structure / charge neutralization structure) formed by a lightly doped P-type gallium nitride layer 51.

[0104] According to an embodiment of the present invention, the source 7 and drain 8 form a two-dimensional electron gas (2DEG) channel by side contacting the multi-heterojunction layer 4. The gate 10 can be a metal-insulator-semiconductor (MIS) structure gate formed by etching (n-1) multi-heterojunction layers 4. The gallium nitride regulation layer 5 (the auxiliary depletion structure / charge neutralization structure) is located between the gate 10 and the drain 8.

[0105] In step S210, see Figure 3JA passivation dielectric layer 11 is deposited on the exposed GaN semi-insulating layer 3, gate metal, and gate dielectric 9. A via is formed in the passivation dielectric layer using an etching process at locations aligned with the source 7, gate 10, GaN control layer 5, and drain 8. The gate dielectric 9 grown after the gate 10 trench is etched can be aluminum oxide (Al2O3) or aluminum nitride (AlN). The passivation dielectric layer 11 can be silicon oxide (SiO2), silicon nitride (SiNx), or a combination of the two. The via in the passivation dielectric layer 11 can be formed using F-based or Cl-based plasma etching.

[0106] According to an embodiment of the present invention, the gate dielectric 9 grown after gate trench etching can be aluminum oxide (Al2O3) or aluminum nitride (AlN), and the passivation dielectric layer can be silicon oxide (SiO2) or silicon nitride (SiNx), or a combination thereof. The vias in the passivation dielectric layer 11 can be formed by F-based or Cl-based plasma etching.

[0107] In step S211, see Figure 3K The vias are used to form a connection structure electrically connecting the source electrode to the GaN control layer, a gate connection portion electrically connected to the gate, and a drain connection portion electrically connected to the drain electrode. In this way, the heavily doped P-type GaN layer 52 (P+-GaN) in the GaN control layer 5 is electrically connected to the source electrode 7 via the connection structure 12 across the gate 10.

[0108] Figure 4 A cross-sectional view of multiple heterojunction layers of a folded channel gallium nitride-based field effect transistor according to an embodiment of the present disclosure is schematically shown.

[0109] Figure 5 Two structural diagrams of the gate 10 groove of the folded channel GaN-based field effect transistor according to an embodiment of the present disclosure are schematically shown.

[0110] like Figure 4-Figure 5 As shown, Al(In, Ga)N is used to represent the barrier layer, and GaN is selected as the material of the channel layer for illustration. There is a barrier layer and a channel layer between the bottom of the gate 10 groove and the gallium nitride semi-insulating layer 3, and the distance between the bottom of the gate 10 groove and the upper surface of the last barrier layer is 0 to 20 nm; or, the bottom of the gate 10 groove is located in the last barrier layer from top to bottom, and the distance between the bottom of the gate 10 groove and the lower surface of the last barrier layer from top to bottom is 0 to 5 nm.

[0111] According to the embodiments of the present disclosure, the folded-channel GaN-based field-effect transistor of this solution employs a gate 10 structure designed as a metal-insulator-semiconductor structure, specifically achieved by etching different materials within the multi-heterojunction layer 4. Depending on the etch depth of the gate 10 trench, the regulation of the two-dimensional electron gas within the multi-channel is also different. It is generally believed that a deeper etch depth of the gate 10 trench increases the threshold voltage of the field-effect transistor.

[0112] The folded channel GaN-based field-effect transistor proposed in this scheme simultaneously realizes the advantages of low on-resistance, high breakdown voltage, small size and high integration of GaN-based field-effect transistors, providing a feasible solution for the industrial development of GaN-based field-effect transistors.

[0113] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A folded channel gallium nitride-based field effect transistor, comprising: A base layer, comprising a nitride buffer layer and a gallium nitride semi-insulating layer formed sequentially from bottom to top on a substrate, wherein a channel region including at least one parallel trench is formed on an upper surface of the gallium nitride semi-insulating layer; a multi-heterojunction layer covering the channel region including the trench, including a channel layer and a barrier layer alternately stacked from bottom to top on the gallium nitride semi-insulating layer, wherein a heterojunction is formed between adjacent barrier layers and channel layers; a gallium nitride regulating layer extending from one side of the channel region to at least a portion of the trench on the multi-heterojunction layer to regulate charge balance in the channel region corresponding to the field effect transistor in an on and off state; a current collapse suppression structure formed on the multi-heterojunction layer on the other side of the channel region and separated from the gallium nitride regulation layer by another portion of the trench; wherein the current collapse suppression structure is adapted to provide hole injection to the drain when the drain voltage is high, thereby achieving charge balance on the drain; a source electrode and a drain electrode, respectively contacting two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, wherein the drain electrode contacts a side surface and a portion of an upper surface of the current collapse suppression structure; a gate formed on the multi-heterojunction layer between the source and the gallium nitride regulating layer; a connecting structure, passing through an upper portion of the gate and electrically connecting the source electrode and the gallium nitride regulating layer; The gallium nitride regulation layer and the current collapse suppression structure both include a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top.

2. The field effect transistor according to claim 1, wherein In the multi-heterojunction layer, the thickness of each barrier layer is between 1 nm and 50 nm; the thickness of the channel layer is between 5 nm and 500 nm.

3. The field effect transistor according to claim 1, wherein The barrier layer is made of one of AlN, AlGaN, AlInN and AlInGaN.

4. The field effect transistor according to claim 1, wherein The thickness of the lightly doped P-type gallium nitride layer is between 3 nm and 150 nm; the thickness of the heavily doped P-type gallium nitride layer is between 5 nm and 30 nm.

5. The field effect transistor according to claim 1, wherein The cross section of each of the trenches is set to be an inverted trapezoid; and the etching angle of the bottom of each of the trenches is set to be between 90 degrees and 180 degrees.

6. The field effect transistor according to claim 1, wherein The depth of each groove is 0.1 μm to 5 μm; the etching angle of each groove is 95° to 175°.

7. The field effect transistor according to claim 1, wherein The source and the drain are formed of an ohmic contact metal; the gate is formed of a Schottky contact metal.

8. The field effect transistor according to claim 7, characterized in that The ohmic contact metal includes at least one of Ti, Al, Ni and Au; The Schottky contact metal includes at least one of Pt, Ti, Al, Ni, and TiN.

9. The field effect transistor according to claim 1, further comprising: a gate dielectric, the gate dielectric being disposed between the gate and the multi-heterojunction layer; and on the source electrode, the drain electrode, the gallium nitride regulation layer, the current collapse suppression structure, and the exposed multi-heterojunction layer; Wherein, the gate dielectric includes one of aluminum oxide, aluminum nitride, silicon oxide and silicon nitride.

10. The field effect transistor according to claim 9, further comprising: a passivation dielectric layer formed on the gate dielectric and the exposed multi-heterojunction layer; The material of the passivation dielectric layer is at least one of aluminum oxide, aluminum nitride, silicon oxide and silicon nitride.

11. The field effect transistor according to claim 1, wherein An auxiliary trench matching the shape of the trench is formed in the multi-heterojunction layer.

12. A method for preparing a folded channel gallium nitride-based field effect transistor according to any one of claims 1 to 11, comprising: forming a nitride buffer layer and a gallium nitride semi-insulating layer on the substrate in a bottom-up order; forming a channel region including at least one trench on the upper surface of the gallium nitride semi-insulating layer by an etching process; Depositing an alternating material layer comprising a barrier layer and a channel layer alternately stacked on the surface having the groove, and depositing a gallium nitride doped layer on the alternating material layer; performing an etching process on the gallium nitride doped layer to expose a portion of the alternating material layer, thereby obtaining the gallium nitride regulation layer and the current collapse suppression structure, wherein the gallium nitride regulation layer extends to at least a portion of the trench on one side of the channel region, and the current collapse suppression structure is formed on the other side of the channel region and is separated from the gallium nitride regulation layer by another portion of the trench; performing an etching process on the exposed alternating material layer to expose a portion of the gallium nitride semi-insulating layer on both sides of the alternating material layer to obtain the multi-heterojunction layer; Depositing a source electrode and a drain electrode on both sides of the heterojunction and on the exposed gallium nitride semi-insulating layer respectively; Obtaining a gate groove by etching the exposed multi-heterojunction layer; Depositing a gate dielectric on the source, the drain, the gallium nitride regulation layer, the current collapse suppression structure, the gate groove and the exposed multi-heterojunction layer; depositing a gate metal on the gate dielectric in the gate trench; Depositing a passivation dielectric layer on the exposed GaN semi-insulating layer, gate metal, and gate dielectric, and forming vias on the passivation dielectric layer at locations aligned with the source, gate, GaN control layer, and drain using an etching process; as well as A connection structure electrically connecting the source electrode and the gallium nitride regulation layer, a gate connection portion electrically connected to the gate electrode, and a drain connection portion electrically connected to the drain electrode are respectively formed in the via holes.

13. The preparation method according to claim 12, characterized in that There is a barrier layer and a channel layer between the bottom of the gate groove and the gallium nitride semi-insulating layer, and the distance between the bottom of the gate groove and the upper surface of the last barrier layer from top to bottom is 0-20 nm; or The bottom of the gate groove is located in the last barrier layer from top to bottom, and the distance between the bottom of the gate groove and the lower surface of the last barrier layer from top to bottom is 0-5 nm.

Images