A short-circuit-resistant SJ-LIGBT device with integrated self-biased PMOS

Abstract

The present invention relates to an anti-short-circuit SJ-LIGBT device with integrated self-biased PMOS, and belongs to the field of semiconductor technology. The self-biased PMOS integrated in the device is composed of a P-body region, an N-CS region, a P-shield region, and a PMOS gate oxide layer, wherein the P-shield region serves as a source, the P-body region serves as a drain, and the N-CS region serves as a substrate. The gate and drain of the self-biased PMOS are short-circuited together by a metal electrode to achieve a self-biasing function, and the gate oxide layer is in the same plane as the gate oxide layer of an ordinary NMOS without the need for an additional manufacturing process, which is convenient for integration. The turn-off loss of the present invention is reduced by 24% compared with the traditional SJ-LIGBT device, which greatly improves the compromise relationship between the turn-off loss and the on-state voltage drop of the device; at the same time, the short-circuit resistance of the present invention is excellent, and when the external short-circuit voltage is 150V, the short-circuit working time of the device is 14.8μs.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to an anti-short-circuit SJ-LIGBT device integrating a self-biased PMOS. Background Art

[0002] LIGBT (Lateral Insulated Gate Bipolar Transistor) is a semiconductor power device that combines the voltage-controlled characteristics of MOSFET and the bipolar conduction characteristics of BJT. Due to its advantages such as low forward conduction power consumption, low driving loss and high operating frequency, it is widely used in the fields of communication technology, photovoltaic power generation and emerging automotive consumer electronics, and is a core component in power electronics systems.

[0003] The advantage of the bipolar working mode of LIGBT is that the saturation voltage is reduced when the device is forward-conducted, and its disadvantage is that there is a current tail when the device is turned off, resulting in high device turn-off loss. The reason for the current tail is that the anode P+ region is a high potential barrier for electrons when turned off, and they cannot be directly extracted through the P+ region. The remaining carriers in the device body mainly disappear by the recombination of non-equilibrium carriers. There is a trade-off relationship between turn-off loss and conduction voltage drop. Reducing turn-off loss can be achieved by reducing the injection efficiency of holes during forward conduction, but the conduction voltage drop of the device will also increase.

[0004] In recent years, with the in-depth research on LIGBT devices and the development of various new technologies, the trade-off relationship between the forward conduction voltage drop and turn-off loss of the device can be further optimized. Super-Junction is a technology that can effectively improve the performance of the device. It replaces the traditional N-drift drift region with the cross-distributed N-pillar and P-pillar. When the device withstands the forward voltage, the cross-distributed N-pillar and P-pillar deplete and compensate each other, introducing a transverse electric field inside the device without affecting the longitudinal electric field distribution. Therefore, without sacrificing the voltage withstand capability of the device, the doping concentration of the N-pillar is significantly improved compared to the traditional N-drift, reducing the forward conduction voltage drop of the device.

[0005] As the demand for new energy power generation and new energy vehicles in the consumer market continues to expand, higher requirements are placed on the short-circuit resistance of LIGBT. The nMOS integrated inside the LIGBT has the characteristic of current saturation. Even if a larger bus voltage is applied, the current output by the device will remain in a constant range. This feature allows the device to work in a short-circuit state for a short time without being burned. This buffer time provides the peripheral protection circuit with a fault detection and timely control of the device shutdown, thereby protecting the entire power electronic system. Improving the short-circuit resistance of the device can not only improve the reliability of the power electronic system, but also reduce the design difficulty of the device's peripheral protection circuit and reduce the cost of the entire power electronic system. Therefore, in order to improve the reliability of the device and reduce the design difficulty and cost of the peripheral circuit, it is very necessary to further improve the LIGBT device to improve the short-circuit resistance and lower power consumption. Summary of the invention

[0006] In view of this, the object of the present invention is to provide a short-circuit resistant SJ-LIGBT device with integrated self-biased PMOS, so as to reduce the saturation current under a larger forward conduction voltage of the device, assist in extracting holes when the device is turned off to reduce the turn-off loss, and increase the short-circuit working time when the device is short-circuited.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] A short-circuit-resistant SJ-LIGBT device with integrated self-biased PMOS includes an anode P+ region 1, an anode N-buffer region 2, a buried oxide layer 3, a substrate 4, a drift region N-pillar 5, a drift region P-pillar 6, a P-shield region 7, an N-CS region 8, a P-body region 9, a cathode N+ region 10, a cathode P+ region 11, a PMOS gate oxide layer 12, a PMOS gate metal electrode 13, an NMOS gate oxide layer 14, an NMOS gate metal electrode 15, a cathode metal electrode 16 and an anode metal electrode 17.

[0009] The substrate 4 and the buried oxide layer 3 are stacked from bottom to top, the drift region N-pillar 5 and the drift region P-pillar 6 constitute the drift region arranged above the buried oxide layer 3, the anode P+ region 1, the anode N-buffer region 2 and the anode metal electrode 17 constitute the anode region, the cathode N+ region 10, the cathode P+ region 11 and the cathode metal electrode 16 constitute the cathode region, and the anode region and the cathode region are respectively located on both sides of the drift region. The anode P+ region 1 is wrapped by the anode N-buffer region 2, and the anode metal electrode 17 is arranged on the anode P+ region 1 and is in direct contact with the anode P+ region 1; the cathode N+ region 10 and the cathode P+ region 11 are wrapped by the P-body region 9, and the cathode P+ region 11 is an L-shaped structure, and the cathode N+ region 10 is wrapped by the L-shaped structure.

[0010] The PMOS gate oxide layer 12 and the NMOS gate oxide layer 14 are adjacent to but not connected to the cathode metal electrode 16, the PMOS gate metal electrode 13 is located above the PMOS gate oxide layer 12, and the NMOS gate metal electrode 15 is located above the NMOS gate oxide layer 14; wherein the PMOS gate oxide layer 12 and the NMOS gate oxide layer 14 are located in the same plane, and no additional process is required for manufacturing, and they are easy to integrate.

[0011] The PMOS gate oxide layer 12, the PMOS gate metal electrode 13, the cathode P+ region 11, the P-body region 9, the N-CS region 8, the cathode metal electrode 16 and the P-shield region 7 constitute a self-biased PMOS; the NMOS gate oxide layer 13, the NMOS gate metal electrode 15, the cathode N+ region 10, the P-body region 9, the N-CS region 8, the drift region N-pillar 5 and the cathode metal electrode 16 constitute a normal NMOS.

[0012] Furthermore, the source of the self-biased PMOS is the P-shield region 7 , the drain is the cathode P+ region 11 , and the substrate is the N-CS region 8 .

[0013] Furthermore, the PMOS gate metal electrode 13 is directly connected to the cathode metal electrode 16, and the gate and drain of the self-biased PMOS are short-circuited through the metal electrode, thereby realizing the self-biasing function, and the PMOS can be turned on and off without an external control signal.

[0014] Furthermore, the self-biased PMOS can automatically turn on to reduce the saturation current when the device is turned on, and assist in extracting holes to reduce turn-off loss when the device is turned off.

[0015] Furthermore, when the device operates in the forward blocking state, the P-shield region 7 can shield the high electric field of the N-CS region 8 to improve the withstand voltage.

[0016] Furthermore, the thickness of the PMOS gate oxide layer 12 can be adjusted as needed.

[0017] The beneficial effects of the present invention are as follows: the present invention introduces N-pillar, P-pillar, N-CS region, and P-shield region on the basis of the traditional LIGBT device, thereby integrating a self-biased PMOS. The P-pillar can increase the doping concentration of the drift region and reduce the on-state voltage drop of the device. The N-CS region, as the substrate of the self-biased PMOS, blocks holes when the device is turned on, increases the hole concentration on the cathode side of the device, and thereby reduces the on-state voltage of the device. The self-biased PMOS can automatically start to extract holes in the body when the device is turned on and is under a large external voltage, thereby reducing the saturation current of the device, automatically start to assist in extracting holes in the device body when the device is turned off, thereby reducing the turn-off loss, and automatically start to extract holes in the body when the device is in a short-circuit working state, thereby increasing the short-circuit working time of the device.

[0018] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 It is a schematic structural diagram of the SJ-LIGBT device of the present invention;

[0021] Figure 2 for Figure 1 Equivalent circuit diagram of

[0022] Figure 3 (a) is a schematic diagram of the structure of a traditional LIGBT device, and (b) is a schematic diagram of the structure of a SJ-LIGBT device;

[0023] Figure 4 The present invention, the SJ-LIGBT and the SJ-LIGBT device with an N-CS layer have a drift region length L D Comparison of blocking characteristics at 25μm;

[0024] Figure 5 (a) is a three-dimensional potential distribution diagram of the present invention under forward blocking, and (b) is a three-dimensional potential distribution diagram of the SJ-LIGBT device under forward blocking;

[0025] Figure 6 It is a forward conduction characteristic diagram of the present invention, the traditional LIGBT device and the SJ-LIGBT device;

[0026] Figure 7 The turn-on breakdown characteristic diagram of the present invention, the traditional LIGBT device and the SJ-LIGBT device;

[0027] Figure 8 (a) is a circuit diagram of the short-circuit operation of the test device, and (b) is a short-circuit operation characteristic diagram of the present invention, the conventional LIGBT device and the SJ-LIGBT device;

[0028] Fig. 9 (a) is the inductive load test circuit of the device; (b) is the turn-off characteristic curve of the present invention, the traditional LIGBT and the SJ-LIGBT devices under the same on-state voltage drop;

[0029] Fig.10 Schematic diagram of the main process flow of the SJ-LIGBT device of the present invention.

[0030] Figure markings: 1-anode P+ region; 2-anode N-buffer region; 3-buried oxide layer; 4-substrate; 5-drift region N-pillar; 6-drift region P-pillar; 7-P-shield region; 8-N-CS region; 9-P-body region; 10-cathode N+ region; 11-cathode P+ region; 12-PMOS gate oxide layer; 13-PMOS gate metal electrode; 14-NMOS gate oxide layer; 15-NMOS gate metal electrode; cathode metal electrode 16; 17-anode metal electrode; 18-zipianzhiPMOS; 19-ordinary NMOS. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0032] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0033] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0034] like Figure 1 As shown, an improvement is made on a traditional LIGBT device. This embodiment provides an anti-short-circuit SJ-LIGBT device with integrated self-biased PMOS, which includes an anode P+ region 1, an anode N-buffer region 2, a buried oxide layer 3, a substrate 4, a drift region N-pillar 5, a drift region P-pillar 6, a P-shield region 7, an N-CS region 8, a P-body region 9, a cathode N+ region 10, a cathode P+ region 11, a PMOS gate oxide layer 12, a PMOS gate metal electrode 13, an NMOS gate oxide layer 14, an NMOS gate metal electrode 15, a cathode metal electrode 16, and an anode metal electrode 17;

[0035] In the device, the self-biased PMOS 18 is composed of a cathode P+ region 11, a P-body region 9, an N-CS region 8, a P-shield region 7, a PMOS gate oxide layer 12, a PMOS gate metal electrode 13, and a cathode metal electrode 16. The NMOS 19 is composed of a cathode N+ region 10, a P-body region 9, an N-CS region 8, a drift region N-pillar 5, an NMOS gate oxide layer 14, an NMOS gate metal electrode 15, and a cathode metal electrode 16.

[0036] The length (Y-axis direction) of the drift region N-pillar5 is 25 μm, the width (Z-axis direction) is 2 μm, and the doping concentration of this region is 1×10 16 cm -3 The length of the drift region P-pillar6 is 23 μm, the width is 1 μm, and the doping concentration of this region is 2×10 15 cm -3 The length of the anode P+ region 1 is 1 μm, the width is 2 μm, and the doping concentration is 1×10 19 cm -3 The length of the anode N-buffer region 2 is 2 μm, the width is 2 μm, and the doping concentration is 1×10 17 cm -3The length of the P-shield region 7 is 1 μm, the width is 1.5 μm, and the doping concentration is 1×10 18 cm -3 The length of the N-CS region 8 is 1 μm, the width is 2 μm, and the doping concentration is 1×10 17 cm -3 The length of the P-body region 9 is 3 μm, the width is 2 μm, and the doping concentration is 1×10 17 cm -3 The cathode N+ region 10 has a length of 1 μm, a width of 1 μm, and a doping concentration of 1×10 19 cm -3 The cathode P+ region 11 has a length of 2 μm, a width of 2 μm, and a doping concentration of 1×10 19 cm -3 .

[0037] The working principle of the device is as follows: when the device is forward-conducting and the applied voltage is small, the self-biased PMOS is in the off state, and the holes emitted by the anode P+ are blocked by the N-CS region and accumulated on the cathode side, so that the forward conduction voltage drop is reduced; when the applied voltage is further increased, the self-biased PMOS automatically turns on and extracts holes in the drift region, and the saturation current of the device is reduced. When the device is turned off, the self-biased PMOS automatically turns on as the applied voltage increases, assists in extracting holes in the body, and reduces the turn-off loss of the device. When the device is in a short-circuit working state, the self-biased PMOS automatically turns on to extract holes in the body, thereby reducing the heat accumulation in the device and extending the short-circuit working time of the device.

[0038] Figure 2 The figure shows an equivalent circuit diagram of the SJ-LIGBT device of this embodiment, wherein the ordinary LIGBT is equivalent to a PNP transistor controlled by an NMOS, and the self-biased PMOS and the narrow base PNP transistor equivalent to the P+ / N-pillar / P-pillar are connected in series and in parallel with the ordinary LIGBT.

[0039] Using SENTAURUS simulation software, Figure 1 , Figure 3 (a) and Figure 3 (b) The structure shown in FIG. 1 is subjected to performance simulation analysis, its mechanism is analyzed, and electrical simulation is performed. During the simulation process, the simulation parameters of the embodiment device and the conventional device are consistent, the carrier lifetime is 10 μs, and the ambient temperature is 300K.

[0040] like Figure 4 As shown, the concentration in the drift region of the embodiment is 1×10 16 cm -3 The concentration of N-CS region is 1×10 17 cm -3The breakdown voltage of SJ-IGBT is 273V; the concentration of SJ-IGBT in the drift region is 1×10 16 cm -3 The breakdown voltage is 265V; SJ-LIGBT increases the N-CS region and the concentration is 1×10 17 cm -3 , the drift region concentration is 5×10 15 cm -3 The breakdown voltage is 17V.

[0041] Figure 5 For the example and SJ-IGBT, the drift region length is 25 μm and the concentration is 1×10 16 cm -3 The three-dimensional potential distribution in the blocking state. Figure 5 (a) It can be seen that the voltage of the P-shield region in the blocking state is only 4V, which shields the high electric field of the N-CS region and prevents premature breakdown. Figure 5 (b) It can be seen that the voltage obtained by the SJ-LIGBT at the same distance from the P-shield on the cathode side is 40V.

[0042] Figure 6 and Figure 7 The current density of the embodiment, the conventional LIGBT and the SJ-IGBT is 100A / cm 2 The conduction characteristic curve and turn-on breakdown characteristic curve are shown below. Figure 6 It can be seen that the forward conduction voltage drop of this embodiment is the lowest; Figure 7 It can be seen that the saturation current of this embodiment is the smallest, which is about 53% lower than that of the SJ-LIGBT, and the turn-on breakdown occurs the latest.

[0043] Figure 8 (a) is a circuit diagram of the short-circuit operation of the test device; (b) is a short-circuit operation characteristic diagram of this embodiment, the traditional LIGBT device and the SJ-LIGBT device. It can be seen that when the short-circuit voltage is 150V, the traditional LIGBT and SJ-LIGBT immediately undergo turn-on breakdown and do not have the ability to work in a short circuit; when the short-circuit voltage is 100V, the short-circuit operation time of the traditional LIGBT is 7μs, and the short-circuit operation time of the SJ-LIGBT is 5.5μs; and the short-circuit operation time of the embodiment when the short-circuit voltage is 150V is 14.8μs, and its anti-short-circuit performance is far superior to that of the traditional LIGBT device and the SJ-LIGBT device.

[0044] Fig. 9(a) is the turn-off test circuit of the device under inductive load; (b) is the turn-off characteristic curve of the present embodiment, the conventional LIGBT and the SJ-LIGBT devices under the same on-state voltage drop. It can be seen that the turn-off time of the present embodiment, the conventional LIGBT and the SJ-IGBT devices are 79.5ns, 119ns and 197ns respectively, and the turn-off loss is 0.24mJ, 0.29mJ and 0.33mJ respectively. The present embodiment has the fastest turn-off speed and the smallest turn-off loss.

[0045] The short-circuit-resistant SJ-LIGBT device with integrated self-biased PMOS is Figure 1 Taking the structure shown in the figure as an example, its main process flow is as follows Fig.10 As shown in the figure, the main processes include: ion implantation, diffusion, etching, oxidation, deposition, polycrystalline filling and annealing. Finally, metal electrodes are deposited to form anodes, gates and cathodes.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. An integrated self-biased PMOS short-circuit resistant SJ-LIGBT device, comprising a buried oxide layer (3), a substrate (4), a drift region, an anode region and a cathode region, wherein the substrate (4), the buried oxide layer (3) and the drift region are stacked in sequence from bottom to top, and the anode region and the cathode region are respectively located on both sides of the drift region; characterized in that: The drift region comprises a drift region N-pillar (5) and a drift region P-pillar (6); the anode region comprises an anode P+ region (1), an anode N-buffer region (2) and an anode metal electrode (17), wherein the anode N-buffer region (2) wraps the anode P+ region (1), and the anode metal electrode (17) is arranged on the anode P+ region (1); the cathode region comprises a cathode N+ region (10), a cathode P+ region (11) and a cathode metal electrode (16), wherein the cathode metal electrode (16) is arranged on the cathode P+ region (11); The device further comprises a P-body region (9), an N-CS region (8), a P-shield region (7), a PMOS gate oxide layer (12), a PMOS gate metal electrode (13), an NMOS gate oxide layer (14) and an NMOS gate metal electrode (15); the P-body region (9) encloses a cathode P+ region (11) and a cathode N+ region (10); the N-CS region (8) is adjacent to the P-body region (9), the P-shield region (7) and a drift region N-pillar (5); the P-shield region (7) is also adjacent to the drift region N-pillar (5) and the drift region P-pillar (6); the PMOS gate oxide layer (12) and the NMOS gate oxide layer (14) are adjacent to the cathode metal electrode (16) but not connected to each other; the PMOS gate metal electrode (13) is located above the PMOS gate oxide layer (12), and the NMOS gate metal electrode (15) is located above the NMOS gate oxide layer (14); The PMOS gate oxide layer (12), the PMOS gate metal electrode (13), the cathode P+ region (11), the P-body region (9), the N-CS region (8), the cathode metal electrode (16) and the P-shield region (7) constitute a self-biased PMOS; the NMOS gate oxide layer (14), the NMOS gate metal electrode (15), the cathode N+ region (10), the P-body region (9), the N-CS region (8), the drift region N-pillar (5) and the cathode metal electrode (16) constitute a common NMOS.

2. The SJ-LIGBT device according to claim 1, characterized in that: The source of the self-biased PMOS is a P-shield region (7), the drain is a cathode P+ region (11), and the substrate is an N-CS region (8).

3. The SJ-LIGBT device according to claim 1, characterized in that: The PMOS gate metal electrode (13) is connected to the cathode metal electrode (16).

4. The SJ-LIGBT device according to claim 1, characterized in that: The PMOS gate oxide layer (12) and the NMOS gate oxide layer (14) are located on the same plane, and are easy to integrate.

5. The SJ-LIGBT device according to claim 1, characterized in that: The self-biased PMOS can automatically turn on to reduce the saturation current when the device is turned on, and assist in extracting holes to reduce turn-off loss when the device is turned off.

6. The SJ-LIGBT device according to claim 1, characterized in that: The P-shield region (7) can shield the high electric field of the N-CS region (8) when the device is operating in a forward blocking state, thereby improving the withstand voltage.

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