Vertical field effect transistor based on modulated island structure and manufacturing method thereof

Abstract

The present invention discloses a vertical field-effect transistor based on a modulated island structure and its fabrication method. This device primarily addresses the problem of existing gallium nitride-based power devices lacking good bidirectional conduction characteristics, which leads to increased circuit cost and decreased performance. From bottom to top, the device comprises: a drain, a substrate layer, a drift layer, an N-type GaN channel layer, a top metal layer, and a passivation layer. A first P-type GaN layer and a second P-type GaN layer are positioned on either side of the N-type GaN channel layer. The first P-type GaN layer is evenly divided into n blocks by grooves to form a modulated island structure. Modulated block metal is positioned on the drift layer, the N-type GaN channel layer, and the first P-type GaN layer. A gate and a gate field plate are positioned on the second P-type GaN layer. MESA isolation trenches are positioned around the entire device. This device reduces the reverse conduction turn-on voltage drop and increases the on-current. It also features low leakage current and high withstand voltage during blocking, exhibiting excellent bidirectional conduction characteristics and suitable for use as a power switching device.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to a vertical field effect transistor based on a modulation island structure, which can be used as a basic device of a power electronic system. Technical Background

[0002] At present, environmental pollution and energy shortages have become global issues that restrict the sustainable development of human society. To this end, my country, as a responsible major country, has taken the lead in proposing the strategic goal of "carbon peak and carbon neutrality" internationally, and has implemented positive and effective measures based on this. The research and development of high-performance, low-loss power semiconductor devices to build high-performance, low-loss power switching power supplies is one of the important ways to solve the above problems and help my country achieve the strategic goal of "carbon peak and carbon neutrality". Power semiconductor devices based on GaN wide bandgap semiconductor materials, especially junction field-effect transistors (also a type of vertical field-effect transistor), have very important advantages in realizing high-performance, low-loss power switching power supplies with their advantages such as high breakdown voltage, low on-resistance, and excellent high-temperature characteristics. Therefore, they have broad application prospects in the national economy and military fields.

[0003] The traditional junction vertical field effect transistor is based on a homoepitaxial structure, which includes: a substrate layer 1, a drift layer 2, an N-type GaN channel layer 3, a P-type GaN layer 4, a source 5, a drain 6, and a gate 7; a drift layer 2 is deposited on the substrate layer 1; an N-type GaN channel layer 3 is provided in the middle part of the upper part of the drift layer 2; a P-type GaN layer 4 is deposited on the left and right sides of the N-type GaN channel layer 3 on the upper part of the drift layer 2; a source 5 is deposited on the N-type GaN channel layer 3; a gate 7 is deposited on the upper part of the P-type GaN layer 4 on the left and right sides; a drain 6 is deposited on the lower part of the substrate layer 1, as shown in FIG. Figure 1 shown.

[0004] In most current power switching power supplies, power semiconductor devices must achieve bidirectional conduction characteristics, both forward and reverse conduction. This means that in forward conduction, when a bias voltage greater than the threshold voltage is applied between the gate and source, a conductive channel is formed in the device. A bias voltage greater than the source is applied to the drain, allowing current to flow from the drain to the source. In reverse conduction, when the bias voltage between the gate and source is zero volts or less than the threshold voltage, the device is turned off. A bias voltage less than the source is applied to the drain, allowing current to flow from the source to the drain. However, in traditional junction vertical field-effect transistors, the device can achieve good forward conduction characteristics, with current flowing from the drain to the source. (See GaNVertical-Channel Junction Field-Effect Transistors With Regrown p-GaN by MOCVD, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 67, No. 10, October 2020.) When the bias voltage applied between the gate and source of a traditional junction vertical field-effect transistor is zero volts or less than the threshold voltage, the device is in the off state. Since the device channel is turned off, in order to make the source and drain conductive, that is, the current flows from the source to the drain, it is necessary to overcome a large turn-on voltage drop, which degrades the reverse conduction characteristics and causes large power losses. Therefore, in order to meet the actual needs of power switching power supplies, it is usually necessary to connect a freewheeling diode with a small turn-on voltage drop in parallel to the outside of the traditional junction vertical field-effect transistor to achieve reverse conduction characteristics. This will generate large parasitic inductance and capacitance, which in turn causes the power switching power supply to have problems such as large size, large weight and low efficiency. Therefore, the development of highly integrated vertical field-effect transistors with excellent bidirectional conduction characteristics and blocking characteristics is urgently needed for current high-performance power electronic systems. Summary of the Invention

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and provide a vertical field-effect transistor based on a modulated island structure and a method for manufacturing the same, so as to improve the forward and reverse conduction characteristics, blocking characteristics, power characteristics and reliability of the device, and to enhance the efficiency and performance of the power electronic system in which it is used without increasing the system volume and weight.

[0006] To achieve the above object, the technical solution of the present invention is implemented as follows:

[0007] 1. A vertical field-effect transistor based on a modulated island structure, comprising, from bottom to top, a drain, a substrate layer, a drift layer, and a passivation layer; an N-type GaN channel layer disposed on the drift layer; a first P-type GaN layer and a second P-type GaN layer disposed on either side of the N-type GaN channel layer; a top metal layer disposed on the N-type GaN channel layer; a MESA isolation trench disposed around the N-type GaN channel layer, the first P-type GaN layer, and the second P-type GaN layer; a gate disposed on the second P-type GaN layer; and a gate field plate disposed above the gate and the passivation layer, characterized in that:

[0008] The drift layer, N-type GaN channel layer, and first P-type GaN layer are covered with a modulation block metal, which forms Schottky contacts with the drift layer and the N-type GaN channel layer, respectively. In the off state, a bias voltage greater than that of the drain is applied through the modulation block metal to generate a reverse current flowing from the modulation block metal to the drain, thereby achieving reverse conduction characteristics.

[0009] The top metal and the modulation block metal together constitute the source of the device;

[0010] The first P-type GaN layer is divided into n blocks by n-1 grooves and evenly distributed on the drift layer to form a modulation island structure to expose the drift layer and the N-type GaN channel layer, thereby facilitating the modulation block metal to contact the drift layer and the N-type GaN channel layer respectively, thereby improving the withstand voltage of the device in a blocking state and reducing leakage current, wherein n is a positive integer greater than 1.

[0011] Furthermore, the substrate layer is made of any one of gallium nitride, silicon, diamond or silicon carbide materials.

[0012] Furthermore, the thickness a of the drift layer is 1 μm to 20 μm, the thickness b of the N-type GaN channel layer, the first P-type GaN layer and the second P-type GaN layer are the same and are all 5 nm to 3 μm; the width c of the N-type GaN channel layer is 5 nm to 3 μm.

[0013] Furthermore, the width d of each first P-type GaN layer is 5 nm to 10 μm; and the width d of each groove is 5 nm to 10 μm.

[0014] Furthermore, a distance e between a right edge of the top metal layer and a left edge of the second P-type GaN layer is greater than 0 μm; and a distance f between a left edge of the gate and a left edge of the second P-type GaN layer is greater than 0 μm.

[0015] Furthermore, the gate field plate is arranged above the gate and the passivation layer, and the distance g between the left edge of the gate field plate and the left edge of the second P-type GaN layer is greater than 0 μm; and the gate field plate is separated from the top metal and the modulation block metal by a passivation layer.

[0016] 2. A method for manufacturing a vertical field-effect transistor based on a modulated island structure, comprising:

[0017] A) epitaxially growing GaN-based wide bandgap semiconductor material on the substrate layer to form a drift layer;

[0018] B) forming a mask on the drift layer for the first time, and etching the drift layer using the mask to form an N-type GaN channel layer with a thickness of b and a width of c;

[0019] C) growing a P-type GaN-based wide bandgap semiconductor material on the drift layer around the N-type GaN channel layer using a selective epitaxial process, with an epitaxial height b such that the P-type GaN is flush with the upper surface of the N-type GaN channel layer, thereby forming a first P-type GaN layer and a second P-type GaN layer;

[0020] D) forming a mask on the device surface for the second time, and using the mask to perform deep trench etching on the N-type GaN channel layer, the first P-type GaN layer, and the second P-type GaN layer to the drift layer to form a MESA isolation trench;

[0021] E) forming a mask on the device surface for the third time, and using the mask to etch grooves into the first P-type GaN layer until the drift layer is reached, thereby forming a modulation island structure;

[0022] F) forming a mask on the device surface for the fourth time, using the mask to deposit metal on the N-type GaN channel layer, and performing rapid thermal annealing to complete the formation of the top metal layer, with the distance e between the right edge of the top metal layer and the left edge of the second P-type GaN layer greater than 0 μm, and forming good ohmic contact with the N-type GaN channel layer;

[0023] G) depositing metal at the bottom of the substrate layer and performing rapid thermal annealing to form a good ohmic contact and complete the fabrication of the drain;

[0024] H) forming a mask on the device surface for the fifth time, depositing metal on the second P-type GaN layer using the mask, and performing thermal annealing to complete the formation of the gate, with a distance f between the left edge of the gate and the left edge of the second P-type GaN layer greater than 0 μm;

[0025] 1) forming a mask on the device surface for the sixth time, using the mask to deposit metal on the surfaces of the drift layer, the N-type GaN channel layer, and the first P-type GaN layer, and performing rapid thermal annealing to complete the formation of the modulation block metal, which forms good Schottky contacts with the drift layer and the N-type GaN channel layer respectively;

[0026] J) depositing an insulating dielectric on the surface of the device using a deposition process to form a passivation layer;

[0027] K) forming a mask on the passivation layer for the seventh time, and etching the passivation layer using the mask until the top metal layer, the gate electrode, and the modulation block metal are exposed;

[0028] L) A mask is formed on the device surface for the eighth time, and metal is deposited using the mask to form a gate field plate that covers both the gate and a portion of the passivation layer, with a distance g between the left edge of the gate field plate and the left edge of the second P-type GaN layer greater than 0 μm. Meanwhile, a passivation layer is provided between the gate field plate and the top metal layer and the modulation block metal, thereby completing device fabrication.

[0029] Compared with traditional junction vertical field effect transistors, the device of the present invention has the following advantages:

[0030] First, the forward and reverse conduction characteristics are improved through monolithic integration.

[0031] Due to the use of a modulated island structure, the present invention can expand the conductive channel formed in the N-type GaN channel layer when the device is forward-conducting, that is, when a bias voltage greater than the threshold voltage is applied between the gate and the top metal, and increase the current flowing from the drain to the top metal when a bias voltage greater than the top metal is applied to the drain.

[0032] When a voltage higher than the drain is applied to the modulation block metal, when the device is reverse-conducted, a current flows from the Schottky metal, i.e., the modulation block metal, to the drain. Since the metal-semiconductor contact between the modulation block metal and the drift layer is a Schottky contact, its barrier height can be modulated by the work function of the modulation block metal, and the turn-on voltage drop of the Schottky junction is very low. This junction is turned on first when the device is reverse-conducted, thereby achieving a low turn-on voltage drop during reverse conduction. At the same time, a Schottky contact can be formed on the side wall of the N-type GaN channel layer through the modulation block metal, thereby increasing the reverse conduction current.

[0033] The device of the present invention improves the bidirectional conduction characteristic in a monolithic integration manner, is compatible with the traditional transistor manufacturing process, and has a simple process.

[0034] Second, the leakage current is small and the withstand voltage is high when blocked.

[0035] When the device of the present invention is in a blocking state, the modulation block metal forms a Schottky junction with the drift layer and the N-type GaN channel layer respectively, and the Schottky junction is in a reverse bias state and participates in voltage withstand; the first P-type GaN layer in the modulation island structure forms a PN junction with the drift layer and the N-type GaN channel layer respectively, and the PN junction is in a reverse bias state and its depletion region widens rapidly. The PN junction depletion region is connected to the Schottky junction depletion region, thereby allowing the PN junction and the Schottky junction to participate in voltage withstand at the same time, reducing the reverse bias leakage current of the Schottky junction, achieving high voltage withstand in the reverse blocking state, and enhancing the blocking capability and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a diagram of the structure of a traditional junction vertical field-effect transistor;

[0037] Figure 2 1 is a top view of the vertical field effect transistor based on the modulated island structure of the present invention;

[0038] Figure 3 yes Figure 2 Cross-section along AB direction;

[0039] Figure 4 yes Figure 2 Cross-section along CD direction;

[0040] Figure 5 yes Figure 2 Cross-section along direction EF;

[0041] Figure 6 This is a flowchart of the present invention for fabricating a vertical field effect transistor based on a modulated island structure;

[0042] Figure 7 It is a simulation experiment result diagram of the present invention. DETAILED DESCRIPTION

[0043] The embodiments and effects of the present invention are further described in detail below with reference to the accompanying drawings.

[0044] Reference Figure 2 、 Figure 3 、 Figure 4 and Figure 5 The vertical field-effect transistor based on the modulation island structure given in this example includes: a substrate layer 1, a drift layer 2, an N-type GaN channel layer 3, a first P-type GaN layer 4, a second P-type GaN layer 5, a top metal 6, a drain 7, a gate 8, a modulation block metal 9, a MESA isolation trench 10, a passivation layer 11, a gate field plate 12, and a groove 13, wherein:

[0045] The substrate layer 1 is made of any one of gallium nitride, silicon, diamond, and silicon carbide;

[0046] The drift layer 2 is located on the upper part of the substrate layer 1 and has a doping concentration of 1×10 15 cm -3 ~5×10 17 cm -3 The N-type GaN-based wide bandgap semiconductor material has a thickness a of 1 μm to 20 μm;

[0047] The N-type GaN channel layer 3 is located in the center of the upper part of the drift layer 2 and is made of the same GaN-based wide bandgap semiconductor material as the drift layer 2, with a width c of 5 nm to 3 μm;

[0048] The first P-type GaN layer 4 and the second P-type GaN layer 5 are respectively located on the left and right sides of the N-type GaN channel layer 3, and are formed by a doping concentration of 1×10 17 cm -3 ~1×10 20 cm -3 The P-type GaN-based wide bandgap semiconductor material is composed of a P-type GaN layer; in the AB direction cross section, the width of the first P-type GaN layer 4 and the second P-type GaN layer 5 are both 5nm to 50μm; the thickness b of the N-type GaN channel layer 3, the first P-type GaN layer 4 and the second P-type GaN layer 5 are all 5nm to 3μm;

[0049] The first P-type GaN layer 4 is divided into n pieces by n-1 grooves 13 and evenly distributed on the drift layer 2 to form a modulated island structure. The width of each divided first P-type GaN layer 4 is the same as the width d of each groove 13, that is, d is 5 nm to 10 μm, where n is a positive integer greater than 1.

[0050] The top metal layer 6 is located on the N-type GaN channel layer 3 to form an ohmic contact, and in the AB direction cross section, the distance e between the right edge of the top metal layer 6 and the left edge of the second P-type GaN layer 5 is greater than 0 μm;

[0051] The drain electrode 7 is located at the bottom of the substrate layer 1 to form an ohmic contact;

[0052] The gate 8 is located on the second P-type GaN layer 5 , and in the AB cross section, a distance f between the left edge of the gate 8 and the left edge of the second P-type GaN layer 5 is greater than 0 μm;

[0053] The modulation block metal 9 is located on the surface of the drift layer 2, the N-type GaN channel layer 3 and the first P-type GaN layer 4, and forms Schottky contacts with the drift layer 2 and the N-type GaN channel layer 3 respectively;

[0054] The MESA isolation trench 10 is surrounded by the N-type GaN channel layer 3, the first P-type GaN layer 4 and the second P-type GaN layer 5, and is filled with a passivation layer 11;

[0055] The gate field plate 12 is located above the gate 8 and the passivation layer 11, and in the AB direction cross-section, the distance g between the left edge of the gate field plate and the left edge of the second P-type GaN layer is greater than 0 μm; at the same time, in the CD direction cross-section, the distance h between the edge of the gate field plate 12 and the edge of the passivation layer 11 is greater than 0 μm, that is, the passivation layer 11 is separated from the top metal 6 and the modulation block metal 9 respectively.

[0056] Reference Figure 6 The vertical field effect transistor based on the modulated island structure manufactured by the present invention is given the following three embodiments.

[0057] Example 1: A drift layer 2 is made using a gallium nitride substrate, and the thickness a is 1 μm. The height b of the N-type GaN channel layer 3 is 5 nm, and the width c is 5 nm. The width of each groove 13 and each first P-type GaN layer 4 in the modulation island structure is 5 nm. The number of grooves 13 is 4, and the number of first P-type GaN layers 4 is 5. A vertical field-effect transistor based on a modulation island structure is formed.

[0058] Step 1: epitaxially grow N-type GaN material on the substrate layer 1 to form the drift layer 2.

[0059] Using metal organic chemical vapor deposition technology, under the process conditions of temperature 500℃, pressure 46Torr, hydrogen flow rate 4300sccm, ammonia flow rate 4300sccm, and gallium source flow rate 20μmol / min, an epitaxial layer with a thickness of 1μm and a doping concentration of 1×10 15 cm -3 The drift layer 2 is formed by an N-type GaN semiconductor material.

[0060] Step 2: Etching the drift layer 2 to form an N-type GaN channel layer 3.

[0061] A mask is first made of SiO2 material on the drift layer 2. Reactive ion etching technology is used to etch the drift layer 2 using the mask under process conditions of 100 W power, 15 sccm Cl2 flow rate, and 12 mTorr to form an N-type GaN channel layer 3 with a width of 5 nm and a height of 5 nm. The SiO2 mask pre-made above the N-type GaN channel layer 3 is temporarily retained.

[0062] Step 3. Form a first P-type GaN layer 4 and a second P-type GaN layer 5 by selective epitaxial growth on the drift layer 2 .

[0063] Using metal organic chemical vapor deposition technology, selective epitaxy was performed using the mask retained in the second step. Under the process conditions of temperature of 500°C, pressure of 46 Torr, hydrogen flow rate of 4300 sccm, ammonia flow rate of 4300 sccm, and gallium source flow rate of 20 μmol / min, epitaxial layers with a thickness of 5 nm, a width of 5 nm, and a doping concentration of 1×10 17 cm -3 The P-type GaN semiconductor material is used to form a first P-type GaN layer 4 and a second P-type GaN layer 5 respectively.

[0064] Step 4. Form a MESA isolation trench 10 around the N-type GaN channel layer 3 , the first P-type GaN layer 4 and the second P-type GaN layer 5 .

[0065] A SiO2 mask is formed on the surface of the N-type GaN channel layer 3, the first P-type GaN layer 4 and the second P-type GaN layer 5 for the second time. Reactive ion etching technology is used. Under the process conditions of a power of 150 W, a Cl2 flow rate of 15 sccm and a pressure of 15 mTorr, the N-type GaN channel layer 3, the first P-type GaN layer 4 and the second P-type GaN layer 5 are deep-grooved using the mask until the etching reaches the upper surface of the drift layer 2, thereby forming a MESA isolation trench 10.

[0066] Step 5. Etching the first P-type GaN layer 4 to form a modulation island structure.

[0067] A SiO2 mask is formed for the third time on the surfaces of the N-type GaN channel layer 3, the first P-type GaN layer 4, and the second P-type GaN layer 5. Reactive ion etching technology is used. Under the process conditions of a power of 150 W, a Cl2 flow rate of 15 sccm, and a pressure of 10 mTorr, deep grooves are etched on the first P-type GaN layer 4 using the mask until the etching reaches the upper surface of the drift layer 2. The width of each groove 13 and each first P-type GaN layer 4 is 5 nm, the number of grooves 13 is 4, and the number of first P-type GaN layers 4 is 5, forming a modulated island structure.

[0068] Step 6. Fabricate a top metal layer 6 on the surface of the N-type GaN channel layer 3 .

[0069] The fourth mask is made on the surface of the drift layer 2, the N-type GaN channel layer 3, the first P-type GaN layer 4 and the second P-type GaN layer 5, using electron beam evaporation technology, in a vacuum degree of less than 1.8×10 -3 Pa, voltage is 750W, evaporation rate is less than Under process conditions of , a multilayer metal layer of Ti / Al / Ni / Au is deposited on the surface of the N-type GaN channel layer 3 using a mask. The metal in contact with the N-type GaN channel layer 3 is Ti, with thicknesses of 0.02μm / 0.15μm / 0.05μm / 0.04μm, respectively. Rapid thermal annealing is performed at a temperature of 860°C in an N2 atmosphere to form a good ohmic contact. The distance e between the right edge of the metal and the left edge of the second P-type GaN layer 5 is 2nm, completing the production of the top metal layer 6.

[0070] Step 7. Fabricate a drain electrode 7 at the bottom of the substrate layer 1 .

[0071] Using electron beam evaporation technology, the vacuum degree is less than 1.8×10 -3 Pa, voltage is 500W, evaporation rate is less than Under the process conditions, a multilayer of metal Ti / Al is deposited on the bottom of the substrate layer 1. The metal in contact with the substrate layer 1 is Ti, and the thicknesses thereof are 0.06 μm / 0.12 μm respectively. Rapid thermal annealing is performed at a temperature of 860°C in an N2 atmosphere process condition to form an ohmic contact, thereby completing the production of the drain electrode 7.

[0072] Step 8. Fabricate a gate 8 on the surface of the second P-type GaN layer 5 .

[0073] The fifth mask is made on the surface of drift layer 2, N-type GaN channel layer 3, first P-type GaN layer 4, second P-type GaN layer 5 and top metal 6, using electron beam evaporation technology, in a vacuum degree of less than 1.8×10 -3 Pa, voltage is 750W, evaporation rate is less than Under the process conditions of , a multilayer metal Ni / Au is deposited on the second P-type GaN layer 5 using a mask, i.e., a lower layer of Ni and an upper layer of Au, with thicknesses of 0.05 μm / 0.15 μm respectively. Thermal annealing is performed at a temperature of 860° C. in an N2 atmosphere, with a distance f between the left edge of the metal and the left edge of the second P-type GaN layer 5 being 3 nm, thereby completing the gate 8.

[0074] Step 9. Fabricate a modulation block metal 9 on the surfaces of the drift layer 2 , the N-type GaN channel layer 3 and the first P-type GaN layer 4 .

[0075] The sixth mask is made on the surface of drift layer 2, N-type GaN channel layer 3, first P-type GaN layer 4, second P-type GaN layer 5, top metal 6 and gate 8, using electron beam evaporation technology, in a vacuum of less than 1.8×10 -3 Pa, voltage is 800W, evaporation rate is less than Under the process conditions of , a multilayer metal Ni / Au is deposited on the surface of the drift layer 2, the N-type GaN channel layer 3 and the first P-type GaN layer 4 using a mask, i.e., a lower layer of Ni and an upper layer of Au with thicknesses of 0.05μm / 0.05μm respectively. Rapid thermal annealing is performed at a temperature of 200°C in an N2 atmosphere to form a good Schottky contact, which is electrically connected to the top metal layer 6, completing the production of the modulation block metal 9;

[0076] Step 10: Making a passivation layer 11.

[0077] Using plasma enhanced chemical vapor deposition technology, under process conditions of N2O flow rate of 850 sccm, SiH4 flow rate of 350 sccm, temperature of 300°C, RF power of 25 W, and pressure of 2500 mT, SiN with a thickness of 0.2 μm was deposited on the device surface to form a passivation layer 11;

[0078] Step 11: Etch the passivation layer 11.

[0079] A mask is made on the passivation layer 11 for the seventh time, and reactive ion etching technology is used. Under the process conditions of CF4 flow rate of 20 sccm, O2 flow rate of 5 sccm, pressure of 15 mT, and power of 300 W, the passivation layer 11 is etched using the mask until the top metal 6, gate 8 and modulation block metal 9 are exposed.

[0080] Step 12: Make the gate field plate 12.

[0081] The eighth mask is made on the surface of the top metal 6, gate 8, modulation block metal 9 and passivation layer 11 using electron beam evaporation technology in a vacuum of less than 1.8×10 -3 Pa, voltage is 900W, evaporation rate is less than Under the process conditions, a mask is used to deposit Al metal with a thickness of 0.5 μm to form a gate field plate 12, and the gate field plate 12 is electrically connected to the gate 8 to complete the production of the entire device.

[0082] Example 2: A vertical field-effect transistor based on a modulation island structure is manufactured using a silicon carbide substrate, in which the drift layer 2 has a thickness a of 5 μm, the N-type GaN channel layer 3 has a height b of 1 μm, a width c of 0.8 μm, the width of each groove 13 and each first P-type GaN layer 4 in the modulation island structure is 1 μm, the number of grooves 13 is 9, and the number of first P-type GaN layers 4 is 10.

[0083] Step A: epitaxially grow N-type GaN material on the substrate layer 1 to form the drift layer 2 .

[0084] The process conditions are set to 500℃, 46Torr, 4300sccm of hydrogen, 4300sccm of ammonia, and 25μmol / min of gallium source. Metal organic chemical vapor deposition technology is used to deposit an epitaxial layer with a thickness of 6μm and a doping concentration of 2×10 16 cm -3 The drift layer 2 is formed by an N-type GaN semiconductor material.

[0085] Step B: Etching to form an N-type GaN channel layer 3 on the drift layer 2 .

[0086] A mask is first made of SiO2 material on the drift layer 2. The process conditions are set to 100 W power, 10 sccm Cl2 flow rate, and 15 mTorr pressure. Reactive ion etching technology is used to etch the drift layer 2 using the mask to form an N-type GaN channel layer 3 with a width of 0.8 μm and a height of 1 μm. The SiO2 mask pre-made above the N-type GaN channel layer 3 is temporarily retained.

[0087] Step C: selectively epitaxially forming a first P-type GaN layer 4 and a second P-type GaN layer 5 on the drift layer 2 .

[0088] Selective epitaxy was performed using the mask retained in the second step. The process conditions were set to 500°C, 46 Torr, 4300 sccm of hydrogen, 4300 sccm of ammonia, and 20 μmol / min of gallium source. Metal organic chemical vapor deposition technology was used to deposit epitaxial layers with a thickness of 1 μm, a width of 2 μm, and a doping concentration of 3×10 19 cm -3 The P-type GaN semiconductor material is used to form a first P-type GaN layer 4 and a second P-type GaN layer 5 respectively.

[0089] Step D: fabricating a MESA isolation trench 10 on the surfaces of the N-type GaN channel layer 3 , the first P-type GaN layer 4 and the second P-type GaN layer 5 .

[0090] A second mask is made of SiO2 material on the surface of the N-type GaN channel layer 3, the first P-type GaN layer 4 and the second P-type GaN layer 5. The process conditions are set to 100 W power, 10 sccm Cl2 flow rate and 15 mTorr pressure. Reactive ion etching technology is used to use the mask to perform deep trench etching on the N-type GaN channel layer 3, the first P-type GaN layer 4 and the second P-type GaN layer 5 until the etching reaches the upper surface of the drift layer 2, thereby forming a MESA isolation trench 10.

[0091] Step E. Etching the first P-type GaN layer 4 to form a modulation island structure

[0092] A mask is formed for the third time using SiO2 material on the surfaces of the N-type GaN channel layer 3, the first P-type GaN layer 4, and the second P-type GaN layer 5. The process conditions are set to 100 W power, 15 sccm Cl2 flow rate, and 15 mTorr pressure. Reactive ion etching technology is used to perform deep groove etching on the first P-type GaN layer 4 using the mask until the etching reaches the upper surface of the drift layer 2. The width of each groove 13 and each first P-type GaN layer 4 is 3 μm, the number of grooves 13 is 9, and the number of first P-type GaN layers 4 is 10, forming a modulated island structure.

[0093] Step F: forming a top metal layer 6 on the surface of the N-type GaN channel layer 3 .

[0094] A fourth mask is made on the surface of the drift layer 2, the N-type GaN channel layer 3, the first P-type GaN layer 4 and the second P-type GaN layer 5, and the vacuum degree is set to be less than 1.8×10 -3 Pa, voltage is 750W, evaporation rate is less than Under the process conditions of , electron beam evaporation technology is used to deposit a multilayer of metal Ti / Al / Ti / Au on the surface of the N-type GaN channel layer 3 using a mask. The metal contacting the N-type GaN channel layer 3 is Ti, and the thicknesses are 0.02μm / 0.15μm / 0.15μm / 0.04μm respectively. Rapid thermal annealing is performed under the process conditions of a temperature of 870°C and an N2 atmosphere to form a good ohmic contact. The distance e between the right edge of the metal and the left edge of the second P-type GaN layer 5 is 0.5μm, completing the production of the top metal 6;

[0095] Step G: forming a drain electrode 7 at the bottom of the substrate layer 1 .

[0096] Set the vacuum degree to less than 1.8×10 -3 Pa, voltage is 600W, evaporation rate is less than Under the process conditions of , electron beam evaporation technology is used to deposit multilayer metal Ti / Au on the bottom of the substrate layer 1. The metal in contact with the substrate layer 1 is Ti, and the thicknesses thereof are 0.1μm / 0.15μm respectively. Rapid thermal annealing is performed at a temperature of 870°C in an N2 atmosphere process condition to form an ohmic contact, thereby completing the production of the drain 7;

[0097] Step H: forming a gate 8 on the surface of the second P-type GaN layer 5 .

[0098] The fifth mask is made on the surface of the drift layer 2, the N-type GaN channel layer 3, the first P-type GaN layer 4, the second P-type GaN layer 5 and the top metal 6, and the vacuum degree is set to less than 1.8×10 -3 Pa, voltage is 750W, evaporation rate is less than Under the process conditions of , electron beam evaporation technology is used to deposit a multilayer metal Ni / Au on the second P-type GaN layer 5 using a mask, i.e., a lower layer Ni and an upper layer Au, with thicknesses of 0.02 μm / 0.02 μm respectively. Thermal annealing is performed at a temperature of 870° C. in an N 2 atmosphere, with a distance f between the left edge of the metal and the left edge of the second P-type GaN layer 5 being 0.3 μm, thereby completing the gate 8;

[0099] Step I: fabricate a modulation block metal 9 on the surfaces of the drift layer 2 , the N-type GaN channel layer 3 and the first P-type GaN layer 4 .

[0100] The sixth mask is made on the surface of the drift layer 2, N-type GaN channel layer 3, first P-type GaN layer 4, second P-type GaN layer 5, top metal 6 and gate 8, and the vacuum degree is set to less than 1.8×10 -3 Pa, voltage is 800W, evaporation rate is less than Under the process conditions of , electron beam evaporation technology is used to deposit multiple layers of metal Ni / Au on the surface of the drift layer 2, the N-type GaN channel layer 3 and the first P-type GaN layer 4 using a mask. The lower metal layer is Ni with a thickness of 0.03μm / 0.05μm respectively. Rapid thermal annealing is performed under the process conditions of a temperature of 300°C and an N2 atmosphere to form a good Schottky contact, which is electrically connected to the top metal layer 6, completing the production of the modulation block metal 9;

[0101] Step J: forming a passivation layer 11 .

[0102] Set the vacuum degree to less than 1.2×10 -3 Pa, voltage is 50W, evaporation rate is less than Under the process conditions, electron beam evaporation technology is used to deposit SiO2 with a thickness of 0.2 μm on the surface of the device to form a passivation layer 11;

[0103] Step K: etching the passivation layer 11 .

[0104] A seventh mask is formed on the passivation layer 11. Process conditions are set at a CF4 flow rate of 25 sccm, an O2 flow rate of 3 sccm, a pressure of 20 mT, and a power of 200 W. Reactive ion etching technology is used to etch the passivation layer 11 through the mask until the top metal 6, the gate 8, and the modulation block metal 9 are exposed.

[0105] Step L: Fabricate the gate field plate 12 .

[0106] The eighth mask is made on the surface of the top metal 6, gate 8, modulation block metal 9 and passivation layer 11, and the vacuum degree is set to be less than 1.8×10 -3 Pa, voltage is 850W, evaporation rate is less than Under the process conditions, electron beam evaporation technology is used to deposit Al metal with a thickness of 0.3 μm using the mask to form a gate field plate 12, and the gate field plate 12 is electrically connected to the gate 8 to complete the production of the entire device.

[0107] Example 3: A vertical field-effect transistor based on a modulation island structure is manufactured using a diamond substrate, in which the drift layer 2 has a thickness a of 20 μm, the N-type GaN channel layer 3 has a height b of 3 μm, a width c of 3 μm, the width of each groove 13 and each first P-type GaN layer 4 in the modulation island structure is 10 μm, the number of grooves 13 is 2, and the number of first P-type GaN layers 4 is 3.

[0108] Step 1: epitaxially grow N-type GaN material from bottom to top on substrate layer 1 to form drift layer 2.

[0109] Using metal organic chemical vapor deposition technology, an epitaxial layer with a thickness of 20 μm and a doping concentration of 5×10 17 cm -3 N-type GaN semiconductor material, forming a drift layer 2;

[0110] The process conditions of metal organic chemical vapor deposition are: temperature of 550° C., pressure of 50 Torr, hydrogen flow rate of 4600 sccm, ammonia flow rate of 4600 sccm, and gallium source flow rate of 30 μmol / min.

[0111] Step 2: Etching to form an N-type GaN channel layer 3 on the drift layer 2.

[0112] A mask is first made of SiO2 material on the drift layer 2. Reactive ion etching technology is used to etch the drift layer 2 using the mask to form an N-type GaN channel layer 3 with a width of 3 μm and a height of 3 μm. The SiO2 mask prefabricated above the N-type GaN channel layer 3 is temporarily retained.

[0113] The process conditions of reactive ion etching technology are: power of 100W, Cl2 flow rate of 15sccm, and pressure of 10mTorr.

[0114] Step 3: selectively epitaxially forming a first P-type GaN layer 4 and a second P-type GaN layer 5 on the drift layer 2 .

[0115] Using metal organic chemical vapor deposition technology, selective epitaxy is performed using the mask retained in the second step. On the left and right sides of the N-type GaN channel layer 3 on the drift layer 2, the epitaxial thickness is 3μm, the width is 50μm, and the doping concentration is 1×10 20 cm -3 P-type GaN semiconductor material is used to form a first P-type GaN layer 4 and a second P-type GaN layer 5;

[0116] The process conditions of the metal organic chemical vapor deposition technology are: temperature of 500°C, pressure of 46 Torr, hydrogen flow rate of 4300 sccm, ammonia flow rate of 4300 sccm, and gallium source flow rate of 20 μmol / min.

[0117] Step 4. Fabricate a MESA isolation trench 10 on the surfaces of the N-type GaN channel layer 3 , the first P-type GaN layer 4 and the second P-type GaN layer 5 .

[0118] A second mask of SiO2 material is formed on the surface of the N-type GaN channel layer 3, the first P-type GaN layer 4, and the second P-type GaN layer 5. Reactive ion etching technology is used to perform deep trench etching on the N-type GaN channel layer 3, the first P-type GaN layer 4, and the second P-type GaN layer 5 using the mask until the etching reaches the upper surface of the drift layer 2, thereby forming a MESA isolation trench 10.

[0119] The process conditions of reactive ion etching technology are: power of 100W, Cl2 flow rate of 15sccm, and pressure of 10mTorr.

[0120] Step 5. Etching the first P-type GaN layer 4 to form a modulation island structure

[0121] A third mask is made of SiO2 material on the surfaces of the N-type GaN channel layer 3, the first P-type GaN layer 4, and the second P-type GaN layer 5. Reactive ion etching technology is used to perform deep groove etching on the first P-type GaN layer 4 using the mask until the etching reaches the upper surface of the drift layer 2. The width of each groove 13 and each first P-type GaN layer 4 is 10 μm, the number of grooves 13 is 2, and the number of first P-type GaN layers 4 is 3, forming a modulated island structure;

[0122] The process conditions of reactive ion etching technology are: power 100W, Cl2 flow rate 15sccm, and pressure 10mTorr.

[0123] Step 6. Form a top metal layer 6 on the surface of the N-type GaN channel layer 3 .

[0124] A fourth mask is formed on the surfaces of the drift layer 2, the N-type GaN channel layer 3, the first P-type GaN layer 4, and the second P-type GaN layer 5. Using electron beam evaporation technology, a multilayer of Ti / Al / Mo / Au metal is deposited on the surface of the N-type GaN channel layer 3 using the mask. The metal contacting the N-type GaN channel layer 3 is Ti, with thicknesses of 0.02μm / 0.15μm / 0.05μm / 0.04μm, respectively. Rapid thermal annealing is performed to form a good ohmic contact. The distance e between the right edge of the metal and the left edge of the second P-type GaN layer 5 is 1μm, completing the formation of the top metal layer 6.

[0125] The process conditions of rapid thermal annealing are: temperature 900 °C, N2 atmosphere;

[0126] The process conditions of electron beam evaporation technology are: vacuum degree less than 1.8×10 -3 Pa, voltage is 750W, evaporation rate is less than

[0127] Step 7. Fabricate a drain electrode 7 at the bottom of the substrate layer 1 .

[0128] Using electron beam evaporation technology, a multilayer of metal Ta / Ni / Au is deposited on the bottom of the substrate layer 1. The metal in contact with the substrate layer 1 is Ta, with thicknesses of 0.05μm / 0.1μm / 0.1μm respectively. Rapid thermal annealing is then performed to form an ohmic contact, completing the fabrication of the drain electrode 7.

[0129] The process conditions of rapid thermal annealing are: temperature 900 °C, N2 atmosphere;

[0130] The process conditions of electron beam evaporation technology are: vacuum degree less than 1.8×10 -3 Pa, voltage is 600W, evaporation rate is less than

[0131] Step 8. Fabricate a gate 8 on the surface of the second P-type GaN layer 5 .

[0132] A fifth mask is formed on the surfaces of the drift layer 2, the N-type GaN channel layer 3, the first P-type GaN layer 4, the second P-type GaN layer 5, and the top metal layer 6. Using electron beam evaporation technology, a multilayer Ni / Au metal layer is deposited on the second P-type GaN layer 5 using the mask. The bottom metal layer is Ni, and the thicknesses thereof are 0.05 μm / 0.15 μm, respectively. Rapid thermal annealing is performed, and the distance f between the left edge of the metal layer and the left edge of the second P-type GaN layer 5 is 0.3 μm. This completes the fabrication of the gate 8.

[0133] The process conditions of rapid thermal annealing are: temperature 900 °C, N2 atmosphere;

[0134] The process conditions of electron beam evaporation technology are: vacuum degree is less than 1.8×10 -3 Pa, voltage is 750W, evaporation rate is less than

[0135]

[0136] Step 9. Fabricate a modulation block metal 9 on the surfaces of the drift layer 2 , the N-type GaN channel layer 3 and the first P-type GaN layer 4 .

[0137] A sixth mask is made on the surfaces of the drift layer 2, the N-type GaN channel layer 3, the first P-type GaN layer 4, the second P-type GaN layer 5, the top metal layer 6, and the gate 8. Using electron beam evaporation technology, a multilayer Ni / Au metal layer is deposited on the surfaces of the drift layer 2, the N-type GaN channel layer 3, and the first P-type GaN layer 4 using the mask. The bottom metal layer is Ni with a thickness of 0.01 μm / 0.05 μm, respectively. Rapid thermal annealing is then performed to form a good Schottky contact, which is electrically connected to the top metal layer 6, completing the fabrication of the modulation block metal 9.

[0138] The process conditions of rapid thermal annealing are: temperature 400 °C, N2 atmosphere;

[0139] The process conditions of electron beam evaporation technology are: vacuum degree is less than 1.8×10 -3 Pa, voltage is 500W, evaporation rate is less than

[0140]

[0141] Step 10: Fabricate a passivation layer 11.

[0142] Using atomic layer deposition technology, Al2O3 with a thickness of 0.5 μm is deposited on the surface of the device to form a passivation layer 11;

[0143] The process conditions of atomic layer deposition technology are: TMA and H2O as reaction sources, N2 as carrier gas, carrier gas flow rate of 200sccm, substrate temperature of 300℃, and gas pressure of 700Pa.

[0144] Step 11: Etch the passivation layer 11.

[0145] A mask is formed on the passivation layer 11 for the seventh time, and the passivation layer 11 is etched using the reactive ion etching technique until the top metal layer 6, the gate electrode 8 and the modulation block metal 9 are exposed.

[0146] The process conditions of the reactive ion etching technology are: CF4 flow rate of 45sccm, O2 flow rate of 5sccm, pressure of 15mT, and power of 250W.

[0147] Step 12: Fabricate the gate field plate 12.

[0148] An eighth mask is formed on the surfaces of the top metal 6, gate 8, modulation block metal 9, and passivation layer 11. RF magnetron sputtering technology is used to deposit 1 μm thick Al metal through the mask to form a gate field plate 12. The gate field plate 12 is electrically connected to the gate 8, completing the fabrication of the entire device.

[0149] The process conditions of RF magnetron sputtering technology are: sputtering gas pressure is maintained at 0.15 Pa, Ar flow rate is 8 sccm, substrate temperature is fixed at 200 ° C, and Al target RF power is 200 W.

[0150] The effects of the present invention can be further illustrated by the following simulation results.

[0151] 1. Simulation parameters:

[0152] Assume that the gate voltage is 0V and 2V respectively, and the drain-source voltage increases from -3V to 3V.

[0153] 2. Simulation content

[0154] Under the above simulation parameters, the forward conduction characteristics and reverse conduction characteristics of the vertical field effect transistor based on the modulation island structure of the present invention and the traditional vertical field effect transistor are simulated respectively. The results are as follows: Figure 7 ,in Figure 7 (a) is the bidirectional conduction characteristics of the two devices when the gate voltage is 0V. Figure 7 (b) shows the bidirectional conduction characteristics of the two devices when the gate voltage is 2V.

[0155] Depend on Figure 7 (a) It can be seen that when the gate voltage is 0V and a reverse voltage is applied across the drain and source, the device of the present invention exhibits a lower reverse turn-on voltage of -0.5V compared to the conventional device with a reverse turn-on voltage of -2V; when a forward voltage is applied across the drain and source, both devices are blocked and no current flows.

[0156] Depend on Figure 7 (b) It can be seen that when the gate voltage is 2V and a reverse voltage is applied across the drain and source, the device of the present invention exhibits a larger reverse current than the traditional device, that is, it has better reverse conduction characteristics; when a forward voltage is applied across the drain and source, the device of the present invention has better forward conduction characteristics.

[0157] Simulation results show that the device of the present invention has good bidirectional conduction characteristics and meets the needs of application in power switching circuits.

[0158] The above description is only a specific embodiment of the present invention and does not constitute a limitation of the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, they can make various modifications and changes in form and details according to the method of the present invention without departing from the principles and scope of the present invention. For example, in addition to gallium nitride, diamond and silicon carbide, the substrate can also use silicon, and the number of blocks n of the first P-type GaN layer can be a positive integer greater than 1 in addition to 3, 5, and 10. However, these modifications and changes based on the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A vertical field-effect transistor based on a modulated island structure, comprising, from bottom to top: A drain electrode (7), a substrate layer (1), a drift layer (2) and a passivation layer (11); an N-type GaN channel layer (3) is provided on the drift layer (2); a first P-type GaN layer (4) and a second P-type GaN layer (5) are provided on both sides of the N-type GaN channel layer (3); a top metal (6) is provided on the N-type GaN channel layer (3); a MESA isolation groove (10) is provided around the N-type GaN channel layer (3), the first P-type GaN layer (4) and the second P-type GaN layer (5); a gate (8) is provided on the second P-type GaN layer (5); a gate field plate (12) is provided on the gate (8) and the passivation layer (11); and the characteristics are: The drift layer (2), the N-type GaN channel layer (3) and the first P-type GaN layer (4) are covered with a modulation block metal (9), and the modulation block metal (9) forms Schottky contacts with the drift layer (2) and the N-type GaN channel layer (3), respectively, so that in the off state, a bias voltage greater than the drain (7) is applied by the modulation block metal (9) to generate a reverse current flowing from the modulation block metal (9) to the drain (7), thereby realizing a reverse conduction characteristic; The top metal (6) and the modulation block metal (9) together constitute the source of the device; The first P-type GaN layer (4) is divided into n blocks by n-1 grooves (13), which are evenly distributed on the drift layer (2) to form a modulation island structure, thereby exposing the drift layer (2) and the N-type GaN channel layer (3), facilitating the modulation block metal (9) to contact the drift layer (2) and the N-type GaN channel layer (3), respectively, thereby improving the withstand voltage of the device in a blocking state and reducing leakage current, wherein n is a positive integer greater than 1.

2. The device according to claim 1, characterized in that The substrate layer (1) is made of any one of gallium nitride, silicon, diamond or silicon carbide materials.

3. The device according to claim 1, wherein: The drift layer (2) has a thickness a of 1 μm to 20 μm; The thicknesses b of the N-type GaN channel layer (3), the first P-type GaN layer (4) and the second P-type GaN layer (5) are the same and are all 5 nm to 3 μm; The width c of the N-type GaN channel layer (3) is 5 nm to 3 μm.

4. The device according to claim 1, wherein: The width d of each first P-type GaN layer (4) is 5 nm to 10 μm; The width d of each groove (13) is 5 nm to 10 μm.

5. The device according to claim 1, wherein: The distance e between the right edge of the top metal layer (6) and the left edge of the second P-type GaN layer (5) is greater than 0 μm; A distance f between the left edge of the gate (8) and the left edge of the second P-type GaN layer (5) is greater than 0 μm.

6. The device according to claim 1, wherein: The distance g between the left edge of the gate field plate (12) and the left edge of the second P-type GaN layer (5) is greater than 0 μm, and a passivation layer (11) is provided between the gate field plate (12) and the top metal layer (6) and the modulation block metal (9).

7. A method for manufacturing a vertical field effect transistor based on a modulated island structure, characterized in that: These include: A) epitaxially growing a GaN-based wide bandgap semiconductor material on a substrate layer (1) using an epitaxial process to form a drift layer (2); B) forming a mask on the drift layer (2) for the first time, and etching the drift layer (2) using the mask to form an N-type GaN channel layer (3) with a thickness of b and a width of c; C) on the drift layer (2), surrounding the N-type GaN channel layer (3), epitaxially growing a P-type GaN-based wide bandgap semiconductor material using a selective epitaxial process, with an epitaxial height of b, so that the P-type GaN is flush with the upper surface of the N-type GaN channel layer (3), thereby forming a first P-type GaN layer (4) and a second P-type GaN layer (5); D) making a mask on the device surface for the second time, and using the mask to perform deep trench etching on the N-type GaN channel layer (3), the first P-type GaN layer (4), and the second P-type GaN layer (5) to the drift layer (2), thereby forming a MESA isolation trench (10); E) making a mask on the device surface for the third time, and using the mask to etch a groove (13) in the first P-type GaN layer (4), until the etching reaches the drift layer (2), thereby forming a modulation island structure; F) making a mask on the device surface for the fourth time, using the mask to deposit metal on the N-type GaN channel layer (3), and performing rapid thermal annealing to complete the production of the top metal (6), wherein the distance e between the right edge of the top metal (6) and the left edge of the second P-type GaN layer (5) is greater than 0 μm, and the top metal (6) forms a good ohmic contact with the N-type GaN channel layer (3); G) depositing metal at the bottom of the substrate layer (1) and performing rapid thermal annealing to form a good ohmic contact and complete the production of the drain (7); H) forming a mask on the device surface for the fifth time, depositing metal on the second P-type GaN layer (5) using the mask, and performing thermal annealing to complete the formation of the gate (8), wherein the distance f between the left edge of the gate and the left edge of the second P-type GaN layer (5) is greater than 0 μm; I) making a mask on the device surface for the sixth time, using the mask to deposit metal on the surfaces of the drift layer (2), the N-type GaN channel layer (3) and the first P-type GaN layer (4), and performing rapid thermal annealing to complete the production of the modulation block metal (9), which forms good Schottky contacts with the drift layer (2) and the N-type GaN channel layer (3); J) depositing an insulating dielectric on the surface of the device using a deposition process to form a passivation layer (11); K) forming a mask on the passivation layer (11) for the seventh time, and etching the passivation layer (11) using the mask until the top metal layer (6), the gate (8) and the modulation block metal (9) are exposed; L) A mask is made on the device surface for the eighth time, and metal is deposited using the mask to form a gate field plate (12) that covers both the gate (8) and a portion of the passivation layer (11), and a distance g between the left edge of the gate field plate (12) and the left edge of the second P-type GaN layer (5) is greater than 0 μm; at the same time, a passivation layer (11) is provided between the gate field plate (12) and the top metal layer (6) and the modulation block metal (9), respectively, to complete device fabrication.

8. The method according to claim 7, characterized in that The epitaxial processes include metal organic chemical vapor deposition, atomic layer deposition technology and plasma enhanced chemical vapor deposition technology.

9. The method according to claim 7, characterized in that The metal deposition process includes: electron beam evaporation process and radio frequency magnetron sputtering technology.

Images