LED chip and preparation method thereof

Abstract

This invention provides an LED chip and its fabrication method. By encircling an insulating layer on the electrodes of the LED chip, the lateral metal migration rate between the P / N electrodes can be limited due to the insulating layer's surrounding arrangement on the electrodes, i.e., along the metal migration path between the electrodes. Furthermore, since the thickness of the insulating layer is greater than or equal to the electrode thickness, the lateral metal migration direction between the P / N electrodes can be limited, ultimately improving the electrode detachment situation. Specifically, the insulating layer includes a first insulator layer and a second insulator layer that work together. The first insulator layer, with its lower refractive index, reduces the number of Si-N bonds, improving high reverse voltage resistance, while the second insulator layer, with its higher refractive index, increases density and prevents moisture ingress, thereby further improving the electrode detachment situation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to an LED chip and its fabrication method. Background Technology

[0002] LEDs (Light-Emitting Diodes) are solid-state active light sources with advantages such as energy saving and environmental protection, high efficiency, long lifespan, high brightness, high color purity, low energy consumption, and fast response time. They can typically achieve higher durability, more compact size, and greater design flexibility, and are widely used in lighting, display, backlighting, automotive, and other fields.

[0003] Currently, common electrode metal materials for LED chips include Ni, Gr, Al, Ti, Pt, and Au. When an external electric field is applied and water vapor or halogens are introduced, the metal elements can be electrolyzed to form ions when water vapor penetrates the chip surface. If a forward voltage is applied, the metal ions electrolyzed from the P electrode will migrate along the direction of the electric field; if a reverse voltage is applied, the metal ions electrolyzed from the N electrode will migrate along the direction of the electric field. Furthermore, in the presence of halogen electrons within the package, halogen electrons readily combine with metal ions, accelerating metal migration and causing abnormal metal migration at the electrodes.

[0004] Understandably, if an LED chip operates for a long time in an environment of heat accumulation, moisture infiltration, and high frequency and high refresh rate, metal migration can easily occur in the electrodes, affecting the adhesion of the metal electrodes and ultimately causing the electrodes to detach. Summary of the Invention

[0005] Based on this, the present invention provides an LED chip and its preparation method, aiming to improve the problem of electrode detachment when LED chips operate for a long time in environments with heat accumulation, moisture infiltration, and high frequency and high refresh rate.

[0006] According to an embodiment of the present invention, an LED chip includes electrodes and an insulating layer surrounding the electrodes. The insulating layer includes a first insulator layer and a second insulator layer that cooperate with each other. The thickness of the insulating layer is greater than or equal to the thickness of the electrodes, wherein the refractive index of the first insulator layer is less than the refractive index of the second insulator layer.

[0007] Furthermore, the second insulator layer is deposited on top of the first insulator layer, and the first insulator layer and the second insulator layer have the same shape and size.

[0008] Furthermore, the first insulator layer and the second insulator layer are sequentially arranged around the electrode, and the distance between the first insulator layer and the electrode is the same as the distance between the first insulator layer and the second insulator layer.

[0009] Furthermore, the refractive index of the first insulator layer is 1.4 to 1.5, and the refractive index of the second insulator layer is 1.45 to 1.55.

[0010] Furthermore, the LED chip also includes a substrate, on which an N-type GaN layer, an active layer, a P-type GaN layer, a transparent conductive layer, a passivation layer, and pads are sequentially deposited. The electrodes include P-type electrodes and N-type electrodes. The P-type electrodes are disposed on the P-type GaN layer, and the N-type electrodes are disposed on the N-type GaN layer. The pads and the passivation layer are sequentially deposited on the electrodes and the insulating layer.

[0011] Furthermore, the thickness of both the electrode and the pad is 1μm to 3μm.

[0012] Furthermore, both the electrode and the pad are structures with multiple stacked metal layers, wherein the metal layers are one or more combinations of Cr, Al, Ti, Ni, Pt, Au, and Cu.

[0013] Furthermore, a through-hole is formed on the transparent conductive layer, and the P-type electrode and the insulating layer corresponding to the P-type electrode are in contact with the P-type GaN layer through the through-hole.

[0014] According to an embodiment of the present invention, a method for preparing an LED chip is used to prepare the aforementioned LED chip, the method comprising:

[0015] Electrodes were prepared using electron beam evaporation.

[0016] An insulating layer is deposited on the electrode using a PECVD device, and then subjected to photolithography, etching, and etching processes to obtain an insulating layer surrounding the electrode, wherein the thickness of the insulating layer is greater than or equal to the thickness of the electrode.

[0017] Furthermore, the deposition temperature of the insulating layer is 230°C to 250°C.

[0018] Compared with existing technologies: By encircling the electrodes of the LED chip with an insulating layer, the lateral metal migration rate between the P / N electrodes in the LED chip can be limited because the insulating layer is surrounded on the electrodes, i.e., along the metal migration path between the electrodes. Furthermore, since the thickness of the insulating layer is greater than or equal to the electrode thickness, the lateral metal migration direction between the P / N electrodes in the LED chip can be limited, ultimately improving the electrode detachment situation. Specifically, because the insulating layer includes a first insulator layer and a second insulator layer that work together, the first insulator layer with a lower refractive index can reduce the number of Si-N bonds and improve the high reverse voltage resistance performance, while the second insulator layer with a higher refractive index can improve the compactness and prevent moisture from entering, thereby further improving the electrode detachment situation. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the LED chip structure in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the structure of an LED chip according to another embodiment of the present invention;

[0021] Figure 3 This is a flowchart illustrating the implementation of an LED chip manufacturing method according to an embodiment of the present invention. Detailed Implementation

[0022] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0023] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an LED chip in an embodiment of the present invention. The LED chip includes a substrate 1, and N-type GaN layer 2, active layer 3, P-type GaN layer 4, transparent conductive layer 5, electrodes, an insulating layer surrounding the electrodes, a passivation layer 9, and pads, which are sequentially deposited on the substrate 1. The electrodes include P-type electrode 61 and N-type electrode 62. P-type electrode 61 is disposed on P-type GaN layer 4, and N-type electrode 62 is disposed on N-type GaN layer 2. Pads and passivation layer 9 are sequentially deposited on the electrodes and the insulating layer.

[0026] In this embodiment, the substrate 1 can be a GaN substrate 1, and the thickness of the N-type GaN layer 2 is 1μm to 3μm. For example, the thickness of the N-type doped GaN layer 41 is 1.1μm, 1.2μm, 2μm, or 2.4μm, but is not limited thereto. The active layer 3 is formed by periodically alternating quantum well layers and quantum barrier layers, with a growth cycle number of 5 to 12. Specifically, the quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer. The thickness of a single quantum well layer is 1nm to 4nm. For example, the thickness of the quantum well layer is 1.5nm, 2nm, 2.5nm, 3nm, or 3.5nm, but is not limited thereto. The thickness of a single quantum barrier layer is 8nm to 20nm. For example, the thickness of a single quantum barrier layer is 9nm. The thickness of the P-type GaN layer 4 is 10nm, 12nm, 14nm, or 16nm, but is not limited to these; the thickness of the P-type GaN layer 4 is 30nm to 200nm. For example, the thickness of the P-type GaN layer 4 is 40nm, 60nm, 80nm, 100nm, or 150nm, but is not limited to these; the transparent conductive layer 5 is a material with high transparency, high conductivity, and low contact resistance. The transparent conductive layer 5 can be selected from indium tin oxide (ITO), zinc oxide (ZnO), cadmium tin oxide (CTO), indium oxide (InO), indium (In)-doped zinc oxide (ZnO), aluminum (Al)-doped zinc oxide (ZnO), gallium (Ga)-doped zinc oxide (ZnO), or any combination thereof. In this embodiment, indium tin oxide (ITO) is preferred. The thickness of the transparent conductive layer 5 is... For example, the thickness of the transparent conductive layer 5 is However, this is not limited to the above; both the P-type electrode 61 and the N-type electrode 62 are structures with multiple stacked metal layers, wherein the metal layers can be one or more of Cr, Al, Ti, Ni, Pt, Au, and Cu, and the thickness of the P-type electrode 61 and the N-type electrode 62 is 1 μm to 3 μm. For example, the thickness of the P-type electrode 61 and the N-type electrode 62 is 1 μm, 1.2 μm, 1.6 μm, 2.2 μm, or 2.6 μm, but is not limited to these. The material of the insulating layer is one or more of silicon dioxide, silicon nitride, and aluminum oxide. For example, it can be a single silicon dioxide layer, a single silicon nitride layer, or a single aluminum oxide layer. The insulating layer can also be a mixed layer of silicon dioxide and silicon nitride, a mixed layer of silicon nitride and aluminum oxide, a mixed layer of silicon dioxide and aluminum oxide, or a mixed layer of silicon dioxide, silicon nitride, and aluminum oxide. The thickness of the insulating layer is 1 μm to 3 μm. For example, the thickness of the insulating layer is 1 μm, 1.2 μm, 1.6 μm, 2.2 μm, or 2.6 μm, but is not limited thereto. The width of the insulating layer is 1 μm to 5 μm. It should be noted that the width of the insulating layer specifically refers to the difference between the outer diameter and the inner diameter of the annular insulating layer. For example, the width of the insulating layer is 1 μm, 1.5 μm, 2.2 μm, 3 μm, or 5 μm, but is not limited thereto.

[0027] Furthermore, the thickness of passivation layer 9 is For example, the thickness of passivation layer 9 is However, it is not limited to this; the pad is a structure of multiple stacked metal layers, wherein the metal layers can be one or more of Cr, Al, Ti, Ni, Pt, Au, and Cu.

[0028] It should be noted that the thickness of the insulating layer is greater than or equal to the thickness of the electrode. In this embodiment, the second insulator layer is deposited on top of the first insulator layer, and the shape and size of the first and second insulator layers are the same. This means that the sum of the thicknesses of the first and second insulator layers is greater than or equal to the thickness of the electrode. The arrangement of the first and second insulator layers can restrict the lateral metal migration direction between the P / N electrodes in the LED chip. Furthermore, since the insulating layer is arranged around the electrodes, i.e., along the metal migration path between the electrodes, it can restrict the lateral metal migration rate between the P / N electrodes in the LED chip. Specifically, the first and second insulator layers are provided at both the P-type electrode 61 and the N-type electrode 62, and the second insulator layer is deposited on top of the first insulator layer. The first and second insulator layers have the same width, ranging from 1 μm to 5 μm. Furthermore, the refractive index of the first insulator layer is lower than that of the second insulator layer. Specifically, the refractive index of the first insulator layer is 1.4 to 1.5, and the refractive index of the second insulator layer is 1.45 to 1.55. The lower refractive index of the first insulator layer reduces the number of Si-N bonds, improving high-voltage resistance. The higher refractive index of the second insulator layer increases density, preventing the increase of voids in the insulation layer itself and thus preventing moisture ingress. For example, the refractive index of the first insulator layer is 1.4, 1.42, 1.45, 1.47, or 1.5, but is not limited to these. Similarly, the refractive index of the second insulator layer is 1.45, 1.47, 1.5, 1.52, or 1.55, but is not limited to these.

[0029] Through holes are formed on the transparent conductive layer 5. The P-type electrode 61 and the first insulator layer corresponding to the P-type electrode 61 are in contact with the P-type GaN layer 4 through the through holes. In addition, by etching the epitaxial layer, i.e. etching from the P-type GaN layer 4 toward the substrate 1, the N-type GaN layer 2 is exposed. Then, the N-type electrode 62 and the first insulator layer corresponding to the N-type electrode 62 are placed on the exposed N-type GaN layer 2. On this basis, the pads and passivation layer 9 are further prepared.

[0030] In this process, corresponding pads are deposited on both the P-type electrode 61 and the N-type electrode 62. Specifically, P-type pad 81 is deposited on the P-type electrode 61 and N-type pad 82 is deposited on the N-type electrode 62. After the passivation layer 9 is prepared, through holes are opened at the positions of the pads in the passivation layer 9 to expose the pads.

[0031] Please see Figure 2 , Figure 2This is a schematic diagram of an LED chip structure according to another embodiment of the present invention. The difference from the LED chip described above is that a first insulator layer and a second insulator layer are sequentially arranged around the electrode, and the distance between the first insulator layer and the electrode is the same as the distance between the first insulator layer and the second insulator layer. This arrangement makes the structure more stable and effectively prevents moisture from entering. It should be noted that the widths of the first and second insulator layers are the same, ranging from 1 μm to 5 μm.

[0032] Accordingly, refer to Figure 3 This invention also provides a method for manufacturing an LED chip, which is used to prepare the above-mentioned LED chip, specifically including the following steps:

[0033] S100: Provides a substrate;

[0034] Preferably, the selected substrate can be a GaN substrate.

[0035] S200: An N-type GaN layer, an active layer, and a P-type GaN layer are sequentially deposited on the substrate along the epitaxial growth direction;

[0036] Specifically, S200 includes:

[0037] S210: An N-type GaN layer is grown on the substrate;

[0038] Specifically, the growth process of N-type GaN layers in MOCVD equipment is as follows: the temperature of the reaction chamber of MOCVD equipment is adjusted to 1000℃~1100℃, the pressure is controlled at 100 torr~300 torr, and the thickness of the deposited N-type GaN layer is controlled at 1μm~3μm.

[0039] S220: An active layer is grown on an N-type GaN layer;

[0040] Specifically, an active layer is grown in an MOCVD device, wherein the active layer is formed by periodically alternating growth of a quantum well layer and a quantum barrier layer, and the number of growth cycles is 5 to 12. In one embodiment of the present invention, the number of cycles can be 5, that is, the active layer is obtained by alternating growth of a quantum well layer and a quantum barrier layer 5 times;

[0041] Furthermore, the temperature of the MOCVD equipment reaction chamber during the growth of the quantum well layer is controlled at 750℃~850℃, the pressure is controlled at 50 torr~200 torr, the thickness of the deposited monolayer InGaN quantum well layer is controlled at 1nm~4nm, and the In composition is 0.1~0.5.

[0042] Furthermore, the temperature of the MOCVD equipment reaction chamber during the growth of the quantum barrier layer is controlled at 850℃~950℃, the pressure is controlled at 50 torr~200 torr, and the thickness of the deposited monolayer GaN quantum barrier layer is controlled at 8nm~20nm.

[0043] S230: A P-type GaN layer is grown on the active layer;

[0044] Specifically, a p-type GaN layer is grown in an MOCVD device using Mg as a dopant, wherein the Mg concentration is controlled to be 10. 19 cm -3 ~10 20 cm -3 The specific growth process is as follows: the temperature of the reaction chamber of the MOCVD equipment is controlled at 900℃~1050℃, the pressure is controlled at 100torr~600torr, TMGa is introduced as Ga source, and the thickness of the deposited P-type GaN layer is controlled at 30nm~200nm.

[0045] S300: Etching of the epitaxial layer, wherein etching is performed from the P-type GaN layer toward the substrate to expose the N-type GaN layer;

[0046] Specifically, ICP (Inductively Coupled Plasma) technology is used to etch the epitaxial layer. The etching proceeds from the P-type GaN layer toward the substrate, exposing the N-type GaN layer. After the N-type GaN layer is exposed, the etching continues to the N-type GaN layer, with an etching depth of 1 μm to 1.5 μm.

[0047] S400: A transparent conductive layer is deposited on a P-type GaN layer;

[0048] Specifically, a transparent conductive layer can be prepared using sputtering or electron beam evaporation processes, and the thickness of the deposited transparent conductive layer can be controlled to be... Preferably, the transparent conductive layer is an ITO transparent conductive layer. After the transparent conductive layer is deposited, through-holes are formed in a predetermined area of ​​the transparent conductive layer by etching or etching processes, so as to expose part of the P-type GaN layer.

[0049] S500: A P-type electrode is fabricated at the via of the transparent conductive layer, that is, on the P-type GaN layer exposed through the via, and an N-type electrode is fabricated on the exposed N-type GaN layer.

[0050] Specifically, the P-type electrode can also be called the P-type contact electrode, and the N-type electrode can also be called the N-type contact electrode. The P-type electrode and the N-type electrode are prepared by electron beam evaporation, and the thickness of the P-type electrode and the N-type electrode is controlled to be 1μm to 3μm.

[0051] S600: Insulating layers are prepared at the P-type electrode and the N-type electrode, respectively;

[0052] Specifically, using PECVD (Plasma Enhanced Chemical Vapor Deposition) equipment, an insulating material is deposited on a P-type electrode, an N-type electrode, a transparent conductive layer, and an N-type GaN layer. The insulating material is one or a combination of silicon dioxide, silicon nitride, and aluminum oxide. Then, photolithography and etching processes are sequentially used to form a first insulator layer and a second insulator layer surrounding the P-type electrode and the N-type electrode, respectively. It should be noted that the deposition temperature is controlled at 230℃~250℃, the total thickness of the first and second insulator layers is controlled at 1μm~3μm, and the width of the first and second insulator layers is controlled at 1μm~5μm. It should also be noted that the thickness of the insulating layer composed of the first and second insulator layers is greater than or equal to the thickness of the electrode. That is, when the thickness of the P-type electrode is 2μm, the corresponding thickness of the insulating layer composed of the first and second insulator layers should be 2μm~3μm.

[0053] S700: P-type pads are prepared on P-type electrodes and the insulating layer corresponding to P-type electrodes, and N-type pads are prepared on N-type electrodes and the insulating layer corresponding to N-type electrodes.

[0054] Specifically, both P-type and N-type pads are prepared by electron beam evaporation, with the thickness of the P-type and N-type pads controlled to be 1μm to 3μm. Specifically, P-type pads are fabricated on the surface of the P-type electrode and the corresponding insulating layer, completely covering the P-type electrode and the annular insulating layer, and are electrically connected to the P-type electrode. At the same time, N-type pads are fabricated on the surface of the N-type electrode and the corresponding insulating layer, completely covering the N-type electrode and the annular insulating layer, and are electrically connected to the N-type electrode.

[0055] S800: A passivation layer is prepared on a transparent conductive layer, an electrode, an insulating layer, and an N-type GaN layer;

[0056] Specifically, the deposition thickness using PECVD equipment is [missing information]. The passivation layer is deposited at a temperature of 230℃ to 250℃. It should be noted that after the passivation layer is deposited, the passivation layer above the P-type pads and N-type pads is opened by photolithography and etching processes to expose the P-type pads and N-type pads.

[0057] The present invention will be further described below with reference to specific embodiments:

[0058] Example 1

[0059] This embodiment provides an LED chip, including a substrate, and an N-type GaN layer, an active layer, a P-type GaN layer, a transparent conductive layer, electrodes, an insulating layer, a passivation layer, and pads sequentially deposited on the substrate. The electrodes include P-type electrodes and N-type electrodes. The P-type electrodes are disposed on the P-type GaN layer, and the N-type electrodes are disposed on the N-type GaN layer. The pads and the passivation layer are sequentially deposited on the electrodes and the insulating layer.

[0060] The substrate is a GaN substrate, specifically, the N-type GaN layer has a thickness of 2 μm; the active layer is formed by periodically alternating quantum well layers and quantum barrier layers, with a growth cycle of 8; specifically, the quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer, with a single quantum well layer thickness of 2 nm and a single quantum barrier layer thickness of 10 nm; the P-type GaN layer has a thickness of 100 nm; the transparent conductive layer is an ITO transparent conductive layer with a thickness of [missing information]. Both the P-type and N-type electrodes have a structure consisting of multiple stacked metal layers. These metal layers can be one or more combinations of Cr, Al, Ti, Ni, Pt, Au, and Cu. The thickness of both the P-type and N-type electrodes is 1.5 μm. The insulating layer has a thickness of 2 μm and a width of 3 μm. The passivation layer has a thickness of [missing information]. The pad is a structure of multiple stacked metal layers, wherein the metal layers can be one or more of Cr, Al, Ti, Ni, Pt, Au, and Cu.

[0061] The method for preparing the LED chip in this embodiment includes the following steps:

[0062] (1) Provide a GaN substrate;

[0063] (2) An N-type GaN layer is grown on a GaN substrate;

[0064] Specifically, the growth process of N-type GaN layers in MOCVD equipment is as follows: the temperature of the reaction chamber of MOCVD equipment is adjusted to 1050℃, the pressure is controlled at 200 torr, and the thickness of the deposited N-type GaN layer is controlled to be 2μm.

[0065] (3) An active layer is grown on the N-type GaN layer;

[0066] Specifically, an active layer is grown in an MOCVD device, wherein the active layer is formed by the periodic alternation of quantum well layers and quantum barrier layers, and the number of growth cycles is 8.

[0067] Furthermore, the temperature of the MOCVD equipment reaction chamber was controlled at 800℃ and the pressure at 100 torr during the growth of the quantum well layer. The thickness of the deposited monolayer InGaN quantum well layer was controlled at 2nm and the In composition was 0.2%.

[0068] Furthermore, the temperature of the MOCVD equipment reaction chamber was controlled at 900°C and the pressure at 100 torr during the growth of the quantum barrier layer, and the thickness of the deposited monolayer GaN quantum barrier layer was controlled at 10 nm.

[0069] (4) Grow a P-type GaN layer on the active layer;

[0070] Specifically, a p-type GaN layer is grown in an MOCVD device using Mg as a dopant, wherein the Mg concentration is controlled to be 10. 19 cm -3 The specific growth process is as follows: the temperature of the reaction chamber of the MOCVD equipment is controlled at 950℃, the pressure is controlled at 200 torr, TMGa is introduced as the Ga source, and the thickness of the deposited P-type GaN layer is controlled at 100nm.

[0071] (5) Etching the epitaxial layer, wherein etching is performed from the P-type GaN layer toward the substrate to expose the N-type GaN layer;

[0072] Specifically, ICP (Inductively Coupled Plasma) technology is used to etch the epitaxial layer. The etching proceeds from the P-type GaN layer toward the substrate, exposing the N-type GaN layer. Once the N-type GaN layer is exposed, the etching continues to the N-type GaN layer, with an etching depth of 1 μm.

[0073] (6) Deposit a transparent conductive layer on the P-type GaN layer;

[0074] Specifically, a transparent conductive layer can be prepared using sputtering or electron beam evaporation processes, and the thickness of the deposited transparent conductive layer can be controlled to be... Preferably, the transparent conductive layer is an ITO transparent conductive layer. After the transparent conductive layer is deposited, through-holes are formed in a predetermined area of ​​the transparent conductive layer by etching or etching processes, so as to expose part of the P-type GaN layer.

[0075] (7) At the via of the transparent conductive layer, i.e. on the P-type GaN layer exposed through the via, a P-type electrode is prepared, and at the same time, an N-type electrode is prepared on the bare N-type GaN layer.

[0076] Specifically, the P-type electrode can also be called the P-type contact electrode, and the N-type electrode can also be called the N-type contact electrode. The P-type electrode and the N-type electrode are prepared by electron beam evaporation, and the thickness of the P-type electrode and the N-type electrode is controlled to be 1.5 μm.

[0077] (8) Prepare insulating layers at the P-type electrode and the N-type electrode respectively;

[0078] Specifically, using PECVD (Plasma Enhanced Chemical Vapor Deposition) equipment, an insulating material is deposited on the P-type electrode, N-type electrode, transparent conductive layer, and N-type GaN layer. The insulating material is one or a combination of silicon dioxide, silicon nitride, and aluminum oxide. Then, photolithography and etching processes are sequentially used to form the insulating layer surrounding the P-type electrode and the insulating layer surrounding the N-type electrode, respectively. It should be noted that the deposition temperature is controlled at 240℃, the thickness of the insulating layer is controlled at 2μm, and the width of the insulating layer is controlled at 1μm.

[0079] (9) Prepare P-type pads on P-type electrodes and the insulating layer corresponding to P-type electrodes, and prepare N-type pads on N-type electrodes and the insulating layer corresponding to N-type electrodes.

[0080] Specifically, both P-type and N-type pads are prepared by electron beam evaporation, with the thickness of the P-type and N-type pads controlled at 1 μm. Specifically, P-type pads are fabricated on the surface of the P-type electrode and the corresponding insulating layer, completely covering the P-type electrode and the annular insulating layer, and are electrically connected to the P-type electrode. At the same time, N-type pads are fabricated on the surface of the N-type electrode and the corresponding insulating layer, completely covering the N-type electrode and the annular insulating layer, and are electrically connected to the N-type electrode.

[0081] (10) A passivation layer is prepared on a transparent conductive layer, an electrode, an insulating layer, and an N-type GaN layer;

[0082] Specifically, the deposition thickness using PECVD equipment is [missing information]. The passivation layer is deposited at a temperature of 240°C. It should be noted that after the passivation layer is deposited, the passivation layer above the P-type and N-type pads is opened by photolithography and etching processes to expose the P-type and N-type pads.

[0083] Example 2

[0084] This embodiment also provides an LED chip, the difference from embodiment 1 is that the electrode thickness is 1μm and the insulating layer thickness is 1μm.

[0085] Example 3

[0086] This embodiment also provides an LED chip, the difference from embodiment 1 is that the electrode thickness is 1μm.

[0087] Example 4

[0088] This embodiment also provides an LED chip, the difference from embodiment 1 is that the electrode thickness is 2μm and the insulating layer width is 3μm.

[0089] Example 5

[0090] This embodiment also provides an LED chip, the difference from embodiment 1 is that the electrode thickness is 3μm, the insulating layer thickness is 3μm, and the insulating layer thickness is 5μm.

[0091] The LED chips prepared in each embodiment and LED chips in the prior art were subjected to salt spray tests to count the number of LED chip electrodes detached. The experimental conditions were: NaCl concentration 5%, temperature 35℃, to accelerate LED chip aging. The test results are shown in Table 1.

[0092] Table 1

[0093]

[0094] As can be seen from the table, the LED chip prepared by the present invention did not show electrode detachment after 84 hours of aging, compared with the LED chip in the prior art. In contrast, the LED chip in the prior art began to show electrode detachment after 36 hours of aging, and after 84 hours of aging, there were 42 pieces of LED chip with electrode detachment.

[0095] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An LED chip, characterized by, The device includes an electrode and an insulating layer surrounding the electrode. The insulating layer includes a first insulator layer and a second insulator layer that cooperate with each other. The thickness of the insulating layer is greater than or equal to the thickness of the electrode. The refractive index of the first insulator layer is less than the refractive index of the second insulator layer. The second insulator layer is deposited on the first insulator layer, and the first insulator layer and the second insulator layer have the same shape and size; or, The first insulator layer and the second insulator layer are sequentially arranged around the electrode, and the distance between the first insulator layer and the electrode is the same as the distance between the first insulator layer and the second insulator layer; The refractive index of the first insulator layer is 1.4~1.5, and the refractive index of the second insulator layer is 1.45~1.

55.

2. The LED chip of claim 1, wherein, The LED chip further includes a substrate, on which an N-type GaN layer, an active layer, a P-type GaN layer, a transparent conductive layer, a passivation layer, and pads are sequentially deposited. The electrodes include P-type electrodes and N-type electrodes. The P-type electrodes are disposed on the P-type GaN layer, and the N-type electrodes are disposed on the N-type GaN layer. The pads and the passivation layer are sequentially deposited on the electrodes and the insulating layer.

3. The LED chip according to claim 2, characterized in that, The thickness of both the electrode and the pad is 1μm~3μm.

4. The LED chip according to claim 2, characterized in that, Both the electrode and the pad have a structure of multiple stacked metal layers, wherein the metal layers are one or more combinations of Cr, Al, Ti, Ni, Pt, Au, and Cu.

5. The LED chip according to claim 2, characterized in that, The transparent conductive layer has a through hole, and the P-type electrode and the insulating layer corresponding to the P-type electrode are in contact with the P-type GaN layer through the through hole.

6. A method for fabricating an LED chip, characterized in that, The method for preparing the LED chip according to any one of claims 1-5 comprises: Electrodes were prepared using electron beam evaporation. An insulating layer is deposited on the electrode using a PECVD device, and then subjected to photolithography, etching, and etching processes to obtain an insulating layer surrounding the electrode, wherein the thickness of the insulating layer is greater than or equal to the thickness of the electrode.

7. The method for preparing an LED chip according to claim 6, characterized in that, The deposition temperature of the insulating layer is 230℃~250℃.

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