A flip-chip LED chip and its preparation process

Abstract

The present invention discloses a flip-chip LED chip and its preparation process, belonging to the technical field of flip-chip LED chips. The flip-chip LED chip preparation process of the present invention eliminates the cumbersome DBR film deposition process and replaces the DBR with an ODR fully reflective film. This not only reduces the overall chip thickness and reduces material loss, but also makes the core more stable during inversion and sorting, reducing the probability of crystal flipping. Furthermore, the ODR fully reflective film can improve light extraction efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of flip-chip LED chips, and in particular to a flip-chip LED chip and a preparation process thereof. Background Art

[0002] At present, LED chips are mainly divided into upright LED chips, flip-chip LED chips and vertical LED chips. Among them, flip-chip LED chips mainly use DBR Bragg reflectors as light source reflection to increase the light output efficiency of the chip (such as Figure 1 DBR reflectors are typically fabricated by stacking silicon dioxide (SiO2) and titanium oxide (TiO2) multiple times, typically 30-50 layers with a deposition thickness of 3-6μm. However, as chip sizes shrink, the problems associated with thicker DBR reflective layers are gradually becoming apparent. For example, chips sized 03×06mil and 04×08mil have a long side that is twice the short side. Due to the minimal height-to-width difference, DBRs can easily cause core grain inversion during casting and even sorting, leading to casting and sorting failures and a waste of time and manpower. Furthermore, DBRs only reflect light within a certain wavelength range, resulting in low light extraction efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is: to overcome the shortcomings of the existing technology, provide a flip-chip LED chip and its preparation process, eliminate the cumbersome DBR film deposition, and adopt an ODR full reflection film layer instead of DBR, which not only reduces the overall thickness of the chip and reduces material loss, but also makes the core particles more stable during inversion and sorting, reduces the probability of crystal flipping, and the use of the ODR full reflection film layer can also improve the light output efficiency.

[0004] The technical solution of the present invention is:

[0005] In one aspect, the present invention provides a process for preparing a flip-chip LED chip, comprising the following steps:

[0006] S1 cleans the wafer substrate, which includes sapphire (PSS), N-GaN epitaxial layer, light-emitting layer (MQW) and P-GaN epitaxial layer;

[0007] S2 performs evaporation and annealing of the ITO layer on the wafer substrate;

[0008] S3: coating a positive photoresist on the ITO layer, and removing the positive photoresist on one side of the ITO layer through exposure and development;

[0009] S4 removes the exposed ITO layer and the underlying P-GaN epitaxial layer, the light-emitting layer, and part of the N-GaN epitaxial layer by dry etching to form an N-electrode conductive platform;

[0010] S5 uses a wet etching method to shrink the four sides of the ITO layer to expose the P-GaN epitaxial layer underneath, and then removes the remaining positive photoresist;

[0011] S6: coating a negative photoresist on the upper surface of the ITO layer, the P-GaN epitaxial layer and the N-electrode conductive platform, and removing the negative photoresist on the N-electrode conductive platform side through exposure and development;

[0012] S7 removes the exposed N-electrode conductive platform by dry etching to form a cutting path; then removes the remaining negative photoresist;

[0013] S8: applying negative photoresist on the ITO layer, the P-GaN epitaxial layer, the N-electrode conductive platform and the cutting path, and removing part of the negative photoresist on the ITO layer and the N-electrode conductive platform through exposure and development;

[0014] S9: evaporating a PAD1 layer on the negative photoresist and the exposed ITO layer and the N-electrode conductive platform, and then stripping off the negative photoresist, thereby depositing a PAD1 layer on the ITO layer and the N-electrode conductive platform respectively;

[0015] S10 deposits the PV1 layer on the ITO layer, P-GaN epitaxial layer, PAD1 layer, N-electrode conductive platform and cutting street;

[0016] S11: coating a positive photoresist on the PV1 layer, and removing part or all of the positive photoresist on the corresponding PAD1 layer through exposure and development; removing the exposed PV1 layer by wet etching, and then removing the remaining positive photoresist;

[0017] S12: coating a negative photoresist on the PV1 layer and the exposed PAD1 layer, and removing the negative photoresist on the PV1 layer through exposure and development;

[0018] S13: evaporating a metal aluminum layer on the PV1 layer and the negative photoresist, and then stripping off the negative photoresist, thereby coating a metal aluminum layer on the PV1 layer;

[0019] S14: coating a negative photoresist on the metal aluminum layer and the PAD1 layer, and removing the negative photoresist on the PAD1 layer through exposure and development;

[0020] S15 evaporates a PAD2 layer on the PAD1 layer and the negative photoresist, and then strips off the negative photoresist, thereby depositing a PAD2 layer on the PAD1 layer;

[0021] S16 deposits a PV2 layer on the semi-finished product obtained in step S15;

[0022] S17: a positive photoresist is applied on the PV2 layer, and a portion or all of the photoresist on the corresponding PAD2 layer is removed through exposure and development;

[0023] S18 removes the exposed PV2 layer by wet etching, and then removes the remaining positive photoresist to form a channel in contact with the solder paste.

[0024] Preferably, it is characterized in that in step S1, acetone, methanol and isopropanol solutions are used to clean the wafer substrate in sequence, and the cleaning temperature is 48-52°C, followed by water washing and nitrogen drying to clean off organic matter, oxides, metal residues and impurity particles; then hydrochloric acid → QDR cleaning → QDR cleaning → ventilation and drying are carried out, and the working temperature is 22.5-23.5°C to remove metal contaminants and particles on the lens.

[0025] Preferably, it is characterized in that, in step S2, the thickness of the ITO layer is 600-1100 angstroms; in step S9, the thickness of the PAD1 layer is 2.8±0.1 μm; in step S10, the thickness of the PV1 layer is 2100±200 angstroms; in step S13, the thickness of the metal aluminum layer is 1000±100 angstroms; in step S15, the thickness of the PAD2 layer is 4.8±0.2 μm; in step S16, the thickness of the PV2 layer is 800-1000 angstroms.

[0026] Preferably, in step S3, the thickness of the positive photoresist is 2±0.1 μm; in step S6, the thickness of the negative photoresist is 10 μm; in step S8, the thickness of the negative photoresist is 4±0.2 μm; in step S11, the thickness of the positive photoresist is 2±0.1 μm; in step S12, the thickness of the negative photoresist is 4±0.2 μm; in step S14, the thickness of the negative photoresist is 6±0.4 μm; in step S17, the thickness of the positive photoresist is 2±0.1 μm.

[0027] Preferably, in step S4, the height difference between the N-electrode conductive platform and the ITO layer is 1-1.2 μm; in step S7, the height difference between the cutting line and the N-electrode conductive platform is 5±0.3 μm.

[0028] Preferably, in step S5, the wet etching solution is a mixture of hydrochloric acid and ferric chloride, the etching temperature is 49-51° C., and after the etching is completed, the surface is cleaned and dried by QDR.

[0029] Preferably, in steps S5, S7, S11 and S18, the degumming method is as follows: first, three degumming treatments with a degumming liquid are performed, then a degumming treatment with isopropyl alcohol is performed, followed by two QDR cleanings, then a degumming treatment with isopropyl alcohol, and finally, nitrogen drying is performed. The degumming temperature of the degumming liquid is 88-92° C., and the temperature of the isopropyl alcohol degumming is room temperature.

[0030] On the other hand, the present invention also provides a flip-chip LED chip prepared by the above preparation process.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] Compared with the traditional flip-chip LED chip, the preparation process of the flip-chip LED chip of the present invention eliminates the tedious DBR film deposition and adopts the ODR full reflection film layer instead of DBR, which not only reduces the overall thickness of the chip and reduces the loss of materials, but also makes the core particles more stable during inversion and sorting, reduces the probability of crystal flipping, and adopts

[0033] The ODR fully reflective film layer can also improve light extraction efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0035] Figure 1 It is a structural diagram of an existing flip-chip LED chip.

[0036] Figure 2 It is a schematic diagram of step S2 in the present invention.

[0037] Figure 3 It is a schematic diagram of step S3 in the present invention.

[0038] Figure 4 It is a schematic diagram of step S4 in the present invention.

[0039] Figure 5 It is a schematic diagram of step S5 in the present invention.

[0040] Figure 6 It is a schematic diagram of step S6 in the present invention.

[0041] Figure 7 It is a schematic diagram of step S7 in the present invention.

[0042] Figure 8 It is a schematic diagram of step S8 in the present invention.

[0043] Figure 9 It is a schematic diagram of step S9 in the present invention.

[0044] Figure 10 It is a schematic diagram of step S10 in the present invention.

[0045] Figure 11 It is a schematic diagram of step S11 in the present invention.

[0046] Figure 12It is a schematic diagram of step S12 in the present invention.

[0047] Figure 13 It is a schematic diagram of step S13 in the present invention.

[0048] Figure 14 It is a schematic diagram of step S14 in the present invention.

[0049] Figure 15 It is a schematic diagram of step S15 in the present invention.

[0050] Figure 16 It is a schematic diagram of step S16 in the present invention.

[0051] Figure 17 It is a schematic diagram of step S17 in the present invention.

[0052] Figure 18 It is a schematic diagram of step S18 in the present invention.

[0053] Figure 19 1 is a reflectivity curve of the ODR total reflection film layer at different wavelengths in Example 1 of the present invention.

[0054] Figure 20 1 is the reflectivity curve of the DBR film layer at different wavelengths in Comparative Example 1 of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0056] Example 1

[0057] like Figure 2-18 As shown, the manufacturing process of the flip-chip LED chip of this embodiment includes the following steps:

[0058] S1 uses acetone, methanol, and isopropanol solutions to clean the wafer substrate in sequence, with the cleaning temperature at 48-52°C. Each cleaning stage lasts for 10 minutes. It is then rinsed with water and dried with nitrogen to remove organic matter, oxides, metal residues, and impurity particles. Hydrochloric acid, QDR cleaning, QDR cleaning, and ventilation drying are then performed at a working temperature of 22.5-23.5°C to remove metal contaminants and particles on the wafer substrate.

[0059] S2: Evaporation and annealing of the transparent current spreading layer (indium tin oxide) (ITO) on a wafer substrate. Evaporation was performed using a two-layer process using a magnetron sputtering machine (Evatac 137687BE). The contact layer was first deposited at 50W DC power, 150W RF power, 55sccm Ar flow, and 0.05sccm O2 flow. The blk layer was then deposited at 600W DC power, 400W RF power, 55sccm Ar flow, and 0.35sccm O2 flow. The ITO layer had a thickness of 600 angstroms and was subjected to rapid thermal annealing at 550°C, 3.5sccm O2 flow, and 15 minutes.

[0060] S3 coated the ITO layer with positive photoresist, using EP3200 positive photoresist (Beijing Kehua Microelectronics Materials Co., Ltd. EP3200), and used a dynamic spin coating equipment (Core Source Microelectronics Co., Ltd. KS-S150) for spin coating. The dynamic spin coating was 100 seconds, baked at 115°C for 110 seconds, and cooled at 23°C for 15 seconds. The thickness of the positive photoresist spin coating was 2 μm. The positive photoresist was then exposed using an ultraviolet exposure machine (Shanghai Microelectronics Equipment Co., Ltd. SSB320) with a wavelength of 365 nm and an exposure energy of 100 mJ / cm 2 , focus0; then develop, use TMAH as developer, develop for 90s, and bake at 115℃ for 110s after development to finally remove the positive photoresist on one side of the ITO layer;

[0061] S4 uses dry etching with an ICP etching machine (North Huachuang NMC GDS C200) at 0°C, a bias power of 300W, a source power of 1000W, and a pressure of 5mtorr to remove the exposed ITO layer and the underlying P-GaN epitaxial layer, the light-emitting layer, and part of the N-GaN epitaxial layer to form an N-electrode conductive platform. The height difference between the N-electrode conductive platform and the ITO layer is 1μm.

[0062] S5 uses a wet etching method to shrink the four sides of the ITO layer to expose the P-GaN epitaxial layer underneath, wherein the etching solution used in the wet etching is a mixture of hydrochloric acid HCl and ferric chloride FeCl3 (volume ratio of 10:22), and the etching is carried out in an environment of 50±1°C, and then QDR cleaning and drying are performed; then the remaining positive photoresist is removed, and the degumming process is as follows: first, three degumming treatments with degumming solution, then degumming treatment with isopropyl alcohol, followed by two QDR cleanings, then one degumming with isopropyl alcohol, and finally drying with nitrogen; wherein, the degumming solution is a mixture of N-methylpyrrolidone (NMP) and isopropyl alcohol, the degumming temperature of the degumming solution is 88-92°C, and the temperature of the isopropyl alcohol degumming is room temperature, and the processing time of each step of the degumming is 10 minutes. After degumming, the edge of the P-GaN layer is 3-5μm away from the edge of the ITO layer;

[0063] S6 coated the upper surface of the ITO layer, P-GaN epitaxial layer, and N-electrode conductive platform with negative photoresist. NR7 negative photoresist (Macronov Technology Co., Ltd.) was used for spin coating using a dynamic spin coating device. The dynamic spin coating was performed for 100 seconds, followed by baking at 150°C for 90 seconds and cooling at 23°C for 15 seconds. The thickness of the negative photoresist was approximately 10 μm. The negative photoresist was then exposed using a UV exposure machine with a wavelength of 365 nm and an exposure energy of 270 mJ / cm 2 , focus0; then develop, use TMAH as developer, develop for 200s, and bake at 115℃ for 110s after development to finally remove the negative photoresist on the N-electrode conductive platform side;

[0064] S7 uses an NMC etcher (North China Huachuang NMC GDS C200) for dry etching with a bias power of 150W, a source power of 500W, a chlorine (Cl2) flow rate of 80sccm, a boron trichloride flow rate of 10sccm, an argon (Ar) flow rate of 5sccm, a temperature of 15°C, and 24 cycles to remove the exposed N-electrode conductive platform to form a cutting street. The height difference between the cutting street and the N-electrode conductive platform is 5μm. The remaining negative photoresist is then removed. The stripping process is as follows: first, three stripping treatments with a stripping solution, then a stripping treatment with isopropyl alcohol, followed by two QDR cleanings, then one stripping with isopropyl alcohol, and finally drying with nitrogen. The stripping solution uses a mixture of N-methylpyrrolidone (NMP) and isopropyl alcohol. The stripping temperature of the stripping solution is 88-92°C, and the temperature of the isopropyl alcohol stripping is room temperature. The processing time for each step of the stripping process is 20min.

[0065] S8 coated the ITO layer, P-GaN epitaxial layer, N-electrode conductive platform, and cutting path with negative photoresist. 3205 negative photoresist (Beijing Kehua Microelectronics Materials Co., Ltd.) was used for spin coating. Dynamic spin coating was performed using a dynamic spin coating device. The dynamic spin coating was performed for 100 seconds, followed by baking at 110°C for 60 seconds and cooling at 23°C for 15 seconds. The thickness of the negative photoresist was approximately 4 μm. The negative photoresist was then exposed using a UV exposure machine with a wavelength of 365 nm and an exposure energy of 270 mJ / cm 2 , focus0; then develop, using TMAH as the developer, developing time 90s, and baking at 105℃ for 90s after development, finally removing part of the negative photoresist on the ITO layer and the N-electrode conductive platform;

[0066] S9 evaporates the PAD1 layer on the negative photoresist and the exposed ITO layer and the N electrode conductive platform. Ion cleaning and water washing are performed before evaporation. The first step of ion cleaning is 1000W power, time 15min, O2 flow rate 0sccm, argon flow rate 400sccm, temperature 70℃, and the second step is 400W power, time 12min, temperature 0℃, O2 flow rate 600sccm, argon flow rate 0sccm; water washing is about 15min; the evaporation of the PAD1 layer uses an electron beam evaporation machine (FSE, Fulin Technology Engineering Co., Ltd.), and the evaporation The negative photoresist is then stripped off using a fully automatic stripper (KS-S150-4ST, manufactured by Core Source Microelectronics Co., Ltd.). High-pressure NMP (N-methylpyrrolidone) is then used to remove the metal layer and the negative photoresist. Room-temperature acetone is then used to remove the residual adhesive and NMP. The wafer is then rinsed with pure water, dehydrated with IPA, and dried with nitrogen. Finally, the PAD1 layer is plated on the ITO layer and the N-electrode conductive platform.

[0067] S10 deposited the PV1 layer on the ITO layer, P-GaN epitaxial layer, PAD1 layer, N electrode conductive platform and cutting street by plasma enhanced chemical vapor deposition (PECVD). The deposition temperature was 300°C, the pressure was 90 Pa, the deposition time was 160 s, the N2O flow rate was 1000 sccm, the N2 flow rate was 400 sccm, and the SiH4 flow rate was 400 sccm. The thickness of the PV1 layer was about 2100 angstroms.

[0068] S11 coated the PV1 layer with positive photoresist, using EP3200 positive photoresist, and used a dynamic spin coating device for spin coating. The dynamic spin coating was performed for 100 seconds, followed by baking at 115°C for 110 seconds and cooling at 23°C for 15 seconds. The thickness of the positive photoresist spin coating was 2 μm. The positive photoresist was then exposed to UV light with a wavelength of 365 nm and an exposure energy of 250 mJ / cm 2 , focus0; then develop, use TMAH as developer, develop for 90s, bake at 120℃ for 110s after development, and finally remove part or all of the positive photoresist on the PAD1 layer; remove the exposed PV1 layer by wet etching, and use BOE etching cleaning machine ( Guanli Control Technology (Part 1) Hai) Co., Ltd.), the etching solution adopts BOE etching solution, which is a mixture of hydrofluoric acid and ammonium fluoride (volume ratio 1:30), the working temperature is 23±0.5℃, and the wet etching time is 160s; finally, the remaining positive photoresist is removed; the degumming process is as follows: first, it is subjected to three degumming treatments with degumming solution, then to isopropyl alcohol degumming treatment, followed by two QDR cleanings, then to isopropyl alcohol degumming, and finally to nitrogen drying; wherein, the degumming solution adopts a mixture of N-methylpyrrolidone (NMP) and isopropyl alcohol, the degumming temperature of the degumming solution is 88-92℃, the temperature of the isopropyl alcohol degumming is room temperature, and the processing time of each step of the degumming is 10min;

[0069] S12 coated the PV1 layer and the exposed PAD1 layer with negative photoresist. NR7 negative photoresist was used for spin coating using a dynamic spin coating device. The dynamic spin coating was performed for 100 seconds, followed by baking at 110°C for 60 seconds and cooling at 23°C for 60 seconds. The thickness of the negative photoresist was about 4 μm. The negative photoresist was then exposed using a UV exposure machine with a wavelength of 365 nm and an exposure energy of 270 mJ / cm 2 , focus0; then develop, use TMAH as developer, develop for 90s, and bake at 110℃ for 90s after development to finally remove the negative photoresist on the PV1 layer;

[0070] S13 uses a Fulin FSE electron beam evaporation machine to evaporate a metal aluminum layer on the PV1 layer and the negative photoresist at a deposition rate of 3 angstroms / second, with a metal aluminum layer thickness of 1000 angstroms. A fully automatic stripper is then used to strip off the negative photoresist. High-pressure NMP (N-methylpyrrolidone) is used to decouple the metal layer from the negative photoresist and remove the negative photoresist. Room-temperature acetone is used to remove residual adhesive and NMP. The wafer is then rinsed with pure water, dehydrated with isopropyl alcohol, and dried with nitrogen, thereby coating the metal aluminum layer on the PV1 layer.

[0071] Here, the silicon dioxide of the PV1 layer and the metal aluminum form a total reflection ODR structure, and the ODR replaces the Bragg reflection DBR reflector. Compared with the traditional DBR, the DBR only reflects light within a specific wavelength range. The DBR is obtained by stacking and depositing silicon dioxide and titanium oxide. The number of layers is generally 39-59 layers, and the thickness is about 4-6μm. There are problems of material waste and long deposition time. Therefore, the thickness of the DBR is relatively thick, which increases the overall thickness of the chip. It is easy to cause the chip to flip when flipping the film, which is not conducive to sorting and point measurement. The present invention adopts an ODR structure instead of DBR, and only needs to evaporate a layer of PV1 layer and a metal aluminum layer to reduce the overall thickness of the chip and reduce the probability of the core particle flipping when flipping the film;

[0072] S14 coated the aluminum layer and the PAD1 layer with negative photoresist. 3205 negative photoresist (Beijing Kehua Microelectronics Materials Co., Ltd.) was used for spin coating. Dynamic spin coating was performed using a dynamic spin coating device. The dynamic spin coating was performed for 100 seconds, followed by baking at 110°C for 60 seconds and cooling at 23°C for 15 seconds. The thickness of the negative photoresist was approximately 6 μm. The negative photoresist was then exposed to UV light at a wavelength of 365 nm and an exposure energy of 270 mJ / cm 2 , focus0; then develop, use TMAH as developer, develop for 90s, and bake at 105℃ for 90s after development to finally remove the negative photoresist on the PAD1 layer;

[0073] S15 evaporates the PAD2 layer on the PAD1 layer and the negative photoresist, and performs ion cleaning and water washing before evaporation. The first step of ion cleaning has a power of 1000W, a time of 15min, an O2 flow rate of 0sccm, an argon flow rate of 400sccm, and a temperature of 70°C. The second step has a power of 400W, a time of 12min, a temperature of 0°C, an O2 flow rate of 600sccm, and an argon flow rate of 0sccm. The water washing lasts about 15min. The evaporation of the PAD2 layer is carried out by Fulin FSE Electronics. A beam evaporation machine is used to deposit multiple layers of metal (Ni, Ti, Pt, Au, etc.), with the PAD2 layer being approximately 4.8μm thick. A fully automatic stripper is then used to remove the negative photoresist. High-pressure NMP (N-methylpyrrolidone) is then used to decouple the metal layer from the negative photoresist and remove the negative photoresist. Room-temperature acetone is then used to remove residual photoresist and NMP. The wafer is then rinsed with pure water, dehydrated with IPA, and dried with nitrogen. Finally, the PAD2 layer is deposited on the PAD1 layer.

[0074] S16: depositing a PV2 layer on the semi-finished product of step S15 by plasma enhanced chemical vapor deposition (PECVD) as a protective passivation layer for the chip, with a deposition temperature of 300° C., a pressure of 90 Pa, a deposition time of 100 s, an N2O flow rate of 1000 sccm, an N2 flow rate of 400 sccm, and an SiH4 flow rate of 400 sccm. The thickness of the PV2 layer is about 800 angstroms.

[0075] S17 coated the PV2 layer with positive photoresist using EP3200 positive photoresist. The spin coating was performed using a dynamic spin coating device. The dynamic spin coating was performed for 100 seconds, followed by baking at 115°C for 110 seconds and cooling at 23°C for 15 seconds. The thickness of the positive photoresist was 2 μm. The positive photoresist was then exposed using a UV exposure machine with a wavelength of 365 nm and an exposure energy of 250 mJ / cm 2 , focus0; then develop, using TMAH as the developer, developing time 90s, and baking at 120°C for 110s after development, and finally remove part or all of the positive photoresist on the PV2 layer corresponding to the PAD2 layer;

[0076] S18 removes the exposed PV2 layer by wet etching and uses a BOE etching and cleaning machine ( Crown Ceremony Control Department Technology (Shanghai) Co., Ltd. ), the etching solution used is BOE etching solution, which is a mixture of hydrofluoric acid and ammonium fluoride (volume ratio 1:30), the working temperature is 23±0.5℃, and the wet etching time is 100s; finally, the remaining positive photoresist is removed, and the degumming process is as follows: first, it is degummed three times with degumming solution, then degummed with isopropyl alcohol, followed by two QDR cleanings, then degummed with isopropyl alcohol, and finally dried with nitrogen; wherein, the degumming solution uses a mixture of N-methylpyrrolidone (NMP) and isopropyl alcohol, the degumming temperature of the degumming solution is 88-92℃, the temperature of the isopropyl alcohol degumming is room temperature, and the processing time of each step during degumming is 10min, and finally a flip-chip LED chip is obtained.

[0077] Comparative Example 1

[0078] The difference between Comparative Example 1 and Example 1 is that: 39 layers of DBR film (silicon dioxide and titanium dioxide are alternately stacked, and the first layer is silicon dioxide) are used, and the thickness is 4 μm.

[0079] Depend on Figure 19-20 It can be seen that the reflectivity of the DBR film layer in comparative example 1 is about 99% within the reflection wavelength range of 400-700nm, and the reflection of light outside this wavelength range is poor; while the ODR structure of embodiment 1 of the present invention has a reflectivity of about 85% even at the wavelength of 850nm where the reflectivity is the lowest, and has high light extraction efficiency.

[0080] Although the present invention has been described in detail with reference to the accompanying drawings and in combination with preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and such modifications or substitutions shall be within the scope of the present invention. Any person skilled in the art who is familiar with the present invention may easily conceive of changes or substitutions within the technical scope disclosed in the present invention, and such changes or substitutions shall be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A process for preparing a flip-chip LED chip, characterized in that: The following steps are involved: S1 cleans the wafer substrate, which includes sapphire, N-GaN epitaxial layer, light-emitting layer and P-GaN epitaxial layer; S2 performs evaporation and annealing of the ITO layer on the wafer substrate; S3: coating a positive photoresist on the ITO layer, and removing the positive photoresist on one side of the ITO layer through exposure and development; S4 removes the exposed ITO layer and the underlying P-GaN epitaxial layer, the light-emitting layer, and part of the N-GaN epitaxial layer by dry etching to form an N-electrode conductive platform; S5 uses a wet etching method to shrink the four sides of the ITO layer to expose the P-GaN epitaxial layer underneath, and then removes the remaining positive photoresist; S6: coating a negative photoresist on the upper surface of the ITO layer, the P-GaN epitaxial layer and the N-electrode conductive platform, and removing the negative photoresist on the N-electrode conductive platform side through exposure and development; S7 removes the exposed N-electrode conductive platform by dry etching to form a cutting path; The remaining negative photoresist is then removed; S8: applying negative photoresist on the ITO layer, the P-GaN epitaxial layer, the N-electrode conductive platform and the cutting path, and removing part of the negative photoresist on the ITO layer and the N-electrode conductive platform through exposure and development; S9: evaporating a PAD1 layer on the negative photoresist and the exposed ITO layer and the N-electrode conductive platform, and then stripping off the negative photoresist, thereby depositing a PAD1 layer on the ITO layer and the N-electrode conductive platform respectively; S10 deposits the PV1 layer on the ITO layer, P-GaN epitaxial layer, PAD1 layer, N-electrode conductive platform and cutting street; S11: coating a positive photoresist on the PV1 layer, and removing part or all of the positive photoresist on the corresponding PAD1 layer through exposure and development; The exposed PV1 layer is removed by wet etching, and then the remaining positive photoresist is removed; S12: coating a negative photoresist on the PV1 layer and the exposed PAD1 layer, and removing the negative photoresist on the PV1 layer through exposure and development; S13: evaporating a metal aluminum layer on the PV1 layer and the negative photoresist, and then stripping off the negative photoresist, thereby coating a metal aluminum layer on the PV1 layer; S14: coating a negative photoresist on the metal aluminum layer and the PAD1 layer, and removing the negative photoresist on the PAD1 layer through exposure and development; S15 evaporates a PAD2 layer on the PAD1 layer and the negative photoresist, and then strips off the negative photoresist, thereby depositing a PAD2 layer on the PAD1 layer; S16 deposits a PV2 layer on the semi-finished product obtained in step S15; S17: a positive photoresist is applied on the PV2 layer, and a portion or all of the photoresist on the corresponding PAD2 layer is removed through exposure and development; S18 removes the exposed PV2 layer by wet etching, and then removes the remaining positive photoresist to form a channel in contact with the solder paste.

2. The process for preparing a flip-chip LED chip according to claim 1, wherein: In step S1, the wafer substrate is cleaned with acetone, methanol and isopropanol solutions in sequence at a cleaning temperature of 48-52°C, followed by water washing and nitrogen drying; then hydrochloric acid → QDR cleaning → QDR cleaning → ventilation and drying are performed, and the working temperature is 22.5-23.5°C.

3. The process for preparing a flip-chip LED chip according to claim 1, wherein: In step S2, the thickness of the ITO layer is 600-1100 angstroms; in step S9, the thickness of the PAD1 layer is 2.8±0.1 μm; in step S10, the thickness of the PV1 layer is 2100±200 angstroms; in step S13, the thickness of the metal aluminum layer is 1000±100 angstroms; in step S15, the thickness of the PAD2 layer is 4.8±0.2 μm; in step S16, the thickness of the PV2 layer is 800-1000 angstroms.

4. The process for preparing a flip-chip LED chip according to claim 1, wherein: In step S3, the thickness of the positive photoresist is 2±0.1 μm; in step S6, the thickness of the negative photoresist is 10 μm; in step S8, the thickness of the negative photoresist is 4±0.2 μm; in step S11, the thickness of the positive photoresist is 2±0.1 μm; in step S12, the thickness of the negative photoresist is 4±0.2 μm; in step S14, the thickness of the negative photoresist is 6±0.4 μm; in step S17, the thickness of the positive photoresist is 2±0.1 μm.

5. The process for preparing a flip-chip LED chip according to claim 1, wherein: In step S4 , the height difference between the N-electrode conductive platform and the ITO layer is 1-1.2 μm; in step S7 , the height difference between the cutting line and the N-electrode conductive platform is 5±0.3 μm.

6. The process for preparing a flip-chip LED chip according to claim 1, wherein: In step S5, the wet etching solution is a mixture of hydrochloric acid and ferric chloride, and the etching temperature is 49-51° C. After the etching is completed, the surface is cleaned and dried by QDR.

7. The process for preparing a flip-chip LED chip according to claim 1, wherein: In steps S5, S7, S11 and S18, the degumming method is as follows: first, three degumming treatments with a degumming solution are performed, then a degumming treatment with isopropyl alcohol is performed, followed by two QDR cleanings, then a degumming treatment with isopropyl alcohol, and finally drying with nitrogen gas; The temperature of the degumming liquid is 88-92℃, and the temperature of the isopropyl alcohol degumming is room temperature.

8. A flip-chip LED chip prepared by the preparation process according to any one of claims 1 to 7.

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