A high speed comparator with controllable speed

Abstract

The application belongs to the technical field of analog integrated circuits, and particularly relates to a high-speed comparator circuit with adjustable speed. The application adds a speed adjusting circuit on the basis of a traditional latch, so that the speed of the comparator is no longer limited by the power supply voltage, and the comparison speed of the comparator is effectively improved. At the same time, the speed adjusting circuit can effectively improve the flexibility and multiplicity of the comparator, so that the comparator can meet different speed requirements of application scenarios. The application aims to provide a high-speed comparator circuit with adjustable speed, which is suitable for low power supply voltage scenarios and high-speed analog-to-digital conversion applications.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of data conversion in analog integrated circuit design, and particularly relates to a high-speed comparator circuit with controllable speed. BACKGROUND

[0002] The comparator circuit is the most common signal processing circuit in the field of analog integrated circuits, and its function is to compare two input signals and output the comparison result in the form of differential or single-ended. The output result has two states of "1" and "0". In an analog-to-digital converter (ADC), the application of the comparator is more extensive. In particular, with the rise of 5G communication, smart home and Internet of Things, higher requirements are put forward for the conversion speed of the analog-to-digital converter, and at the same time, higher requirements are put forward for the speed of the comparator circuit.

[0003] At present, the traditional high-speed comparator circuit structure often increases the size of MOS tube and the power consumption of the circuit to improve the comparison speed of the comparator, and for some specific speed requirements, the comparator needs to be redesigned, resulting in poor flexibility and reusability of the circuit.

[0004] Therefore, a high-speed comparator circuit with adjustable speed is expected, which can improve the speed of the comparator, the overall circuit power consumption, and the flexibility and reusability of the circuit. SUMMARY

[0005] The technical problem to be solved by the present application is to overcome the defects of poor flexibility and reusability of the circuit caused by the unadjustable speed of the comparator in the prior art, and the increase of the overall circuit power consumption caused by the high-speed requirement of the comparator, and to provide a high-speed comparator with controllable speed.

[0006] The present application solves the above technical problems by the following technical solutions:

[0007] A high-speed comparator with controllable speed, comprising an inverted clock generating circuit, a data latch circuit with speed adjustment function and a pre-buffer circuit; the input of the inverted clock generating circuit is an external CLK signal, and the output is a signal opposite in phase to the external CLK signal, defined as CLK_N signal; the input end of the data latch circuit with speed adjustment function is connected with the external CLK signal and the CLK_N signal, used for adjusting the comparison speed of the high-speed comparator, and the output end of the data latch circuit with speed adjustment function is the output end of the high-speed comparator; the input end of the pre-buffer circuit is the input end of the high-speed comparator, and the pre-buffer circuit is also connected with the data latch circuit with speed adjustment function, and the pre-buffer circuit is used for collecting, buffering and isolating the input end signal of the high-speed comparator.

[0008] Further, the inverting clock generating circuit comprises a first MOS transistor and a second MOS transistor; the gate of the first MOS transistor and the gate of the second MOS transistor are connected to an external CLK signal, the source and the substrate of the first MOS transistor are connected to a VSS level; the drain of the first MOS transistor and the drain of the second MOS transistor are connected, and the connection point is an output terminal of the inverting clock generating circuit, and the output signal is defined as a CLK_N signal;

[0009] The source and the substrate of the second MOS transistor are connected and connected to a VDD level.

[0010] The first MOS transistor is an NMOS transistor, and the second MOS transistor is a PMOS transistor.

[0011] Further, the data latch circuit with speed adjustment function comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a ninth switch.

[0012] The first connection end of the first switch is connected to the first connection end of the first capacitor, and the second connection end of the first switch is connected to the first connection end of the third switch and is commonly connected to the first connection end of the second capacitor.

[0013] The first connection end of the second switch is connected to the second connection end of the first capacitor, and the second connection end of the second switch is connected to the first connection end of the fourth switch and is commonly connected to the second connection end of the second capacitor.

[0014] The second connection end of the third switch is connected to a first bias voltage, and the second connection end of the fourth switch is connected to a second bias voltage.

[0015] The first connection end of the fifth switch is connected to the first connection end of the third capacitor, and the second connection end of the fifth switch is connected to the first connection end of the seventh switch and is commonly connected to the first connection end of the fourth capacitor.

[0016] The first connection end of the sixth switch is connected to the second connection end of the third capacitor, and the second connection end of the sixth switch is connected to the first connection end of the eighth switch and is commonly connected to the second connection end of the fourth capacitor.

[0017] The second connection end of the seventh switch is connected to the second bias voltage, and the second connection end of the eighth switch is connected to the first bias voltage.

[0018] The first switch, the second switch, the fifth switch and the sixth switch are clock control switches, and the closing and opening of the switches are controlled by an external CLK signal;

[0019] The third switch, the fourth switch, the seventh switch and the eighth switch are clock control switches, and the closing and opening of the switches are controlled by the CLK_N signal;

[0020] The capacitance of the first capacitor is equal to that of the third capacitor.

[0021] The capacitance of the second capacitor is equal to that of the fourth capacitor.

[0022] The gate of the third MOS tube is connected to the first connection end of the fifth switch and the first connection end of the third capacitor, the source and substrate of the third MOS tube are connected to a VSS level, the drain of the third MOS tube is connected to the first connection end of the first switch, the first connection end of the first capacitor, the drain of the fifth MOS tube and the first connection end of the ninth switch, and the connection point is a positive output end OUTP of a high-speed comparator.

[0023] The gate of the fourth MOS tube is connected to the first connection end of the second switch and the second connection end of the first capacitor, the source and substrate of the fourth MOS tube are connected to a VSS level, the drain of the fourth MOS tube is connected to the first connection end of the sixth switch, the second connection end of the third capacitor, the drain of the sixth MOS tube and the second connection end of the ninth switch, and the connection point is a negative output end OUTN of the high-speed comparator.

[0024] The gate of the fifth MOS tube is connected to the negative output end OUTN of the high-speed comparator, the source and substrate of the fifth MOS tube are connected to a VDD level, and the drain of the fifth MOS tube is connected to the positive output end OUTP of the high-speed comparator.

[0025] The gate of the sixth MOS tube is connected to the positive output end OUTP of the high-speed comparator, the source and substrate of the sixth MOS tube are connected to a VDD level, and the drain of the sixth MOS tube is connected to the negative output end OUTN of the high-speed comparator.

[0026] The ninth switch is a clock control switch, and the closing and opening of the switch are controlled by an external CLK signal.

[0027] The third MOS tube and the fourth MOS tube are NMOS tubes, and the fifth MOS tube and the sixth MOS tube are PMOS tubes.

[0028] Further, the pre-buffer circuit comprises a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a tenth switch and an eleventh switch.

[0029] The gate of the seventh MOS transistor is connected to the negative input end VINN of the high-speed comparator, the substrate of the seventh MOS transistor is connected to the VSS level, the source of the seventh MOS transistor and the source of the eighth MOS transistor are connected to the drain of the ninth MOS transistor, the drain of the seventh MOS transistor and the source of the tenth MOS transistor are connected, and are commonly connected to the first connection end of the eleventh switch.

[0030] The gate of the eighth MOS transistor is connected to the positive input end VINP of the high-speed comparator, the substrate of the eighth MOS transistor is connected to the VSS level, the drain of the eighth MOS transistor and the source of the eleventh MOS transistor are connected, and are commonly connected to the first connection end of the tenth switch.

[0031] The second connection end of the tenth switch is connected to the gate of the third MOS transistor in the data latch circuit with the speed adjustment function.

[0032] The second connection end of the eleventh switch is connected to the gate of the fourth MOS transistor in the data latch circuit with the speed adjustment function.

[0033] The gate of the ninth MOS transistor is connected to the third bias voltage, and the substrate and the source of the ninth MOS transistor are connected to the VSS level.

[0034] The gate, the drain and the substrate of the tenth MOS transistor are connected to the VDD level.

[0035] The gate, the drain and the substrate of the eleventh MOS transistor are connected to the VDD level.

[0036] The tenth switch and the eleventh switch are clock control switches, and the closing and opening of the switches are controlled by an external CLK signal.

[0037] The seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor and the eleventh MOS transistor are all NMOS transistors.

[0038] The application has the advantages that the speed of the high-speed comparator is improved, the design flexibility of the comparator is improved, and the application scenarios of the comparator are widened, and the circuit is especially suitable for an analog-to-digital conversion circuit with high speed requirements. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 The circuit principle diagram of the application;

[0040] Figure 2 The time control switch used in the application;

[0041] Figure 3 is a working principle diagram of the application, wherein (a) is a circuit state when CLK is high and CLK_N is low, and (b) is a circuit state when CLK is low and CLK_N is high. DETAILED DESCRIPTION

[0042] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0043] It should be noted that, in the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. For example, the first connection end and the second connection end of the capacitor and the switch only represent two connection ends of the capacitor and the switch, and the first connection end and the second connection end can be interchanged.

[0044] The controllable speed high-speed comparator of the present application can be used in different speed requirement scenarios of analog-to-digital conversion by adding a speed adjusting circuit, such as Figure 1 As shown in the figure, the controllable speed high-speed comparator of the present application includes three parts: an inverting clock generating circuit, a data latch circuit with a speed adjusting function, and a pre-buffer circuit.

[0045] The inverting clock generating circuit inputs a CLK signal and outputs a CLK_N signal opposite in phase to the CLK signal. The inverting clock generating circuit includes a first MOS transistor MN1 and a second MOS transistor MP2. The gate of the first MOS transistor MN1 is connected to the gate of the second MOS transistor MP2 and inputs the CLK signal. The source and the substrate of the first MOS transistor MN1 are connected and connected to a VSS level. The drain of the first MOS transistor MN1 and the drain of the second MOS transistor MP2 are connected, and the CLK_N signal is obtained at the connection. The source and the substrate of the second MOS transistor MP2 are connected and connected to a VDD level. The inverting clock generating circuit generates the CLK_N signal opposite to the CLK signal and provides sufficient driving capability for the CLK_N signal.

[0046] The application discloses a data latch circuit with a speed adjusting function, and a part of nodes of the data latch circuit with the speed adjusting function are connected with an output end of an inverting clock generating circuit or a CLK signal, and an embedded speed adjusting circuit is used for adjusting the comparison speed of a high-speed comparator; the data latch circuit with the speed adjusting function comprises a first switch S1, a first switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a third MOS tube MN3, a fourth MOS tube MN4, a fifth MOS tube MP5, a sixth MOS tube MP6 and a ninth switch S9; a first connecting end of the first switch S1 is connected with a first connecting end of the first capacitor C1, a second connecting end is connected with a first connecting end of the third switch S3 and is commonly connected to a first connecting end of the second capacitor C2; a first connecting end of the first switch S2 is connected with a second connecting end of the first capacitor C1, a second connecting end is connected with a first connecting end of the fourth switch S4 and is commonly connected to a second connecting end of the second capacitor C2; the first connecting end of the third switch S3 is connected with the first connecting end of the first switch S1 and is commonly connected to the first connecting end of the second capacitor C2, and a second connecting end is connected with a first bias voltage; the first connecting end of the fourth switch S4 is connected with the second connecting end of the first switch S2 and is commonly connected to the second connecting end of the second capacitor C2, and a second connecting end is connected with a second bias voltage; a first connecting end of the fifth switch S5 is connected with a first connecting end of the third capacitor C3, a second connecting end is connected with a first connecting end of the seventh switch S7 and is commonly connected to a first connecting end of the fourth capacitor C4; a first connecting end of the sixth switch S6 is connected with a second connecting end of the third capacitor C3, a second connecting end is connected with a first connecting end of the eighth switch S8 and is commonly connected to a second connecting end of the fourth capacitor C4; the first connecting end of the seventh switch S7 is connected with the second connecting end of the fifth switch S5 and is commonly connected to the first connecting end of the fourth capacitor C4, and a second connecting end is connected with the second bias voltage; the first connecting end of the eighth switch S8 is connected with the second connecting end of the sixth switch S6 and is commonly connected to the second connecting end of the fourth capacitor C4, and a second connecting end is connected with the first bias voltage; the first switch S1, the first switch S2, the fifth switch S5 and the sixth switch S6 are clock control switches, and the closing and opening of the switches are controlled by a CLK signal; the third switch S3, the fourth switch S4, the seventh switch S7 and the eighth switch S8 are clock control switches, and the closing and opening of the switches are controlled by a CLK_N signal; the capacitance of the first capacitor C1 is equal to that of the third capacitor C3; the capacitance of the second capacitor C2 is equal to that of the fourth capacitor C4.The gate of the third MOS transistor MN3 is connected with the first connecting end of the fifth switch S5 and the first connecting end of the third capacitor C3, the source and the substrate of the third MOS transistor MN3 are connected and connected with the VSS level, the drain of the third MOS transistor MN3 is connected with the first connecting end of the first switch S1, the first connecting end of the first capacitor C1, the drain of the fifth MOS transistor MP5 and the first connecting end of the ninth switch S9, and the connecting place of the drain of the third MOS transistor MN3 is the positive output end OUTP of the high-speed comparator with controllable speed; the gate of the fourth MOS transistor MN4 is connected with the first connecting end of the first switch S2 and the second connecting end of the first capacitor C1, the source and the substrate of the fourth MOS transistor MN4 are connected and connected with the VSS level, the drain of the fourth MOS transistor MN4 is connected with the first connecting end of the sixth switch S6, the second connecting end of the third capacitor C3, the drain of the sixth MOS transistor MP6 and the second connecting end of the ninth switch S9, and the connecting place of the drain of the fourth MOS transistor MN4 is the negative output end OUTN of the high-speed comparator with controllable speed; the gate of the fifth MOS transistor MP5 is connected with the negative output end OUTN of the high-speed comparator with controllable speed, the source and the substrate of the fifth MOS transistor MP5 are connected and connected with the VDD level, and the drain of the fifth MOS transistor MP5 is connected with the positive output end OUTP of the high-speed comparator with controllable speed; the gate of the sixth MOS transistor MP6 is connected with the positive output end OUTP of the high-speed comparator with controllable speed, the source and the substrate of the sixth MOS transistor MP6 are connected and connected with the VDD level, and the drain of the sixth MOS transistor MP6 is connected with the negative output end OUTN of the high-speed comparator with controllable speed; the ninth switch S9 is a clock control switch, and the closing and opening of the switch are controlled by the CLK signal; the data latch circuit with speed adjustment function controls different phases through the CLK and CLK_N signals, so that the setting of the first bias voltage and the second bias voltage can change the comparison speed of the comparator.

[0047] The pre-buffer circuit is connected with the data latch circuit with the speed adjustment function, and is connected with the VINN and VINP signals for collecting, buffering and isolating the VINN and VINP signals. The pre-buffer circuit comprises a seventh MOS transistor MN7, an eighth MOS transistor MN8, a ninth MOS transistor MN9, a tenth MOS transistor MN10, an eleventh MOS transistor MN11, a tenth switch S10 and an eleventh switch S11; the gate of the seventh MOS transistor MN7 is connected with the negative input end VINN of the high-speed comparator with the controllable speed, the substrate of the seventh MOS transistor MN7 is connected with the VSS level, the source of the seventh MOS transistor MN7 and the source of the eighth MOS transistor MN8 are connected with the drain of the ninth MOS transistor MN9, the drain of the seventh MOS transistor MN7 and the source of the tenth MOS transistor MN10 are connected with the first connection end of the eleventh switch S11; the gate of the eighth MOS transistor MN8 is connected with the positive input end VINP of the high-speed comparator with the controllable speed, the substrate of the eighth MOS transistor MN8 is connected with the VSS level, the drain of the eighth MOS transistor MN8 and the source of the eleventh MOS transistor MN11 are connected with the first connection end of the tenth switch S10; the second connection end of the tenth switch S10 is connected with the gate of the third MOS transistor in the data latch circuit with the comparator speed adjustment circuit; the second connection end of the eleventh switch S11 is connected with the gate of the fourth MOS transistor in the data latch circuit with the comparator speed adjustment circuit; the gate of the ninth MOS transistor MN9 is connected with the third bias voltage, the substrate and the source of the ninth MOS transistor MN9 are connected with the VSS level; the gate, the drain and the substrate of the tenth MOS transistor MN10 are connected with the VDD level; the gate, the drain and the substrate of the eleventh MOS transistor MN11 are connected with the VDD level; the tenth switch S10 and the eleventh switch S11 are clock control switches, and the closing and opening of the switches are controlled by the CLK signal.

[0048] The tenth switch S10 and the eleventh switch S11 are clock control switches, and the closing and opening of the switches are controlled by the CLK signal. Figure 2 The tenth switch S10 and the eleventh switch S11 are clock control switches, and the closing and opening of the switches are controlled by the CLK signal.

[0049] The working principle of the application is as follows:

[0050] (1) When CLK is high and CLK_N is low, the present application is in reset phase. As shown in Fig. 3(a), the VINN signal acts on the gate of the seventh MOS transistor MN7 in the pre-buffer circuit and transmits the signal to the VP node, and the signal of the VP node acts on the gate of the fourth MOS transistor MN4 in the data latch circuit with speed regulation function to obtain the VOP signal. The VINP signal acts on the gate of the eighth MOS transistor MN8 in the pre-buffer circuit and transmits the signal to the VN node, and the signal of the VN node acts on the gate of the third MOS transistor MN3 in the data latch circuit with speed regulation function to obtain the VON signal. The charge on the second capacitor C2 in the data latch circuit with speed regulation function is transmitted to the first capacitor C1 through the first switch S1 and the second switch S2, so that the voltage difference between the second connection end and the first connection end of the first capacitor C1 is the voltage difference V2-V1 between the second bias voltage V2 and the first bias voltage V1. The charge on the fourth capacitor C4 in the data latch circuit with speed regulation function is transmitted to the third capacitor C3 through the fifth switch S5 and the sixth switch S6, so that the voltage difference between the first connection end and the second connection end of the third capacitor C3 is the voltage difference V2-V1 between the second bias voltage V2 and the first bias voltage V1. The closing of the ninth switch S9 makes the difference between the two ends of the comparator OUTP and OUTN close to achieve the reset of the comparator.

[0051] (2) When CLK is low and CLK_N is high, the application is in the comparison phase. As shown in Fig. 3(b), the eleventh switch S11 and the tenth switch S10 of the pre-buffer circuit are disconnected, and the VINN signal and the VINP signal no longer act on the data latch with the speed adjustment function. The third switch S3 and the fourth switch S4 in the data latch with the speed adjustment function are closed, the second bias voltage V2 is connected to the second connection end of the second capacitor C2, and the first bias voltage V1 is connected to the first connection end of the second capacitor C2, so as to update the charge on the second capacitor C2. The seventh switch S7 and the eighth switch S8 in the data latch with the speed adjustment function are closed, the second bias voltage V2 is connected to the first connection end of the fourth capacitor C4, and the first bias voltage V1 is connected to the second connection end of the fourth capacitor C4, so as to update the charge on the fourth capacitor C4. At the same time, because the ninth switch S9 is disconnected, the inverter composed of the fourth MOS tube MN4, the first capacitor C1 and the sixth MOS tube MP6 and the inverter composed of the third MOS tube MN3, the first capacitor C3 and the fifth MOS tube MP5 are cross-coupled to form a latch, and the differential output result OUTP-OUTN of the comparator is obtained by sampling the VOP-VON signal obtained from the sampling phase. The application realizes the adjustable speed, and the voltage difference between the voltage at the first connection end of the first capacitor C1 and the voltage at the second connection end and the voltage difference between the voltage at the first connection end of the third capacitor C3 and the voltage at the second connection end are the voltage difference between the second bias voltage V2 and the first bias voltage V1, so that when the inverter composed of the fourth MOS tube MN4, the first capacitor C1 and the sixth MOS tube MP6 and the inverter composed of the third MOS tube MN3, the first capacitor C3 and the fifth MOS tube MP5 are cross-coupled to form a latch, the source-gate voltage VSG6 of the sixth MOS tube MP6 plus the gate-source voltage VGS4 of the fourth MOS tube MN4 is the power supply voltage VDD minus the second bias voltage V2 plus the first bias voltage V1, that is, VSG6+VGS4=VDD+V2-V1; the source-gate voltage VSG5 of the fifth MOS tube MP5 plus the gate-source voltage VGS3 of the third MOS tube MN3 is the power supply voltage VDD minus the second bias voltage V2 plus the first bias voltage V1, that is, VSG5+VGS3=VDD+V2-V1. Therefore, the controllable speed of the high-speed comparator can be realized by adjusting the difference between the second bias voltage V2 and the first bias voltage V1.

[0052] The above is the preferred embodiment of the application. It should be pointed out that those skilled in the art can make several improvements and refinements without departing from the principles of the application, and these improvements and refinements should also be considered as the protection scope of the application.

Claims

1. A controllable speed high speed comparator characterized by, The application relates to a clock signal generating circuit, which comprises an inverting clock signal generating circuit, a data latch circuit with a speed adjusting function and a pre-buffer circuit. The input of the inverting clock signal generating circuit is an external CLK signal, and the output is a signal opposite in phase to the external CLK signal, defined as a CLK_N signal. The input of the data latch circuit with the speed adjusting function is connected with the external CLK signal and the CLK_N signal, and is used for adjusting the comparison speed of a high-speed comparator. The input of the pre-buffer circuit is the input of the high-speed comparator, and the pre-buffer circuit is also connected with the data latch circuit with the speed adjusting function. The pre-buffer circuit is used for collecting, buffering and isolating the input signal of the high-speed comparator. The inverting clock signal generating circuit comprises a first MOS tube and a second MOS tube; the gate of the first MOS tube and the gate of the second MOS tube are connected with the external CLK signal; the source and the substrate of the first MOS tube are connected with a VSS level; the drain of the first MOS tube and the drain of the second MOS tube are connected, and the connection point is the output of the inverting clock signal generating circuit, and the output signal is defined as the CLK_N signal. The source and the substrate of the second MOS tube are connected and connected with a VDD level. The first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube. The data latch circuit with the speed adjusting function comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a ninth switch. The first connection end of the first switch is connected with the first connection end of the first capacitor, and the second connection end of the first switch is connected with the first connection end of the third switch and is jointly connected to the first connection end of the second capacitor. The first connection end of the second switch is connected with the second connection end of the first capacitor, and the second connection end of the second switch is connected with the first connection end of the fourth switch and is jointly connected to the second connection end of the second capacitor. The second connection end of the third switch is connected with a first bias voltage, and the second connection end of the fourth switch is connected with a second bias voltage. The first connection end of the fifth switch is connected with the first connection end of the third capacitor, and the second connection end of the fifth switch is connected with the first connection end of the seventh switch and is jointly connected to the first connection end of the fourth capacitor. The first connection end of the sixth switch is connected with the second connection end of the third capacitor, and the second connection end of the sixth switch is connected with the first connection end of the eighth switch and is jointly connected to the second connection end of the fourth capacitor. The second connection end of the seventh switch is connected with the second bias voltage, and the second connection end of the eighth switch is connected with the first bias voltage. The first switch, the second switch, the fifth switch and the sixth switch are clock control switches, and the closing and opening of the switches are controlled by the external CLK signal. The third switch, the fourth switch, the seventh switch and the eighth switch are clock control switches, and the closing and opening of the switches are controlled by the CLK_N signal; The first capacitor and the third capacitor have equal capacitance values; The second capacitor and the fourth capacitor have equal capacitance values; The gate of the third MOS tube is connected with the first connection end of the fifth switch and the first connection end of the third capacitor, the source and substrate of the third MOS tube are connected with the VSS level, the drain of the third MOS tube is connected with the first connection end of the first switch, the first connection end of the first capacitor, the drain of the fifth MOS tube and the first connection end of the ninth switch, and the connection point is the positive output end OUTP of the high-speed comparator; The gate of the fourth MOS tube is connected with the first connection end of the second switch and the second connection end of the first capacitor, the source and substrate of the fourth MOS tube are connected with the VSS level, the drain of the fourth MOS tube is connected with the first connection end of the sixth switch, the second connection end of the third capacitor, the drain of the sixth MOS tube and the second connection end of the ninth switch, and the connection point is the negative output end OUTN of the high-speed comparator; The gate of the fifth MOS tube is connected with the negative output end OUTN of the high-speed comparator, the source and substrate of the fifth MOS tube are connected with the VDD level, and the drain of the fifth MOS tube is connected with the positive output end OUTP of the high-speed comparator; The gate of the sixth MOS tube is connected with the positive output end OUTP of the high-speed comparator, the source and substrate of the sixth MOS tube are connected with the VDD level, and the drain of the sixth MOS tube is connected with the negative output end OUTN of the high-speed comparator; The ninth switch is a clock control switch, and the closing and opening of the switch are controlled by an external CLK signal; The third MOS tube and the fourth MOS tube are NMOS tubes, and the fifth MOS tube and the sixth MOS tube are PMOS tubes; The pre-buffer circuit comprises a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a tenth switch and an eleventh switch; The gate of the seventh MOS tube is connected with the negative input end VINN of the high-speed comparator, the substrate of the seventh MOS tube is connected with the VSS level, the source of the seventh MOS tube is connected with the source of the eighth MOS tube and the drain of the ninth MOS tube, and the drain of the seventh MOS tube is connected with the source of the tenth MOS tube and the first connection end of the eleventh switch; The gate of the eighth MOS tube is connected with the positive input end VINP of the high-speed comparator, the substrate of the eighth MOS tube is connected with the VSS level, and the drain of the eighth MOS tube is connected with the source of the eleventh MOS tube and the first connection end of the tenth switch; The second connection end of the tenth switch is connected with the gate of the third MOS tube in the data latch circuit with the speed adjustment function; The second connection end of the eleventh switch is connected with the gate of the fourth MOS tube in the data latch circuit with the speed adjustment function. The gate of the ninth MOS is connected with a third bias voltage, and the substrate and the source of the ninth MOS are connected with a VSS level; The gate, the drain and the substrate of the tenth MOS are connected with a VDD level; The gate, the drain and the substrate of the eleventh MOS are connected with a VDD level; The tenth switch and the eleventh switch are clock control switches, and the closing and opening of the switches are controlled by an external CLK signal; The seventh MOS, the eighth MOS, the ninth MOS, the tenth MOS and the eleventh MOS are all NMOS.

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