Reset circuit, reset signal generation method and chip

Abstract

The present application proposes a reset circuit, a reset signal generating method and a chip, wherein the reset circuit includes a first signal generating module, a second signal generating module and a signal output module. The first signal generating module is used to receive a detection signal and generate a first signal based on the detection signal. The second signal generating module is electrically connected to the first signal generating module, and the second signal generating module is used to receive and generate a second signal based on the detection signal and the first signal. The signal output module is electrically connected to the second signal generating module and the first signal generating module, so as to receive and output a reset signal based on the first signal and the second signal. In this way, the circuit structure of the reset circuit proposed in the present application is relatively simple, the area occupied is small, and the operating voltage and quiescent current of the reset circuit can be reduced during operation.

Description

Technical Field

[0001] The present application relates to the field of reset technology, and in particular to a reset circuit, a reset signal generating method, and a chip. Background Art

[0002] Most main control chip circuits of electronic products in the prior art are equipped with a reset circuit, which is a circuit used to generate a reset signal to restore other related circuits to an initial state. The reset circuit in the prior art includes a reset circuit with a voltage regulator, which has a complex circuit structure and occupies a large area. In addition, the operating voltage required and the quiescent current consumed by the reset circuit during operation are high. Summary of the Invention

[0003] In view of this, the present application proposes a reset circuit, a reset signal generating method and a chip to solve the above problems.

[0004] The present application proposes a reset circuit, which includes: a first signal generating module, the first signal generating module is used to receive a detection signal and generate a first signal based on the detection signal. A second signal generating module, the second signal generating module is electrically connected to the first signal generating module, the second signal generating module is used to receive the detection signal and the first signal, and generate a second signal based on the detection signal and the first signal. And a signal output module, the signal output module is electrically connected to the second signal generating module and the first signal generating module, the signal output module is used to receive the first signal and the second signal, and output a reset signal based on the first signal and the second signal. When the voltage of the detection signal is less than the reference voltage, the level of the reset signal is a first level. When the voltage of the detection signal is greater than the reference voltage, the level of the reset signal is a second level opposite to the first level.

[0005] Furthermore, the first signal generation module includes a first switching transistor and a second switching transistor. The first end of the first switching transistor is connected to a voltage source, and the second end of the first switching transistor, the third end of the first switching transistor, and the first end of the second switching transistor are connected to a first node. The second end of the second switching transistor is used to receive the detection signal, and the third end of the second switching transistor is grounded. The second switching transistor is an NMOS transistor, and the first switching transistor is a depletion-mode NMOS transistor. The first signal generation module is connected to the signal output module and the second signal generation module via the first node to output the first signal to the signal output module and the second signal generation module via the first node.

[0006] Further, the reference voltage is the voltage of the first node when the detection signal is the same as the first signal.

[0007] Furthermore, the first signal generation module includes N first switching transistors and second switching transistors, where N is a positive integer; the N first switching transistors and the N second switching transistors are sequentially connected between a voltage source and ground, wherein the third end of each first switching transistor is connected to the first end of an adjacent first switching transistor, the second end of each first switching transistor is connected to the second end of an adjacent first switching transistor, the first end of the first first switching transistor is connected to the voltage source, the second end of the Nth first switching transistor, the third end of the Nth first switching transistor, and the first end of the second switching transistor are connected to a first node, the second end of the second switching transistor is used to receive a detection signal, and the third end of the second switching transistor is grounded; wherein the second switching transistor is an NMOS transistor, and the first switching transistor is a depletion-mode NMOS transistor. The first signal generation module is connected to the signal output module and the second signal generation module via the first node.

[0008] Furthermore, the second signal generation module includes a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, and a seventh switching transistor. The first end of the third switching transistor is connected to the first end of the fourth switching transistor and is also connected to a voltage source. The second end of the third switching transistor, the third end of the third switching transistor, and the second end of the fourth switching transistor are connected to a second node. The third end of the third switching transistor is connected to the first end of the fifth switching transistor, and the second end of the fifth switching transistor is connected to the first node of the first signal generation module to receive the first signal. The third end of the fifth switching transistor is connected to the third end of the sixth switching transistor. The third end of the fourth switching transistor is connected to the first end of the sixth switching transistor, and the second end of the sixth switching transistor is used to receive the detection signal. The third end of the fourth switching transistor and the first end of the sixth switching transistor are connected to a third node. The second signal generation module is connected to the signal output module via the third node. The third end of the fifth switching transistor, the third end of the sixth switching transistor, and the first end of the seventh switching transistor are connected to a fourth node. The second end of the seventh switching transistor and the third end of the seventh switching transistor are grounded. The third and fourth switching transistors are PMOS transistors, the fifth and sixth switching transistors are NMOS transistors, and the seventh switching transistor is a depletion-mode NMOS transistor.

[0009] Furthermore, the signal output module includes an eighth switching tube and a ninth switching tube, the first end of the eighth switching tube is connected to the voltage source, the second end of the eighth switching tube is connected to the third node of the second signal generating module to receive the second signal; the third end of the eighth switching tube is connected to the first end of the ninth switching tube; the second end of the ninth switching tube is connected to the first node of the first signal generating module to receive the first signal; the third end of the ninth switching tube is grounded; the third end of the eighth switching tube and the first end of the ninth switching tube are connected to the fifth node, and the signal output module outputs a reset signal through the fifth node.

[0010] Furthermore, when the voltage of the detection signal is less than the reference voltage, the second and sixth switches are turned off, the voltage at the first node is pulled high, and the voltage of the first signal is at a high level. When the voltage of the first signal is at a high level, the fifth switch is turned on, the voltage at the second node is pulled low, the third and fourth switches are turned on, and the seventh switch is turned on; the third, fifth, and seventh switches form a conductive branch. When the sixth switch is turned off, the voltage of the second signal is at a high level, the eighth switch is turned off, and the ninth switch is turned on, pulling the voltage at the fifth node low, so that the level of the reset signal is the first level.

[0011] Furthermore, when the voltage of the detection signal is greater than the reference voltage, the second and sixth switches are turned on, the voltage at the first node is pulled down, and the voltage of the first signal is at a low level; wherein the first and second switches form a conductive branch. When the voltage of the first signal is at a low level, the fifth switch is turned off, the voltage at the second node is pulled up, and the third and fourth switches are both turned off. When the sixth switch is turned on, the voltage at the third node is pulled down, the voltage of the second signal is at a low level, the eighth switch is turned on, and the ninth switch is turned off, the voltage at the fifth node is pulled up, so that the level of the reset signal is at the second level.

[0012] The present application also proposes a reset signal generation method, the method comprising: receiving a detection signal, wherein the detection signal is received using a bias module and a comparator module. Based on the detection signal, a first signal is generated using the bias module. Based on the first signal and the detection signal, a second signal is generated using the comparator module. Based on the first signal and the second signal, a corresponding reset signal is generated using a buffer module. When the voltage of the detection signal is less than a reference voltage, the level of the reset signal is a first level. When the voltage of the detection signal is greater than the reference voltage, the level of the reset signal is a second level opposite to the first level.

[0013] Furthermore, the reset signal generating method further includes: generating a first signal by a bias module, wherein the bias module includes a depletion-type NMOS transistor.

[0014] The present application also proposes a chip, which includes a detection pin, a reset signal output pin and a reset circuit, wherein the reset circuit is electrically connected to the detection pin and the signal output pin, the reset circuit receives a detection signal through the detection pin, and outputs a reset signal through the reset signal output pin.

[0015] The reset circuit proposed in the present application includes a first signal generating module, a second signal generating module, and a signal output module. The first signal generating module adjusts the state of the first signal input to the second signal generating module and the signal output module based on the voltage of the detection signal, thereby adjusting the second signal output by the second signal generating module, thereby adjusting the reset signal output by the signal output module. Thus, the reset circuit proposed in the present application can generate an internal bias signal based on the detection signal to adjust the voltage of the output signal, eliminating the need for an additional voltage regulator. This makes the circuit structure of the reset circuit simpler, occupies a smaller area, and reduces the operating voltage and quiescent current required for its operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a circuit block diagram of a reset circuit proposed in one embodiment of the present application;

[0017] Figure 2 is a circuit diagram of a reset circuit proposed in one embodiment of the present application;

[0018] Figure 3 Based on Figure 2 An equivalent circuit diagram for generating a reference voltage adjusted by the first signal generating module shown;

[0019] Figure 4 is a waveform diagram of a signal generated by the reset circuit proposed in an embodiment of the present application;

[0020] Figure 5 is a circuit diagram of a reset circuit proposed in another embodiment of the present application;

[0021] Figure 6 Schematic diagram of the structure of the chip proposed in the embodiment of the present application;

[0022] Figure 7 This is a flowchart of the reset signal generation method proposed in an embodiment of the present application.

[0023] Description of main component symbols

[0024] Reset circuits 100, 100a

[0025] Voltage source VDD

[0026] First signal generating module 10, 10a

[0027] The first switch tube M1

[0028] The first regulating switch tube M11

[0029] The second regulating switch tube M12

[0030] The second switch tube M2

[0031] The first node N1

[0032] The second node N2

[0033] Second signal generating module 20, 20a

[0034] The third switch tube M3

[0035] The fourth switch tube M4

[0036] The fifth switch tube M5

[0037] The sixth switch tube M6

[0038] Seventh switch tube M7

[0039] The third node N3

[0040] Fourth node N4

[0041] Fifth node N5

[0042] Sixth node N6

[0043] Signal output modules 30, 30a

[0044] The eighth switch tube M8

[0045] Ninth switch tube M9

[0046] Seventh node N7

[0047] Chip 1

[0048] Detection pin PIN1

[0049] Signal output pin PIN2

[0050] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0053] The terms "first" and "second," etc., in the specification of this application and the accompanying drawings are used to distinguish between different objects, not to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to the process, method, product, or apparatus.

[0054] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0055] See also Figure 1 , is a circuit block diagram of the reset circuit 100 proposed in an embodiment of the present application. The reset circuit 100 includes a first signal generating module 10, a second signal generating module 20 and a signal output module 30. Specifically, the first signal generating module 10 is connected to the second signal generating module 20 and the signal output module 30. The first signal generating module 10 is used to receive a detection signal and generate a first signal based on the received detection signal. The first signal generating module 10 is also used to transmit the first signal to the second signal generating module 20 and the signal output module 30. The second signal generating module 20 is connected to the signal output module 30. The second signal generating module 20 is used to receive the first signal and the detection signal, and generate a second signal by comparing the first signal and the detection signal. The signal output module 30 is used to receive the first signal and the second signal to output a reset signal based on the first signal and the second signal.

[0056] Please also refer to Figure 2 , which is a circuit diagram of the reset circuit 100 proposed in an embodiment of the present application.

[0057] Among them, the first signal generating module 10 includes a first switching tube M1 and a second switching tube M2. Specifically, the first end of the first switching tube M1 is connected to the voltage source VDD to receive the voltage transmitted by the voltage source VDD, wherein the voltage output by the voltage source VDD can range from 1 to 5.5 volts (V). The second end of the first switching tube M1 is connected to the third end of the first switching tube M1. The third end of the first switching tube M1 and the first end of the second switching tube M2 are connected to the first node N1. The second end of the second switching tube M2 is used to receive the detection signal; the third end of the second switching tube M2 is grounded. In an embodiment of the present application, the first signal generating module 10 is connected to the signal output module 30 and the second signal generating module 20 through the first node N1 to output the first signal to the signal output module 30 and the second signal generating module 20 through the first node N1.

[0058] In some embodiments, the first signal generating module 10 can be replaced by a bias module or any module that can generate a first signal.

[0059] The second signal generating module 20 includes a third switch M3 and a fourth switch M4. Specifically, a first terminal of the third switch M3 is connected to a first terminal of the fourth switch M4, and both terminals are connected to a voltage source VDD to receive a voltage transmitted by the voltage source VDD. A second terminal of the third switch M3, a third terminal of the third switch M3, and a second terminal of the fourth switch M4 are connected to a second node N2.

[0060] The second signal generating module 20 also includes a fifth switch transistor M5 and a sixth switch transistor M6. Specifically, a first end of the fifth switch transistor M5 is connected to a second node N2; a second end of the fifth switch transistor M5 is connected to a first node N1 to receive the first signal. A first end of the sixth switch transistor M6 and a third end of the fourth switch transistor M4 are connected to a third node N3; a second end of the sixth switch transistor M6 is used to receive a detection signal; a third end of the sixth switch transistor M6 and a third end of the fifth switch transistor M5 are connected to a fourth node N4. The second signal generating module 20 is connected to the signal output module 30 via a third node N3 and transmits the second signal to the signal output module 30 via the third node N3.

[0061] The second signal generating module 20 further includes a seventh switch transistor M7 . Specifically, a first terminal of the seventh switch transistor M7 is connected to the fourth node N4 , and a second terminal and a third terminal of the seventh switch transistor M7 are grounded.

[0062] In some embodiments, the second signal generating module 20 can be replaced by a comparator module or any module that can generate a second signal.

[0063] The signal output module 30 includes an eighth switch transistor M8 and a ninth switch transistor M9. Specifically, a first terminal of the eighth switch transistor M8 is connected to a voltage source VDD to receive a voltage transmitted by the voltage source VDD. A second terminal of the eighth switch transistor M8 is connected to a third node N3 to receive a second signal. A third terminal of the eighth switch transistor M8 and a first terminal of the ninth switch transistor M9 are connected to a fifth node N5. A second terminal of the ninth switch transistor M9 is connected to a first node N1 to receive a first signal. A third terminal of the ninth switch transistor M9 is grounded. The signal output module 30 outputs a reset signal through the fifth node N5.

[0064] In some embodiments, the signal output module 30 may be a buffer module or any module that can generate a reset signal.

[0065] In some embodiments, the first switch transistor M1, the second switch transistor M2, the fifth switch transistor M5, the sixth switch transistor M6, the seventh switch transistor M7, and the ninth switch transistor M9 may be NMOS (N-channel Metal Oxide Semiconductor) transistors. Thus, the first terminals of the first switch transistor M1, the second switch transistor M2, the fifth switch transistor M5, the sixth switch transistor M6, the seventh switch transistor M7, and the ninth switch transistor M9 serve as drain terminals of the NMOS transistors. The second terminals of the first switch transistor M1, the second switch transistor M2, the fifth switch transistor M5, the sixth switch transistor M6, the seventh switch transistor M7, and the ninth switch transistor M9 serve as gate terminals of the NMOS transistors. The third terminals of the first switch transistor M1, the second switch transistor M2, the fifth switch transistor M5, the sixth switch transistor M6, the seventh switch transistor M7, and the ninth switch transistor M9 serve as sources of the NMOS transistors. The first switch transistor M1 and the seventh switch transistor M7 may be depletion mode NMOS transistors.

[0066] In some embodiments, the third switch transistor M3, the fourth switch transistor M4, and the eighth switch transistor M8 may be PMOS (P-channel Metal Oxide Semiconductor) transistors. Thus, the first terminals of the third switch transistor M3, the fourth switch transistor M4, and the eighth switch transistor M8 serve as the source terminals of the PMOS transistors. The second terminals of the third switch transistor M3, the fourth switch transistor M4, and the eighth switch transistor M8 serve as the gate terminals of the PMOS transistors. The third terminals of the third switch transistor M3, the fourth switch transistor M4, and the eighth switch transistor M8 serve as the drain terminals of the PMOS transistors.

[0067] In some embodiments, the reference voltage is the voltage of the first node N1 when the detection signal is the same as the first signal. Figure 3 , Figure 3 This is an equivalent circuit for generating a reference voltage adjusted based on the first signal generating module 10, wherein the second terminal of the second switch M2 in the first signal generating module 10 is connected to the first node N1. It can be understood that in this scenario, the first current I1 flowing through the first switch M1 is equal to the second current I2 flowing through the second switch M2. Specifically, the first current I1 and the second current I2 are obtained using the following formula:

[0068]

[0069]

[0070] Among them, μ n C ox is the parameter of MOS tube, is the width-to-length ratio of the first switch tube M1, V GS1 V is the voltage difference between the voltage at the second terminal of the first switch tube M1 and the voltage at the third terminal.TH1 is the threshold voltage of the first switch tube M1. is the width-to-length ratio of the second switch tube M2, V GS2 The voltage difference between the voltage at the second terminal of the second switch tube M2 and the voltage at the third terminal is V TH2 is the threshold voltage of the second switch tube M2, V REF for Figure 3 The reference voltage at the first node N1 in .

[0071] Since I1=I2, the method for obtaining the reference voltage is as follows:

[0072]

[0073] So, it can be understood that the application Figure 2 In the circuit of the first signal generating module 10 shown in FIG. 1 , V REF is the transition voltage of the second switch tube M2 when it is turned on or off. Specifically, when the voltage of the detection signal received by the second end of the second switch tube M2 is greater than V REF When the voltage of the detection signal received by the second end of the second switch tube M2 is less than V REF When the second switch tube M2 is turned off, the first signal generating module 10 generates V by the first switch tube M1. REF Among them, the first switch tube M1 is a depletion-type NMOS tube, which has a simple circuit structure, occupies a small area, and thus has a low cost.

[0074] Please refer again Figure 2 It is understandable that the working principle of the reset circuit 100 provided in this application after power-on is as follows:

[0075] When the voltage of the detection signal is less than the reference voltage, the second switch M2 is turned off, thereby increasing the voltage at the first node N1, causing the voltage of the first signal at the first node N1 to be high (for example, when the output voltage of the voltage source VDD is 1 volt (V), the voltage of the first signal is 0.99V). Understandably, when the voltage of the first signal output from the first node N1 to the fifth switch M5 is high, the fifth switch M5 is turned on. When the fifth switch M5 is turned on, the voltage at the second node N2 is lowered, thereby turning on the third and fourth switches M3 and M4. This turns on the seventh switch M7, forming a circuit between the third, fifth, and seventh switches M3 and M5. Because the detection signal is less than the reference voltage, the sixth switch M6 is turned off. Because the sixth switch tube M6 is turned off, the voltage at the third node N3 is pulled up, so that the voltage of the second signal output from the third node N3 is high (for example, when the output voltage of the voltage source VDD is 1V, the voltage of the second signal is 0.99V). The eighth switch tube M8 is turned off, and the ninth switch tube M9 is turned on, so that the voltage at the fifth node N5 is pulled down, so that the level of the reset signal output from the fifth node N5 is the first level, for example, a low level (for example, when the output voltage of the voltage source VDD is 1V, the level of the reset signal is 51.97 nanovolts (nV)).

[0076] In this case, only the third switch M3, the fifth switch M5, and the seventh switch M7 in the reset circuit 100 form a conductive branch. Furthermore, when the voltage of the detection signal is lower than the reference voltage, the minimum operating voltage of the reset circuit 100 is only the sum of the voltages of the third switch M3, the fifth switch M5, and the seventh switch M7 (for example, V GS_M3 +V DS_M5 +V DS_M7 ), that is, the voltage output by the voltage source VDD can be the sum of the operating voltages of the third switch M3, the fifth switch M5, and the seventh switch M7. Thus, the first signal generating module 10 and the second signal generating module 20 can operate at a lower operating voltage (e.g., 1V).

[0077] When the voltage of the detection signal is greater than the reference voltage, the second switch M2 is turned on, thereby pulling down the voltage at the first node N1, causing the voltage of the first signal at the first node N1 to be low (for example, when the voltage output by the voltage source VDD is 1V, the voltage of the first signal is 17.83 millivolts (mV)). Understandably, the low voltage of the first signal at the first node N1 causes the fifth switch M5 to be turned off. Furthermore, because the detection signal is greater than the reference voltage, the sixth switch M6 is turned on. Since the fifth switch M5 is turned off, the voltage at the second node N2 is pulled up, causing the third and fourth switches M3 and M4 to be turned off. Since the sixth switch tube M6 is turned on, the voltage at the third node N3 is pulled down, so that the voltage of the second signal output by the third node N3 is low (for example, when the voltage output by the voltage source VDD is 1V, the voltage of the second signal is 553.18 microvolts (μV)), and the eighth switch tube M8 is turned on and the ninth switch tube M9 is turned off, so that the voltage at the fifth node N5 is pulled up, so that the level of the reset signal output by the fifth node N5 is the second level, for example, a high level (for example, when the output voltage of the voltage source VDD is 1V, the level of the reset signal is 0.99V).

[0078] In this case, only the first switch M1 and the second switch M2 form a conductive branch in the reset circuit 100. Furthermore, when the voltage of the detection signal is greater than the reference voltage, the minimum operating voltage of the reset circuit 100 is only the sum of the voltages of the first switch M1 and the second switch M2 (for example, V DS_M1 +V DS_M2 ), that is, the voltage output by the voltage source VDD can be the sum of the operating voltages of the first switch tube M1 and the second switch tube M2 when they are in operation. Therefore, the first signal generating module 10 and the second signal generating module 20 can also operate at a lower operating voltage (for example, 1V).

[0079] Therefore, after the reset circuit 100 is powered on, when the voltage of the detection signal is lower than the reference voltage, the lowest operating voltage of the reset circuit 100 during operation is the first operating voltage, i.e., the sum of the operating voltages of the third switch tube M3, the fifth switch tube M5, and the seventh switch tube M7 during operation (e.g., V GS_M3 +V DS_M5 +V DS_M7 When the voltage of the detection signal is greater than the reference voltage, the minimum operating voltage of the reset circuit 100 is the second operating voltage, that is, the sum of the operating voltages of the first switch tube M1 and the second switch tube M2 when they are running (for example, V DS_M1 +V DS_M2 ). It can be understood that in order to ensure stable operation of the reset circuit 100, the larger voltage between the first operating voltage and the second operating voltage should be selected as the lowest operating voltage of the reset circuit 100.

[0080] Please also refer to Figure 4 , Figure 4 Figure 1 shows the waveforms of the various signals and currents in reset circuit 100 when the voltage output by voltage source VDD is 1V and the reference voltage is approximately 0.57V. As can be seen from the figure, when the voltage of the detection signal is less than the reference voltage, the voltage of the first signal is at a high level of approximately 0.99V, the voltage of the second signal is at a high level of approximately 0.99V, and the level of the reset signal is at a low level of approximately 51.97nV. At this time, the quiescent current of reset circuit 100 is approximately 105 nanoamperes (nA). When the voltage of the detection signal is greater than the reference voltage, the voltage of the first signal transitions from a high level to a low level of approximately 17.83mV, the voltage of the second signal is approximately 553.18μV, and the level of the reset signal transitions from a low level to a high level of approximately 0.99V. At this time, the quiescent current of reset circuit 100 is approximately 400nA. Typically, reset circuits used in the prior art (reset circuits with voltage regulators) operate in an operating voltage range of approximately 1.7 to 5.5V, and the quiescent current of the reset circuit is approximately 1.6μA. Obviously, the operating voltage and the quiescent current of the reset circuit 100 proposed in the present application during operation are smaller than the operating voltage and the quiescent current of the reset circuit used in the prior art during operation.

[0081] In some embodiments, the reference voltage can be adjusted by adjusting the number of first switch tubes M1 in the first signal generating module 10. Furthermore, in actual production, the number of first switch tubes M1 can be set according to actual needs.

[0082] In some embodiments, the first signal generating module 10 includes N first switching transistors M1 and N second switching transistors M2, where N is a positive integer. Specifically, the N first switching transistors M1 and the N second switching transistors M2 are sequentially connected between a voltage source VDD and ground, wherein the third terminal of each first switching transistor M1 is connected to the first terminal of an adjacent first switching transistor M1, the second terminal of each first switching transistor M1 is connected to the second terminal of an adjacent first switching transistor M1, the first terminal of the first first switching transistor M1 is connected to the voltage source VDD, the second terminal and the third terminal of the Nth first switching transistor M1 are interconnected, the third terminal of the Nth first switching transistor M1 and the first terminal of the second switching transistor M2 are connected to a first node N1, the second terminal of the second switching transistor M2 is used to receive a detection signal, and the third terminal of the second switching transistor M2 is grounded. The first signal generating module 10 is connected to the signal output module 30 and the second signal generating module 20 via the first node N1.

[0083] For example, see Figure 5, another embodiment of the present application also provides a reset circuit 100a. The circuit structure of the reset circuit 100a is basically the same as the circuit structure of the reset circuit 100, the difference being that the circuit structure of the first signal generating module 10a in the reset circuit 100a is different from the circuit structure of the first signal generating module 10 in the reset circuit 100. Among them, the first signal generating module 10a includes two first switch tubes M1 (for example, a first regulating switch tube M11 and a second regulating switch tube M12) and a second switch tube M2. Among them, the first end of the first regulating switch tube M11 is connected to the voltage source, the second end of the first regulating switch tube M11 is connected to the second end of the second regulating switch tube M12, and the third end of the first regulating switch tube M11 is connected to the first end of the second regulating switch tube M12. The second end and the third end of the second regulating switch tube M12 are connected to the first end of the second switch tube M2. It can be understood that, Figure 5 The reset circuit 100a and Figure 2 The circuit connection mode and working principle of the reset circuit 100 are the same or similar. For details, please refer to Figure 2 , I will not go into details here.

[0084] See Figure 6 , is a schematic diagram of the structure of the chip 1 proposed in an embodiment of the present application. The chip 1 includes a reset circuit 100, a detection pin PIN1, and a reset signal output pin PIN2. Among them, the reset circuit 100 is electrically connected to the detection pin PIN1 and the reset signal output pin PIN2, the reset circuit 100 receives the detection signal through the detection pin PIN1, and the reset circuit 100 outputs the reset signal through the reset signal output pin PIN2. In another embodiment, in addition to the reset circuit 100, the chip 1 may further include a control circuit (not shown), a memory (not shown), and a processor (not shown), and the reset circuit 100 may provide a reset signal to the control circuit, the memory, and / or the processor.

[0085] The reset circuit 100 proposed in the present application is provided with a first signal generating module 10, a second signal generating module 20, and a signal output module 30. The first signal generating module 10 adjusts the state of the first signal input to the second signal generating module 20 and the signal output module 30 according to the voltage of the detected detection signal and the reference voltage, thereby adjusting the second signal output by the second signal generating module 20, thereby adjusting the reset signal output by the signal output module 30. When the first signal output by the first signal generating module 10 to the second signal generating module 20 and the signal output module 30 is in different states, different parts of the circuit in the reset circuit 100 are turned on, thereby reducing the operating voltage and quiescent current of the reset circuit 100 during operation.

[0086] See Figure 7, is a flow chart of a reset signal generating method proposed in an embodiment of the present application. Specifically, the reset signal generating method includes:

[0087] S701: Receive a detection signal, wherein the detection signal is received using a bias module and a comparator module.

[0088] Specifically, the second terminal of the second switch transistor M2 in the first signal generating module 10 is used to receive the detection signal. The second terminal of the sixth switch transistor M6 in the second signal generating module 20 is used to receive the detection signal. In some embodiments, the first signal generating module 10 can be replaced with a bias module, and the second signal generating module 20 can be replaced with a comparator module.

[0089] S702: Generate a first signal using a bias module according to the detection signal.

[0090] Specifically, the first signal generating module 10 is connected to the second signal generating module 20 and the signal output module 30. The first signal generating module 10 is configured to generate a first signal and adjust the state of the first signal based on the received detection signal. The first signal generating module 10 also transmits the first signal to the second signal generating module 20 and the signal output module 30. In some embodiments, the first signal generating module 10 can be replaced with a bias module or any other module capable of generating a first signal.

[0091] S703: Generate a second signal using a comparator module according to the first signal and the detection signal.

[0092] The second signal generating module 20 is connected to the signal output module 30. The second signal generating module 20 is configured to receive the first signal transmitted by the first signal generating module 10 and output a second signal to the signal output module 30 based on the first signal and the detection signal. In some embodiments, the second signal generating module 20 can be replaced by a comparator module or any module capable of generating a second signal.

[0093] S704: Generate a corresponding reset signal using a buffer module according to the first signal and the second signal.

[0094] Specifically, the signal output module 30 is configured to receive the first signal transmitted by the first signal generating module 10 and the second signal transmitted by the second signal generating module 20, and output a reset signal based on the first signal and the second signal. In some embodiments, the signal output module 30 may be a buffer module or any module capable of generating a reset signal.

[0095] When the voltage of the detection signal is less than the reference voltage, the level of the reset signal is a first level, such as a low level (for example, when the output voltage of the voltage source VDD is 1V, the level of the reset signal is 51.97 nanovolts (nV)).

[0096] When the voltage of the detection signal is greater than the reference voltage, the level of the reset signal is a second level, such as a high level (for example, when the output voltage of the voltage source VDD is 1V, the level of the reset signal is 0.99V).

[0097] Those skilled in the art should recognize that the above embodiments are merely intended to illustrate the present application and are not intended to limit the present application. As long as they are within the spirit of the present application, appropriate changes and modifications to the above embodiments should fall within the scope of protection claimed in the present application.

Claims

1. A reset circuit, characterized in that: The reset circuit comprises: a first signal generating module, configured to receive a detection signal and generate a first signal according to the detection signal; a second signal generating module, the second signal generating module being electrically connected to the first signal generating module, the second signal generating module being configured to receive the detection signal and the first signal, and generate a second signal according to the detection signal and the first signal; and a signal output module, the signal output module being electrically connected to the second signal generating module and the first signal generating module, the signal output module being configured to receive the first signal and the second signal, and output a reset signal according to the first signal and the second signal; When the voltage of the detection signal is lower than the reference voltage, the level of the reset signal is a first level; When the voltage of the detection signal is greater than the reference voltage, the level of the reset signal is a second level opposite to the first level; The first signal generating module includes a first switching transistor and a second switching transistor, wherein the first terminal of the first switching transistor is connected to a voltage source, and the second terminal of the first switching transistor, the third terminal of the first switching transistor, and the first terminal of the second switching transistor are connected to a first node; the second terminal of the second switching transistor is used to receive the detection signal, and the third terminal of the second switching transistor is grounded; wherein the second switching transistor is an NMOS transistor, and the first switching transistor is a depletion-mode NMOS transistor; The first signal generating module is connected to the signal output module and the second signal generating module through the first node, so as to output the first signal to the signal output module and the second signal generating module through the first node.

2. The reset circuit according to claim 1, wherein: The reference voltage is a voltage of the first node when the detection signal is the same as the first signal.

3. The reset circuit according to claim 1, wherein: The first signal generating module includes N first switching transistors and second switching transistors, where N is a positive integer; the N first switching transistors and the N second switching transistors are sequentially connected between a voltage source and ground, wherein the third end of each first switching transistor is connected to the first end of an adjacent first switching transistor, and the second end of each first switching transistor is connected to the second end of an adjacent first switching transistor; the first end of the first first switching transistor is connected to the voltage source, the second end of the Nth first switching transistor, the third end of the Nth first switching transistor, and the first end of the second switching transistor are connected to a first node; the second end of the second switching transistor is used to receive the detection signal, and the third end of the second switching transistor is grounded; wherein the second switching transistor is an NMOS transistor, and the first switching transistor is a depletion-type NMOS transistor; The first signal generating module is connected to the signal output module and the second signal generating module through the first node.

4. The reset circuit according to claim 1, wherein: The second signal generating module includes a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube and a seventh switching tube; The first end of the third switch tube is connected to the first end of the fourth switch tube, and both are connected to the voltage source, and the second end of the third switch tube, the third end of the third switch tube, and the second end of the fourth switch tube are connected to a second node; The third terminal of the third switch tube is connected to the first terminal of the fifth switch tube, the second terminal of the fifth switch tube is connected to the first node of the first signal generating module to receive the first signal, and the third terminal of the fifth switch tube is connected to the third terminal of the sixth switch tube; The third end of the fourth switch tube is connected to the first end of the sixth switch tube, and the second end of the sixth switch tube is used to receive the detection signal; the third end of the fourth switch tube and the first end of the sixth switch tube are connected to a third node, and the second signal generating module is connected to the signal output module through the third node; The third end of the fifth switch tube, the third end of the sixth switch tube, and the first end of the seventh switch tube are connected to a fourth node, and the second end of the seventh switch tube and the third end of the seventh switch tube are grounded; The third switch tube and the fourth switch tube are PMOS tubes, the fifth switch tube and the sixth switch tube are NMOS tubes, and the seventh switch tube is a depletion-type NMOS tube.

5. The reset circuit according to claim 4, wherein: The signal output module includes an eighth switching tube and a ninth switching tube. The first end of the eighth switching tube is connected to the voltage source, and the second end of the eighth switching tube is connected to the third node of the second signal generating module to receive the second signal; the third end of the eighth switching tube is connected to the first end of the ninth switching tube; the second end of the ninth switching tube is connected to the first node of the first signal generating module to receive the first signal; the third end of the ninth switching tube is grounded; the third end of the eighth switching tube and the first end of the ninth switching tube are connected to a fifth node, and the signal output module outputs the reset signal through the fifth node.

6. The reset circuit according to claim 5, wherein: When the voltage of the detection signal is lower than the reference voltage, the second switch tube and the sixth switch tube are turned off, the voltage at the first node is pulled up, and the voltage of the first signal is at a high level; When the voltage of the first signal is at a high level, the fifth switch is turned on, the voltage at the second node is pulled down, the third and fourth switches are turned on, and the seventh switch is turned on; wherein the third, fifth, and seventh switches form a conducting branch. When the sixth switch tube is turned off, the voltage of the second signal is high, the eighth switch tube is turned off, the ninth switch tube is turned on, and the voltage at the fifth node is pulled low, so that the level of the reset signal is the first level.

7. The reset circuit according to claim 5, wherein: When the voltage of the detection signal is greater than the reference voltage, the second switch tube and the sixth switch tube are turned on, the voltage at the first node is pulled down, and the voltage of the first signal is at a low level; wherein the first switch tube and the second switch tube form a conducting branch; When the voltage of the first signal is at a low level, the fifth switch is turned off, the voltage at the second node is pulled high, and the third switch and the fourth switch are both turned off; When the sixth switch tube is turned on, the voltage at the third node is pulled low, and the voltage of the second signal is at a low level. The eighth switch tube is turned on, and the ninth switch tube is turned off. The voltage at the fifth node is pulled high, so that the level of the reset signal is the second level.

8. A chip, characterized in that: The chip includes a detection pin, a reset signal output pin and a reset circuit according to any one of claims 1 to 7, wherein the reset circuit is electrically connected to the detection pin and the signal output pin, the reset circuit receives the detection signal through the detection pin, and outputs the reset signal through the reset signal output pin.

Images