A memristor 555 timer circuit
By designing a memristor 555 timer circuit with a memristor SR latch as its core and combining it with CMOS transistors, the problems of large circuit area and numerous components in traditional 555 timer circuits are solved, achieving circuit simplification and low power consumption design, and significantly reducing the circuit area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU DIANZI UNIV
- Filing Date
- 2023-03-28
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional 555 timer circuits have a large area and a large number of components, making it difficult to simplify the circuit and achieve low-power design.
Using a memristor SR latch as the core and combining it with CMOS transistors, a memristor 555 timer circuit is designed, including a voltage divider module, a comparator module, a control module, and an output module. The non-volatile and bipolar threshold characteristics of the memristor are used to realize signal storage and logic operations.
It achieves a simple circuit structure, low power consumption, and a significantly reduced circuit area, which has significant advantages over the traditional 555 timer.
Smart Images
Figure CN116346104B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of circuit design technology, specifically relating to a 555 timer circuit constructed using a memristor SR latch structure as its core. Background Technology
[0002] Memristors have been developed for many years since their introduction in 1971. Circuits implemented with memristors can also perform in-memory computing functions and are considered a strong contender to replace silicon-based chips. As a novel nanodevice, memristors have received widespread attention in many fields, especially in digital logic circuits, due to their advantages such as low power consumption, non-volatility, and switching threshold characteristics. Latches typically perform various logic functions under a stable power supply, and data is lost when power is off. If data needs to be stored, it must be stored in other memory units before power is turned off. However, because memristors are non-volatile devices, they can simultaneously perform logic operations and data storage functions, making them very suitable for the design of novel latch circuits. Moreover, since memristors are perfectly compatible with CMOS, the design of memristor-CMOS hybrid circuits is also a popular research direction. Summary of the Invention
[0003] To address the issues of large circuit area and numerous components in traditional 555 timers, this invention aims to design a memristor SR latch using memristors and CMOS transistors. A memristor 555 timer is then constructed using this latch as its core, resulting in a simpler circuit structure and contributing significantly to the research of CMOS-memristor hybrid circuits.
[0004] This invention provides a memristor 555 timer circuit, comprising: a voltage divider module, a comparator module, a control module, an output module, and a memristor SR latch module;
[0005] The voltage divider module is connected to the comparator module;
[0006] The comparison module is connected to the memristor SR latch module;
[0007] The comparison module is connected to the control module;
[0008] The memristor SR latch module is connected to the control module;
[0009] The control module is connected to the output module;
[0010] The memristor SR latch module includes a fourth memristor M4, a fifth memristor M5, a first analog voltage comparator C1, a second analog voltage comparator C2, a first DC voltage V1, a second DC voltage V2, a third inverter N3, a second memristor OR logic unit G2, a first NMOS transistor T1, a second NMOS transistor T2, a third NMOS transistor T3, a fourth NMOS transistor T4, and a first PMOS transistor T5.
[0011] The first input terminal of the second memristor OR logic unit G2 is connected to the gate of the first NMOS transistor T1, serving as the input terminal V of the memristor SR latch module. S ;
[0012] The second input terminal of the second memristor OR logic unit G2 is connected to the gate of the second NMOS transistor T2, serving as the input terminal V of the memristor SR latch module. R ;
[0013] The source of the first pmos transistor T5 is connected to the first DC voltage V1, the drain of the first pmos transistor T5 is connected to the output terminal of the third inverter N3, and the drain of the first pmos transistor T5 is connected to the inverting input terminal of the fourth memristor M4.
[0014] The input terminal of the third inverter N3 is connected to the drain of the fourth nmos transistor T4;
[0015] The positive input terminal of the fourth memristor M4 is connected to the positive input terminal of the fifth memristor M5. The positive input terminal of the fourth memristor M4 is connected to the source of the third NMOS transistor T3. The positive input terminal of the fourth memristor M4 serves as the output terminal V of the memristor SR latch module. SR ;
[0016] The drain of the third NMOS transistor T3 is connected to the source of the first NMOS transistor T1, and the drain of the third NMOS transistor T3 is connected to the drain of the second NMOS transistor T2; the source of the second NMOS transistor T2 is grounded.
[0017] The drain of the first NMOS transistor T1 is connected to the second DC voltage V2;
[0018] The inverting input terminal of the fifth memristor M5 is grounded.
[0019] Preferably, the voltage divider module includes: a first memristor M1, a second memristor M2, a third memristor M3, and a third DC voltage V. cc ;
[0020] The positive input terminal of the first memristor M1 is connected to the third DC voltage V. cc;
[0021] The inverting input terminal of the first memristor M1 is connected to the non-inverting input terminal of the second memristor M2, and the inverting input terminal of the first memristor M1 serves as the output terminal V of the voltage divider module. M1 ;
[0022] The inverting input terminal of the second memristor M2 is connected to the non-inverting input terminal of the third memristor M3, and the inverting input terminal of the second memristor M2 serves as the output terminal V of the voltage divider module. M2 ;
[0023] The inverting input terminal of the third memristor M3 is grounded.
[0024] Preferably, the comparison module includes: a threshold voltage input terminal IN1, a trigger input terminal IN2, a first analog voltage comparator C1, and a second analog voltage comparator C2;
[0025] The positive input of the first analog voltage comparator C1 is connected to the threshold voltage input IN1, and the output of the first analog voltage comparator C1 is connected to the input V of the memristor SR latch module. R The inverting input of the first analog voltage comparator C1 is connected to the output V of the voltage divider module. M1
[0026] The inverting input of the second analog voltage comparator C2 is connected to the threshold voltage input IN2, and the non-inverting input of the second analog voltage comparator C2 is connected to the output V of the voltage divider module. M2 The output of the second analog voltage comparator C2 serves as the output V of the comparison module. S0 .
[0027] Preferably, the control module includes:
[0028] The trigger reset terminal RESET, the first inverter N1, the fourth inverter N4, the first memristor OR logic unit G1, and the third memristor OR logic unit G3;
[0029] The input terminal of the first inverter N1 is connected to the RESET terminal of the flip-flop, the output terminal of the first inverter N1 is connected to the second input terminal of the first memristor or logic unit G1, and the output terminal of the first inverter N1 is connected to the second input terminal of the third memristor or logic unit G3.
[0030] The output of the first memristor OR logic unit G1 is connected to the input V of the memristor SR latch module. S The first input terminal of the first memristor or logic operation unit G1 is connected to the output terminal V of the comparison module. S0 ;
[0031] The output of the fourth inverter N4 is connected to the first input of the third memristor or logic unit G3;
[0032] The output terminal of the third memristor or logic operation unit G3 serves as the output terminal V of the control module. O2 ;
[0033] The input terminal of the fourth inverter N4 is connected to the output terminal V of the memristor SR latch module. SR .
[0034] Preferably, the output module includes: a second inverter N2, a second PMOS transistor T6, and a discharge terminal DISCH;
[0035] The input terminal of the second inverter N2 is connected to the output terminal V of the control module. O2 ,
[0036] The input terminal of the second inverter N2 is connected to the gate of the second PMOS transistor T6;
[0037] The output terminal of the second inverter N2 serves as the output terminal V of the timer circuit. out ;
[0038] The drain of the second PMOS transistor T6 is connected to the inverting input terminal of the third memristor M3 in the voltage divider module; the drain of the second PMOS transistor T6 is grounded.
[0039] The source of the second PMOS transistor T6 is connected to the discharge terminal DISCH.
[0040] Preferably, the memristor or logic operation unit consists of two memristors;
[0041] The positive input terminals of the two memristors are connected to each other to serve as the output terminal of the memristor OR logic unit;
[0042] The inverting input terminals of the two memristors serve as the first and second input terminals of the memristor or logic operation unit, respectively.
[0043] The beneficial effects of this invention are:
[0044] The memristor of this invention adopts the Biolek threshold memristor model. This invention utilizes the excellent bipolar threshold characteristics and non-volatility of this memristor to design the circuit, using a novel memristor SR latch as the core, and leveraging the non-volatility of the memristor to achieve signal storage. The memristor 555 timer circuit of this invention is implemented entirely using MOS transistors and memristors, resulting in a simple circuit structure, low power consumption, and a significant reduction in overall circuit area compared to traditional 555 timers. Attached Figure Description
[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Some specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings indicate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0046] Figure 1 This is the circuit symbol for the Biolek threshold memristor used in this invention;
[0047] Figure 2 This is a graph showing the current-voltage characteristic of the Biolek threshold memristor used in this invention.
[0048] Figure 3 This is a block diagram of a memristor 555 timer circuit according to the present invention.
[0049] Figure 4 This is a circuit diagram of each functional module of a memristor 555 timer circuit according to the present invention.
[0050] Figure 5 This is an overall circuit diagram of a memristor 555 timer circuit according to the present invention.
[0051] Figure 6 The image shows a PSPICE simulation waveform of a memristor 555 timer circuit according to the present invention. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0053] An embodiment of the present invention provides a memristor 555 timer circuit, including: a first memristor M1, a second memristor M2, a third memristor M3, a fourth memristor M4, a fifth memristor M5, a first analog voltage comparator C1, a second analog voltage comparator C2, a first DC voltage V1, a second DC voltage V2, and a third DC voltage V... ccThe circuit consists of: a first inverter N1, a second inverter N2, a third inverter N3, a fourth inverter N4, a first memristor or logic unit G1, a second memristor or logic unit G2, a third memristor or logic unit G3, a first NMOS transistor T1, a second NMOS transistor T2, a third NMOS transistor T3, a fourth NMOS transistor T4, a first PMOS transistor T5, a second PMOS transistor T6, a threshold voltage input IN1, a trigger input IN2, a trigger reset RESET, a control voltage input CONT, and a discharge terminal DISCH.
[0054] The positive input terminal of the first memristor M1 is connected to the third DC voltage V. cc The inverting input terminal of the first memristor M1 is connected to the control voltage input terminal CONT, the inverting input terminal of the first memristor M1 is connected to the non-inverting input terminal of the second memristor M2, and the inverting input terminal of the first memristor M1 is connected to the inverting input terminal of the first analog voltage comparator C1.
[0055] The inverting input of the second memristor M2 is connected to the non-inverting input of the second analog voltage comparator C2, and the inverting input of the second memristor M2 is connected to the non-inverting input of the third memristor M3.
[0056] The inverting input terminal of the third memristor M3 is grounded, and the inverting input terminal of the third memristor M3 is connected to the drain of the second pmos transistor T6.
[0057] The positive input terminal of the first analog voltage comparator C1 is connected to the threshold voltage input terminal IN1, and the output terminal of the first analog voltage comparator C1 is connected to the first input terminal of the second memristor OR logic unit G2; the output terminal of the first analog voltage comparator C1 is connected to the gate of the second NMOS transistor T2.
[0058] The inverting input of the second analog voltage comparator C2 is connected to the threshold voltage input IN2, and the output of the second analog voltage comparator C2 is connected to the first input of the first memristor or logic unit G1.
[0059] The input terminal of the first inverter N1 is connected to the RESET terminal of the flip-flop, the output terminal of the first inverter N1 is connected to the second input terminal of the first memristor or logic unit G1, and the output terminal of the first inverter N1 is connected to the second input terminal of the third memristor or logic unit G3.
[0060] The output terminal of the first memristor or logic operation unit G1 is connected to the second input terminal of the second memristor or logic operation unit G2, and the output terminal of the first memristor or logic operation unit G1 is connected to the gate of the first nmos transistor T1.
[0061] The output of the second memristor or logic operation unit G2 is connected to the gate of the third nmos transistor T3, the output of the logic operation unit G2 is connected to the gate of the fourth nmos transistor T4, and the output of the logic operation unit G2 is connected to the gate of the first pmoos transistor T5.
[0062] The source of the first pmos transistor T5 is connected to the first DC voltage V1, the drain of the first pmos transistor T5 is connected to the output terminal of the third inverter N3, and the drain of the first pmos transistor T5 is connected to the inverting input terminal of the fourth memristor M4.
[0063] The input terminal of the third inverter N3 is connected to the drain of the fourth nmos transistor T4;
[0064] The positive input terminal of the fourth memristor M4 is connected to the positive input terminal of the fifth memristor M5. The positive input terminal of the fourth memristor M4 is connected to the source of the third NMOS transistor T3. The positive input terminal of the fourth memristor M4 is connected to the source of the fourth NMOS transistor T4. The positive input terminal of the fourth memristor M4 is connected to the input terminal of the fourth inverter N4.
[0065] The drain of the third NMOS transistor T3 is connected to the source of the first NMOS transistor T1, and the drain of the third NMOS transistor T3 is connected to the drain of the second NMOS transistor T2; the source of the second NMOS transistor T2 is grounded.
[0066] The drain of the first NMOS transistor T1 is connected to the second DC voltage V2;
[0067] The inverting input terminal of the fifth memristor M5 is grounded;
[0068] The output of the fourth inverter N4 is connected to the first input of the third memristor or logic unit G3;
[0069] The output terminal of the third memristor or logic operation unit G3 is connected to the gate of the second pmos transistor T6, and the output terminal of the third memristor or logic operation unit G3 is connected to the input terminal of the second inverter N2.
[0070] The output terminal of the second inverter N2 serves as the output terminal V of the timer circuit. out ;
[0071] The source of the second PMOS transistor T6 is connected to the discharge terminal DISCH;
[0072] The present invention will now be described in detail with reference to the accompanying drawings.
[0073] Figure 1 This is the circuit symbol for the Biolk memristor used in this invention. Figure 2 This is the current-voltage characteristic curve of the memristor. Figure 2It can be seen that when the voltage applied across the memristor exceeds the set threshold voltage, V th This is the threshold voltage. Its resistance will change, exhibiting good hysteresis and threshold characteristics. When the voltage applied across the memristor is a positive voltage and greater than its threshold voltage, the memristor resistance changes from its initial value R. ini Change to low resistance R on When the voltage applied across the memristor is a reverse voltage and greater than the threshold voltage, the memristor resistance changes from the initial resistance R. ini Become a high resistance value R off When the voltage applied across the memristor is less than its threshold voltage, the resistance of the memristor does not change.
[0074] Figure 3 This is a block diagram of a memristor 555 timer circuit, consisting of a voltage divider module, a comparator module, a memristor SR latch module, an output module, and a control module.
[0075] The circuits corresponding to each module are as follows: Figure 4 As shown.
[0076] The voltage divider module uses three memristors to regulate the third DC voltage V. cc The voltage divider, the output of this module is V. M1 and V M2 These are respectively used as the inverted input signal of the first analog voltage comparator C1 and the positive input signal of the second analog voltage comparator C2 in the comparison module.
[0077] The comparison module will send in V M1 and V M2 The signal is compared with two input signals IN1 and IN2 respectively. When the voltage at IN1 is higher than V... M1 When the voltage is applied, the output V of the first analog voltage comparator C1 is... R The output is high when the voltage at IN2 is high, and low when the voltage at IN2 is low. M2 When the voltage is constant, the output V of the second analog voltage comparator C2 is... S0 A low level indicates a low voltage level, while a high level indicates a high voltage level.
[0078] The output V of the second analog voltage comparator C2 S0 As an input signal of the control module, it is the inverted signal of RESET. The input is ORed with the first memristor OR logic unit G1, and the output is V. S .
[0079] V R and V S The signal is input to the memristor SR latch module to realize the SR latching function operation, and the output signal is V. SR The signal is inverted and then compared with... The signal is input to the third memristor OR logic unit G3 for OR operation to obtain V. o2 V o2 It is used to control the working state of the second PMOS tube T6 in the output module.
[0080] The memristor SR latch module is the core of this invention. The second DC voltage V2 is set to a value greater than the threshold voltage of the fourth memristor M4 and less than the threshold voltage of the fifth memristor M5; the first DC voltage V1 is set to a value less than the threshold voltage of both the fourth memristor M4 and the fifth memristor M5. The influence of MOSFET voltage drop is ignored. The operation of the memristor SR latch module is as follows:
[0081] 1. When the input signal V S High level, V R When the signal is low: the first NMOS transistor T1 is on, the second NMOS transistor T2 is off, the second memristor OR logic unit G2 outputs a high level, therefore the third NMOS transistor T3 and the fourth NMOS transistor T4 are on, the first PMOS transistor T5 is off, and at this time the memristor SR latch module outputs V. SR A high level signal enables the function of setting the signal to "1".
[0082] 2. When V S The input is low, V R When the input is high: the first NMOS transistor T1 is off, the second NMOS transistor T2 is on, the second memristor OR logic unit G2 outputs a high level, therefore the third NMOS transistor T3 and the fourth NMOS transistor T4 are on, the first PMOS transistor T5 is off, and at this time the memristor SR latch module outputs V. SR When the level is low, the function of setting to "0" is implemented.
[0083] 3. When the input signal V S and V R When all are at low levels, the first NMOS transistor T1 and the second NMOS transistor T2 are off, the output of the second memristor OR logic unit G2 is low, the first NMOS transistor T5 is on, and the third NMOS transistor T3 and the fourth NMOS transistor T4 are both off. The output is mainly determined by the resistance value of the fourth memristor M4. The fourth memristor M4 and the fifth memristor M5 divide the first DC voltage V1. Since the voltage value of V1 is lower than the threshold voltage of M4 and M5, the voltage at point A after voltage division will also be lower than the threshold voltage of the fifth memristor M5, and the resistance value of M5 will not change. Set the initial resistance value R of M5. ini For R on < <R ini < <R off The output voltage V at point A SR As shown in formula (1).
[0084]
[0085] If the memristor SR latch module output was high at the previous moment, and the second memristor OR logic unit G2 output was logic high, then the fourth NMOS transistor T4 is turned on, and the output terminal C of the third inverter N3 is low. That is, the voltage applied across the fourth memristor M4 is a positive voltage greater than its threshold voltage. At this time, the state of the fourth memristor M4 is low resistance R. on When the input signal V S and V R After the voltage level changes to low, the output of the second memristor or logic unit G2 is low, the fifth PMOS transistor T5 is turned on while the fourth NMOS transistor T4 is turned off. Since V1 is a DC voltage lower than the threshold voltage of M4, V1 will not change the state of M4, so M4 remains at R at this moment. on According to formula (1), the output voltage V of the memristor SR latch module is... SR Keep the high level unchanged.
[0086] If the memristor SR latch module output was low at the previous moment, and the second memristor OR logic unit G2 output was logic high, the fourth NMOS transistor T4 was turned on, and point C was at a high level. That is, the voltage applied across the fourth memristor M4 was a reverse voltage greater than its threshold voltage. At this time, M4 was in a high-impedance state. off When the input signal V S and V R After the voltage drops to low, the output of the second memristor or logic unit G2 is low, the first PMOS transistor T5 turns on while the fourth NMOS transistor T4 turns off. Since V1 is a DC voltage lower than the threshold voltage of M4, M4 maintains R at this moment. off The output voltage V remains unchanged. SR It is a low level.
[0087] This process achieves the "hold" function of the latch by changing the state of the memristor.
[0088] 4. V S and V R At the same time, a high level indicates an inhibited state.
[0089] Figure 5 The complete circuit of the 555 timer circuit of the present invention consists of 11 threshold memristors (6 of which form 3 memristor OR logic operation units G1, G2 and G3), 6 MOSFETs, 2 analog voltage comparators and 4 inverters.
[0090] Set the third DC voltage V ccThe voltage is below the threshold voltage of the first memristor M1. M1, M2, and M3 are memristors with identical parameters and the same initial state. Set their initial value R. ini For R on < <R ini < <R off The third DC voltage V cc V obtained after voltage division by the first, second, and third memristors M1, M2, and M3 M1 2 / 3V cc V M2 1 / 3V cc .
[0091] Figure 6 The results are PSPICE simulation results of the memristor 555 timer circuit of this invention.
[0092] When the reset pin RESET is high, then V... out The IN2 pin is at a high level, therefore the V pin controls the voltage. out When the RESET pin is set to a high level, the RESET signal will not affect the state of the 555 timer output. When the RESET pin is set to a low level, the outputs of the first and third memristor OR logic units G1 and G3 are both high, and the output V... out It is at a low level, thus achieving the reset function.
[0093] 1. When the reset pin RESET is high, make the input IN1 greater than 2 / 3V. cc IN2 is greater than 1 / 3V cc Then V R Output high level, V S0 Output low level, V S The output is low, therefore V SR The output is low, V o2 When the output is high, the memristor 555 timer circuit outputs a low level. The simulation results are as follows. Figure 6 As shown in part t1.
[0094] 2. When the reset pin RESET is high, set the input IN1 to be less than 2 / 3V. cc IN2 is less than 1 / 3V cc Then V R Output low level, V S0 Output high level, V S The output is high, therefore V SR The output is high, V o2 When the output is low, the memristor 555 timer circuit outputs a high level. The simulation results are as follows: Figure 6 As shown in part t2.
[0095] 3. When the reset pin RESET is high, set the input IN1 to be less than 2 / 3V. cc IN2 voltage is greater than 1 / 3V cc Then V R Output low level, V S0 Output low level, V S When the output is low, the memristor SR latch module performs a hold function. Simulation results are as follows: Figure 6 As shown in section t3. Since the output of the memristor SR latch module was high at the previous moment, the output of the memristor SR latch module is still high at this moment, and the output of the memristor 555 timer circuit is high.
[0096] 4. When the RESET terminal is low, the output is reset regardless of the values of inputs IN1 and IN2, such as... Figure 6 As shown in section t4.
[0097] Depend on Figure 6 The simulation results show that the circuit can realize the function of the 555 timer and has a simple structure.
[0098] Table 1 is a function table of the enable control terminal and input / output signals of this invention.
[0099] Table 1. Input parameter settings and output status functions of a memristor 555 timer.
[0100]
[0101] (X indicates that the input voltages IN1 and IN2 can be any value)
[0102] Tables 2 and 3 compare the conventional 555 timer with the 555 timer of this invention. The SR latch module, serving as the main module in this invention, is designed using MOS transistors and memristors. Since memristors are nanodevices, they can be directly stacked on CMOS as molecular devices during manufacturing. Although this invention uses 11 memristors, the circuit area is significantly reduced due to the absence of resistive devices. Compared to the SR latch module at the core of the conventional 555 timer circuit, the number of MOS transistors in the SR latch module of this invention is also reduced by 33%.
[0103] Table 2 Comparison of the overall circuit of the 555 timer
[0104]
[0105] Table 3 Comparison of the core SR latch module of the 555 timer circuit
[0106]
[0107] The above description is only a part of the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.
Claims
1. A memristor 555 timer circuit, comprising: The voltage divider module, the comparison module, the control module, and the output module are characterized by further including: a memristor SR latch module; The voltage divider module is connected to the comparator module; The comparison module is connected to the memristor SR latch module; The comparison module is connected to the control module; The memristor SR latch module is connected to the control module; The control module is connected to the output module; The memristor SR latch module includes a fourth memristor M4, a fifth memristor M5, a first analog voltage comparator C1, a second analog voltage comparator C2, a first DC voltage V1, a second DC voltage V2, a third inverter N3, a second memristor OR logic unit G2, a first NMOS transistor T1, a second NMOS transistor T2, a third NMOS transistor T3, a fourth NMOS transistor T4, and a first PMOS transistor T5. The first input terminal of the second memristor OR logic unit G2 is connected to the gate of the first NMOS transistor T1, serving as the input terminal V of the memristor SR latch module. S ; The second input terminal of the second memristor OR logic unit G2 is connected to the gate of the second NMOS transistor T2, serving as the input terminal V of the memristor SR latch module. R ; The source of the first pmos transistor T5 is connected to the first DC voltage V1, the drain of the first pmos transistor T5 is connected to the output terminal of the third inverter N3, and the drain of the first pmos transistor T5 is connected to the inverting input terminal of the fourth memristor M4. The input terminal of the third inverter N3 is connected to the drain of the fourth nmos transistor T4; The positive input terminal of the fourth memristor M4 is connected to the positive input terminal of the fifth memristor M5. The positive input terminal of the fourth memristor M4 is connected to the source of the third NMOS transistor T3. The positive input terminal of the fourth memristor M4 serves as the output terminal V of the memristor SR latch module. SR ; The drain of the third NMOS transistor T3 is connected to the source of the first NMOS transistor T1, and the drain of the third NMOS transistor T3 is connected to the drain of the second NMOS transistor T2; the source of the second NMOS transistor T2 is grounded. The drain of the first NMOS transistor T1 is connected to the second DC voltage V2; The inverting input terminal of the fifth memristor M5 is grounded.
2. The memristor 555 timer circuit as described in claim 1, characterized in that, The voltage divider module includes: a first memristor M1, a second memristor M2, a third memristor M3, and a third DC voltage V. cc ; The positive input terminal of the first memristor M1 is connected to the third DC voltage V. cc ; The inverting input terminal of the first memristor M1 is connected to the non-inverting input terminal of the second memristor M2, and the inverting input terminal of the first memristor M1 serves as the output terminal V of the voltage divider module. M1 ; The inverting input terminal of the second memristor M2 is connected to the non-inverting input terminal of the third memristor M3, and the inverting input terminal of the second memristor M2 serves as the output terminal V of the voltage divider module. M2 ; The inverting input terminal of the third memristor M3 is grounded.
3. The memristor 555 timer circuit as described in claim 2, characterized in that, The comparison module includes: a threshold voltage input terminal IN1, a trigger input terminal IN2, a first analog voltage comparator C1, and a second analog voltage comparator C2; The positive input of the first analog voltage comparator C1 is connected to the threshold voltage input IN1, and the output of the first analog voltage comparator C1 is connected to the input V of the memristor SR latch module. R The inverting input of the first analog voltage comparator C1 is connected to the output V of the voltage divider module. M1 ; The inverting input of the second analog voltage comparator C2 is connected to the threshold voltage input IN2, and the non-inverting input of the second analog voltage comparator C2 is connected to the output V of the voltage divider module. M2 The output of the second analog voltage comparator C2 serves as the output V of the comparison module. S0 .
4. The memristor 555 timer circuit as described in claim 3, characterized in that, The control module includes: The trigger reset terminal RESET, the first inverter N1, the fourth inverter N4, the first memristor OR logic unit G1, and the third memristor OR logic unit G3; The input terminal of the first inverter N1 is connected to the RESET terminal of the flip-flop, the output terminal of the first inverter N1 is connected to the second input terminal of the first memristor or logic unit G1, and the output terminal of the first inverter N1 is connected to the second input terminal of the third memristor or logic unit G3. The output of the first memristor OR logic unit G1 is connected to the input V of the memristor SR latch module. S The first input terminal of the first memristor or logic operation unit G1 is connected to the output terminal V of the comparison module. S0 ; The output of the fourth inverter N4 is connected to the first input of the third memristor or logic unit G3; The output terminal of the third memristor or logic operation unit G3 serves as the output terminal V of the control module. O2 ; The input terminal of the fourth inverter N4 is connected to the output terminal V of the memristor SR latch module. SR .
5. A memristor 555 timer circuit as described in claim 4, characterized in that, The output module includes: a second inverter N2, a second PMOS transistor T6, and a discharge terminal DISCH; The input terminal of the second inverter N2 is connected to the output terminal V of the control module. O2 , The input terminal of the second inverter N2 is connected to the gate of the second PMOS transistor T6; The output terminal of the second inverter N2 serves as the output terminal V of the timer circuit. out ; The drain of the second PMOS transistor T6 is connected to the inverting input terminal of the third memristor M3 in the voltage divider module; the drain of the second PMOS transistor T6 is grounded. The source of the second PMOS transistor T6 is connected to the discharge terminal DISCH.
6. A memristor 555 timer circuit as described in any one of claims 1 to 5, characterized in that, The memristor or logic operation unit consists of two memristors; The positive input terminals of the two memristors are connected to each other to serve as the output terminal of the memristor OR logic unit; The inverting input terminals of the two memristors serve as the first and second input terminals of the memristor or logic operation unit, respectively.