Low dropout regulator and chip

Abstract

The application discloses a low-dropout regulator with high PSRR at high frequency and a chip. The low-dropout regulator comprises a first power transistor, which is a first NMOS tube. The drain of the first NMOS tube is coupled to a power supply end. The source of the first NMOS tube is used for providing an output current to a load. The gate of the first NMOS tube is used for receiving a second feedback voltage. An error amplifier is a common-gate amplifier and is used for generating a first feedback voltage according to an output voltage provided to the load and a reference voltage. A loop gain amplifier is a common-source amplifier and is used for generating the second feedback voltage based on the first feedback voltage. In the low-dropout regulator, the first NMOS tube is used as a power tube, and high PSRR can be achieved at a high frequency band.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to a low dropout voltage regulator and its chip. Background Technology

[0002] A low-dropout regulator (LDO), also known as a low-dropout linear regulator or low-voltage-drop regulator, is a type of linear DC regulator used to provide a stable DC voltage power supply. Compared to a typical linear DC regulator, a low-dropout regulator can operate with a smaller output-input voltage difference.

[0003] In chip design, utilizing on-chip integrated LDOs to power other devices within the chip has become a mainstream design requirement in order to reduce the power supply cost. With the continuous development of integrated circuits, chip design requires LDOs to have performance requirements such as low power consumption, low cost, high power supply rejection ratio (PSRR), and low noise.

[0004] like Figure 1 The LDO with the Cascaded Flipped Voltage Follower (CAS-FVF) structure shown is widely used in chip design because it uses fewer transistors, has high gain, and has advantages such as low power consumption, small area, and low noise.

[0005] However, with increasingly stringent requirements for chip integration, analog front-ends and radio frequency front-ends are being integrated into System-on-Chip (SoC) chips used for wireless communication. Therefore, isolating analog circuitry from power supply noise in digital circuits within SoCs has become a key research focus in SoC chip design. Currently, power supply noise in digital circuits is mainly distributed between 10MHz and 1GHz, and noise suppression in this range remains a bottleneck. However, higher frequency bands... Figure 1 The LDO with the CAS-FVF structure shown deteriorates in its PSRR at high frequencies, making it difficult to effectively suppress digital noise in the 10MHz to 1GHz range. This results in it being unable to meet the noise suppression requirements of SoC chip design. Therefore, there is an urgent need to provide an LDO with a high power supply voltage rejection ratio (High PSRR) at high frequencies. Summary of the Invention

[0006] This application provides a low dropout regulator and chip that can be applied to the high-frequency band. It improves the existing CAS-FVF structure LDO and enhances the PSRR performance of the LDO at high frequencies.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] A first aspect of this application provides a low-dropout regulator, comprising: a first power transistor, which is a first NMOS transistor, the drain of which is coupled to a power supply terminal, the source of which is used to provide an output current to a load, and the gate of which is used to receive a second feedback voltage; an error amplifier, which is a common-gate amplifier, used to generate a first feedback voltage based on the output voltage provided to the load and a reference voltage; and a loop gain amplifier, which is a common-source amplifier, used to generate the second feedback voltage based on the first feedback voltage. In this application, by using a first NMOS transistor as the power transistor, firstly, it can largely isolate the power supply voltage received at the drain of the NMOS transistor from the output voltage at the source of the first NMOS transistor, avoiding the influence of noise from the power supply voltage on the output voltage and improving power supply noise suppression capability; secondly, through the cooperation of the loop gain amplifier and the first power transistor, since the source output of the first NMOS transistor and the input voltage V received at the drain of the first NMOS transistor are... dd Decoupling, power supply voltage V dd The small-signal gain A directly reaches the output voltage via the first power transistor. dd It becomes very small, due to the difference between PSRR and A in high-frequency scenarios. dd It is inversely proportional, thus achieving high PSRR at high frequencies.

[0009] In one possible implementation, the error amplifier is a PMOS transistor, the source of which is coupled to the source of the first NMOS transistor and the load at a single point, the gate of which is coupled to a first bias voltage source, and the drain of which is used to output the first feedback voltage, wherein the first bias voltage source is used to provide the reference voltage.

[0010] In one possible implementation, the loop gain amplifier is a second NMOS transistor, the gate of which is coupled to the drain of the PMOS transistor, the source of which is coupled to ground, and the drain of which is used to output the second feedback voltage.

[0011] In one possible implementation, the drain of the second NMOS transistor is coupled to the gate of the first NMOS transistor.

[0012] In one possible implementation, the low dropout regulator may further include: a first bias current source, one end of which is coupled to the drain of the PMOS transistor, and the other end of which is coupled to ground.

[0013] In a possible implementation, the low-dropout regulator can further include a second bias current source, one end of the second bias current source being coupled to the power supply end, and the other end of the second bias current source being coupled to the drain of the second NMOS transistor and the gate of the first NMOS transistor at a point.

[0014] In a possible implementation, the first bias current source and the second bias current source can be implemented based on a current mirror.

[0015] In a possible implementation, the low-dropout regulator can further include a second power transistor, the second power transistor being a third NMOS transistor, and the drain of the first NMOS transistor being coupled to the power supply end through the third NMOS transistor. The second power transistor can further isolate the power supply voltage V dd The influence on the source output of the first power transistor is such that A dd is further reduced, thereby improving the PSRR at a high frequency band.

[0016] In a possible implementation, the low-dropout regulator can further include a low-pass filter, and the low-pass filter is coupled to the power supply end and the gate of the third NMOS transistor, respectively.

[0017] In the foregoing implementation, the low-pass filter can include a first impedance and a first capacitor, a first end of the first impedance being coupled to the power supply end, a second end of the first impedance and a first end of the first capacitor being coupled to the gate of the third NMOS transistor at a point, and a second end of the first capacitor being coupled to ground.

[0018] The second aspect of the embodiments of the present application further provides a chip, which includes: a power supply voltage input end, a low-dropout regulator provided by the foregoing first aspect and any possible implementation of the first aspect, and an analog circuit; wherein: the power supply voltage input end is configured to provide an input voltage; the low-dropout regulator is configured to perform low-dropout regulation on the input voltage to generate an output voltage, and to supply power to the analog circuit by using the output voltage. In the present application, the low-dropout regulator with high PSRR at a high frequency band provided by the first aspect is adopted, and the greater the PSRR is, the smaller the ripple at the output end of the LDO is under the same input ripple, so that the design needs of the analog circuit with high requirements on the ripple can be met.

[0019] In a possible implementation, the chip can be a radio frequency transceiver. In a possible implementation, the chip can be a Wi-Fi chip.

[0020] In a possible implementation, the analog circuit can be at least one of a low-noise amplifier, a voltage-controlled oscillator, or a mixer.

[0021] In a possible implementation, the chip can be an optical image sensor.

[0022] In a possible implementation, the chip can be a SoC chip integrating the low-noise amplifier, the voltage-controlled oscillator, the phase-locked loop, or the mixer.

[0023] In a possible implementation, the chip further includes a digital circuit coupled to the power voltage input terminal. Since the digital circuit causes power noise in the power voltage, and the conventional LDO has significant attenuation of the PSRR at a high frequency band, it is difficult to effectively suppress the power noise in the range of 10 MHz to 1 GHz. However, the low-dropout voltage regulator provided in the foregoing implementation of the present application can still achieve high PSRR at the high frequency band, effectively suppress the noise at the high frequency band, and meet the design requirements of the SoC chip applied to the wireless communication scenario.

[0024] The third aspect of the embodiment of the present application further provides a low-dropout voltage regulator, including: a first power transistor, which is a first NPN transistor, a collector of the first NPN transistor being coupled to a power terminal, an emitter of the first NPN transistor being configured to provide an output current to a load, and a base of the first NPN transistor being configured to receive a second feedback voltage; an error amplifier, which is a common-base amplifier, configured to generate a first feedback voltage according to an output voltage provided to the load and a reference voltage; and a loop gain amplifier, which is a common-emitter amplifier, configured to generate the second feedback voltage based on the first feedback voltage. In the present application, by using the first NPN transistor as the power transistor, the effect of the power voltage received by the collector of the NPN transistor on the output voltage of the emitter of the first NPN transistor is isolated, and the noise from the power voltage is prevented from affecting the output voltage, thereby achieving high PSRR at a high frequency band.

[0025] In a possible implementation, the error amplifier is a PNP transistor, an emitter of the PNP transistor and the emitter of the first NPN transistor and the load being coupled to a same point, a base of the PNP transistor being coupled to a first bias voltage source, and a collector of the PNP transistor being configured to output the first feedback voltage, where the first bias voltage source is configured to provide the reference voltage.

[0026] In a possible implementation, the loop gain amplifier is a second NPN transistor, a base of the second NPN transistor being coupled to the collector of the NPN transistor, an emitter of the second NPN transistor being coupled to ground, and a collector of the second NPN transistor being configured to output the second feedback voltage.

[0027] In one possible implementation, the low-dropout regulator may further include a second power transistor, which may be a third NPN transistor, with the collector of the first NPN transistor coupled to the power supply terminal through the third NPN transistor. The second power transistor may further isolate the power supply voltage V. dd The effect on the emitter output of the first power transistor causes A dd Further reduce the size, thereby improving PSRR at high frequencies.

[0028] In one possible implementation, the low-dropout regulator may further include a low-pass filter; the low-pass filter is coupled to both the power supply terminal and the base of the third NPN transistor. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of an LDO with a CAS-FVF structure in the prior art;

[0030] Figure 2 for Figure 1 The diagram shows the PSRR amplitude-frequency response of the LDO.

[0031] Figure 3 A schematic diagram of an LDO applicable to high-frequency bands provided in an embodiment of this application;

[0032] Figure 4 This is the equivalent circuit diagram of a traditional LDO based on negative feedback.

[0033] Figure 5 This is a schematic diagram of the amplitude-frequency response of the error amplifier in a traditional LDO;

[0034] Figure 6 for Figure 3 The diagram shown is a small-signal schematic of an LDO.

[0035] Figure 7 A schematic diagram of another novel LDO applicable to high-frequency bands provided for embodiments of this application;

[0036] Figure 8 This is a schematic diagram of a chip architecture using an LDO, provided as an embodiment of this application. Detailed Implementation

[0037] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship of the associated objects is described by "and / or", which means that there can be three kinds of relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can mean a, b, c, a and b, a and c, b and c, or a and b and c, where a, b and c can be single or multiple. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, "first", "second" and the like are used to distinguish the same items or similar items with basically the same function and effect, and those skilled in the art can understand that "first", "second" and the like do not limit the quantity and execution order. The first, second and the like in the embodiments of the present application are only used for illustration and distinction of the description objects, and there is no order difference, nor does it represent a special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0038] Figure 1 The traditional LDO based on CAS-FVF structure is shown. Among them, M p is a power transistor realized based on a P-channel metal-oxide semiconductor field effect transistor (PMOS), which can also be called a pass transistor. The power transistor M p is responsible for providing current to the load through "node A". It should be noted that, for the sake of convenience, Figure 1 the load equivalent impedance r L and the load equivalent capacitance C L represent the load. In the actual circuit, the load can be various circuits or devices that need to be powered by the LDO. M1 is a common-gate amplifier used as an error amplifier (EA), which compares the output voltage V out of the LDO at "node A" with the reference voltage V set coupled to the gate of M1, and feeds back the change of the output voltage V out to the first feedback voltage V fb1 at "node B". M2 is another common-gate amplifier, which is used to provide loop gain. In this CAS-FVF structure, when the output voltage V outWhen the voltage drops, the current flowing through M1 decreases accordingly, which in turn reduces the first feedback voltage V. fb1 The voltage decreases due to the Vo of the source and drain of the common-gate amplifier M2. fb2 With V fb1 In-phase change, therefore the second feedback voltage V fb2 The power transistor M is also reduced accordingly. The power transistor M is calculated according to the following formula (1). p Brief output current relationship:

[0039] I out ≈g mp *(V DD -V fb2 (1)

[0040] Among them, I out For power transistor M p The drain current, g mp For power transistor M p transconductance, V dd For power transistor M p The power supply voltage of the source.

[0041] According to the above formula, when V fb2 When the current decreases, the output current I out It will increase accordingly, and with I out Increasing it will make V out The pressure rises, thus completing the stabilization process.

[0042] In summary, the entire voltage regulation process of an LDO can be represented as follows:

[0043] V out ↓→V fb1 ↓→V fb2 ↓→I out ↑→V out ↑.

[0044] When the output voltage V out During the rise, the changing trends of various parameters during the voltage regulation process are exactly the opposite of those described above, so they will not be elaborated further here. LDOs with this type of CAS-FVF structure are suitable for on-chip integration due to their advantages such as low power consumption, small area, and low noise.

[0045] However, as Figure 2 As shown, the applicant discovered that Figure 1 The CAS-FVF structure of the LDO shown, like other traditional LDOs, exhibits a significant decrease in PSRR as the frequency increases. Figure 1 The CAS-FVF LDO shown only has a high PSRR in the low-frequency range, while in the high-frequency range, for example at 10MHz (i.e., 10...7 Hz) near, the PSRR of the LDO will be significantly deteriorated.

[0046] It should be noted that the power supply rejection ratio (PSRR), which can also be referred to as "power supply ripple rejection ratio", is a parameter representing the ability of a voltage regulator to suppress power supply noise (noise from the power supply). That is, the PSRR represents the ratio of the two voltage gains obtained when the input power supply and the output power supply are regarded as two independent signal sources. The higher the PSRR, the smaller the change in the output power supply caused by the change in the input power supply, that is, the better the noise suppression performance of the input power supply.

[0047] As the integration level of SoC for wireless communication is getting higher and higher, analog devices such as analog front end and radio frequency front end will be gradually integrated in the SoC. At the same time, as the digital circuit in the SoC works more and more in the high frequency band, the power supply noise distributed between 10MHz and 1GHz becomes one of the main noise factors of the SoC in the high frequency application scenario. Radio frequency analog devices such as linear amplifier (LNA), voltage controlled oscillator (VCO), phase-locked loop (PLL) and mixer (Mixer) are very sensitive to power supply noise in the above range, so the LDO that powers these devices is required to have high PSRR characteristics in the high frequency band to enhance the suppression of power supply noise. Obviously Figure 1 The CAS-FVFLDO shown in the prior art cannot meet this requirement.

[0048] Based on this, the embodiment of the present application provides a new LDO 100 with high PSRR in the high frequency band. As Figure 3 shown, the LDO 100 includes a first power transistor M pass , an error amplifier M1 and a loop gain amplifier M2.

[0049] Wherein, M pass is an N-channel MOS transistor (NMOS), the first power transistor M pass as a power transistor, the drain thereof is coupled to a power supply terminal to receive a power supply voltage V dd , and under the action of a second feedback voltage V fb2 input at the gate, the source thereof provides an output current I out for a load at a node A. For the sake of simplicity, Figure 3 the load equivalent impedance r L and the load equivalent capacitance C L are also used to represent the load in the formula (1). In addition, it should be noted that in the chip, the power supply voltage V ddAs the working voltage of the LDO, the battery voltage input through the power input pin of the chip can be adjusted by the power management unit and then provided to the LDO through the power line. Therefore, the aforementioned power terminal can actually be a node or a different node on the power line providing the same potential. In the subsequent description, the power terminal V dd is used to represent the node providing the power voltage V dd . Specifically, the output current I out can be represented by formula (2):

[0050] I out = g mp *(V fb2 -V out ) (2)

[0051] where g mp is the transconductance of the first power transistor M pass .

[0052] Figure 3 The parasitic capacitances of the first power transistor M pass , including the drain-source parasitic capacitance C ds,p , the gate-drain parasitic capacitance C gd,p , and the gate-source parasitic capacitance C gs,p , are further shown in FIG. 1 to facilitate understanding of the subsequent small-signal schematic. Figure 3 In FIG. 1, the error amplifier M1 is a common-gate amplifier based on a P-channel MOS (PMOS) transistor. The source of the error amplifier M1 is coupled to the source of the first power transistor M pass and the node A, the drain of the error amplifier M1 is connected to the first bias current source I bias1 , and the gate of the error amplifier M1 is connected to the first bias voltage source V set . The first bias voltage source V set is used to provide a reference voltage, and the first bias current source I bias1 is used to provide a bias current for the error amplifier M1. The above biasing makes the error amplifier M1 work in the saturation region to provide a stable amplification gain. Figure 3 The parasitic impedance r b1 of the first bias current source I bias1 and the parasitic capacitance C fb1 of the node B to ground are further shown in FIG. 1 to facilitate understanding of the subsequent small-signal schematic. The first bias current source I bias1 can be implemented in the chip by using a current mirror or the like, which is not limited in the present application. The error amplifier M1 is used to receive the output voltage V outand a reference voltage V set is coupled to the gate of the error amplifier M1. out The change of the output voltage V fb1 is reflected by a first feedback voltage V bias2 outputted from the drain of the error amplifier M1, i.e. negative feedback is provided.

[0053] The loop gain amplifier M2 is a NMOS-based common-source amplifier, the gate of the loop gain amplifier M2 is coupled to the drain of the error amplifier M1 at "Node B", the source of the loop gain amplifier M2 is grounded, and the drain of the loop gain amplifier M2 is coupled to a power terminal V dd through a second bias current source I bias2 . Figure 3 The parasitic impedance r b2 of the second bias current source I fb2 and the parasitic capacitance C fb1 of "Node C" to ground are further shown in FIG. 2 for facilitating the understanding of the small-signal schematic diagram later. The loop gain amplifier M2 receives the first feedback voltage V fb2 from the drain of the error amplifier M1 through its gate, and outputs a second feedback voltage V fb2 from its drain after gain amplification.

[0054] At "Node C", the second feedback voltage V pass is inputted to the gate of the first power transistor M pass , thereby providing feedback control to the output current of the first power transistor M dd .

[0055] It is noted that the core components of an LDO are the error amplifier EA and the power transistor, and thus, Figure 3 in FIG. 1, the error amplifier M1 and the loop gain amplifier M2 can be considered as a whole as an error amplifier EA based on different partition manners.

[0056] Figure 3 In FIG. 1, the power voltage V dd , the first bias current source I bias1 , the second bias current source I bias2 , etc. are used as bias circuits to provide the required bias for the whole LDO 100, so that the first power transistor M pass , the error amplifier M1 and the loop gain amplifier M2 all work in the saturation region, thereby providing stable amplification gain.

[0057] Figure 3 In FIG. 1, the output voltage V out can be considered as the difference between the reference voltage V set and the gate-source voltage Vgs1 and the drain voltage of the error amplifier Ml is considered as being provided by the gate-source voltage V gs2 and the drain voltage of the loop gain amplifier M2 is considered as being provided by V dd - (V gsp + V out ) provided that V gsp is the gate-source voltage of the first power transistor M pass . By providing the appropriate biasing of these voltages, it is ensured that the first power transistor M pass , the error amplifier Ml and the loop gain amplifier M2 all operate in the saturation region, thereby resulting in a stable gain.

[0058] Figure 3 The voltage regulation process of the LDO 100 shown in FIG. 1 is roughly as follows: when the output voltage V out drops, the current flowing through the error amplifier Ml decreases accordingly, causing the first feedback voltage V fb1 to decrease. Since the loop gain amplifier M2 is designed as a common-source amplifier, its voltage gain is negative, and thus the second feedback voltage V fb2 outputted by the drain of the loop gain amplifier M2 is inversely proportional to the first feedback voltage V fb1 received by the gate, that is, when the first feedback voltage V fb1 decreases, the second feedback voltage V fb2 increases. According to the aforementioned formula (2), as the second feedback voltage V fb2 increases, the output current I pass of the first power transistor M out based on NMOS also increases. The increase of the output current I out further causes the output voltage V out of the LDO 100 to increase, thereby achieving voltage regulation.

[0059] To summarize, the voltage regulation process of the LDO 100 based on the negative feedback mechanism can be represented as follows:

[0060] V out ↓→V fb1 ↓→V fb2 ↑→I out ↑→V out ↑.

[0061] Those skilled in the art should know that, under the negative feedback mechanism, when the output voltage V out increases, the change trends of various parameters in its voltage regulation process are just the opposite of the above-described voltage regulation process, and thus are not described here again.

[0062] It should be noted that, due to the advantages of complementary metal-oxide-semiconductor (CMOS) technology, such as simple manufacturing process and small footprint, it is widely used in large-scale circuits. Therefore, the above embodiments of this application mainly describe the LDO 100 based on CMOS devices. Those skilled in the art should know that in some circuits with small integration scale, devices such as bipolar junction transistors (BJTs) can also be used. Accordingly, the NMOS transistors used in the LDO 100 can be replaced by NPN-type BJTs, and the PMOS transistors can be replaced by PNP-type BJTs. Correspondingly, when the error amplifier M1, which uses a common gate configuration, is replaced with a PNP-type BJT, a common base configuration can be used; and when the loop gain amplifier M2, which uses a common source configuration, is replaced with an NPN-type BJT, a common emitter configuration can be used. Therefore, based on the ideas of the embodiments of this application, using BJTs to implement the LDO can be considered an equivalent substitution of the embodiments of this application and should be included within the protection scope of this application.

[0063] The novel LDO 100 provided in this application embodiment, in addition to having the basic function of voltage regulation, uses fewer transistors and has a simpler circuit structure, which can meet the chip design requirements for low power consumption and small area. At the same time, fewer transistors mean fewer noise sources in the LDO itself, resulting in lower system noise and facilitating on-chip integration. More importantly, while possessing the aforementioned advantages, the LDO 100 also has high-frequency and high PSRR performance.

[0064] The following combination Figure 4-6 right Figure 3 The high-frequency PSRR performance of the LDO 100 is described in detail.

[0065] like Figure 4 For a traditional negative feedback LDO system, its system gain is mainly divided into two categories: 1. The system's loop gain A v 2. Power supply voltage V dd After passing through power transistor M pass Small-signal gain A to output voltage dd .

[0066] Figure 4 In the diagram, V1 represents the voltage at the non-inverting input terminal of error amplifier EA, and V2 represents the voltage at the inverting input terminal of error amplifier EA. ss This represents the grounding voltage. The system's output voltage V out It can be expressed by formula (4):

[0067] V out =Add V dd +A v (V1-V2)=A dd V dd -A v V out (4)

[0068] By transforming formula (4), we can obtain the following formula (5):

[0069] V out (1+A v ) = A dd V dd (5)

[0070] For the error amplifier EA, its amplitude-frequency characteristic is typically as follows: Figure 5 As shown. According to Figure 5 As can be seen, at low frequencies, the amplitude of the signal amplified by the error amplifier EA is very large, and the loop gain A it provides is also large. v Much greater than 1.

[0071] Therefore, according to formula (5), we can further obtain:

[0072]

[0073] According to formula (6), to improve the PSRR of the system, the loop gain A needs to be increased. v and reduce A dd .

[0074] Figure 5 Further, it is shown that as the frequency increases, the amplitude degradation of the signal amplified by the error amplifier EA also gradually increases. For example, when the frequency changes from the low-frequency f1 to the high-frequency f2, the amplitude degradation is 20dB. Correspondingly, the loop gain A provided by the error amplifier EA... v It also decreases significantly with increasing frequency. In other words, due to the amplitude-frequency characteristics of the error amplifier EA, it is impossible to increase the loop gain A in high-frequency applications. v To improve the system's PSRR, the only option is to reduce A. dd To improve the system's PSRR.

[0075] However, for Figure 1 For the LDO with the CAS-FVF structure shown, its power transistor M p Using a PMOS transistor, according to formula (1), the power supply voltage V dd It can be achieved through power transistor M p The parasitic capacitance between the source and drain is fed into the output voltage V. outThe small signal analysis shows that, Figure 1 The power terminal V dd The impedance R p of the "Node A" can be regarded as the impedance 1 / g p generated by the transconductance of the power transistor M mp and the internal resistance r p of the power transistor M op in parallel, i.e. as shown in equation (7):

[0076] R p = 1 / g m / / r op (7)

[0077] Further, the small signal gain A dd of the power voltage V pass directly to the output through the power transistor M dd satisfies the relationship shown in equation (8) as follows:

[0078]

[0079] where R l is the impedance from the load terminal, and R l is much smaller than R p .

[0080] Therefore, to reduce A dd , it is necessary to make R p large. However, in the Figure 1 , since the power transistor M p is responsible for providing a large current, according to equation (1), since the power voltage V dd and the output voltage V out are relatively fixed, to provide a large current, the power transistor M p is required to have a larger transconductance g mp , so that the transconductance g mp cannot be made smaller. The larger the transconductance g mp , the smaller the R p , thereby resulting in that the gain A dd of the system is difficult to be small at high frequency, and thus it can be seen that Figure 1 the LDO with the CAS-FVF structure shown in the figure can present good PSRR at low frequency, but cannot achieve high PSRR at high frequency.

[0081] Those skilled in the art should know that in the current integrated circuit, analog circuit and digital circuit are generally integrated at the same time, and the existence of the digital circuit causes the power voltage V dd of the integrated circuit to usually have a large power noise, and thus when using Figure 1When the LDO with the CAS-FVF structure shown supplies power to the analog circuit, due to the power transistor M... pass Using a PMOS transistor, refer to formula (1), power supply voltage V dd The source input voltage of the PMOS transistor is fed to the output voltage V at the drain of the PMOS transistor. out In addition, this will also seriously affect the performance of analog circuits.

[0082] And this application Figure 3 As shown in the LDO 100, according to formula (2), since the first power transistor M... pass Using an NMOS transistor, its output current I out Mainly related to the second feedback voltage V at the gate input fb2 and output voltage V out Related to the power supply voltage V dd Decoupling is achieved between them. Therefore, the power supply voltage V dd Coupled to output voltage V out The part in it is negligible, and correspondingly, A dd This naturally reduces the PSRR, thereby ensuring that the PSRR can be improved to meet the power supply noise suppression requirements of RF devices such as LNA, VCO, PLL, and Mixer that are sensitive to high-frequency PSRR.

[0083] The above content theoretically analyzes how the LDO 100 of this application improves PSRR and enhances power supply noise suppression capability. The following section provides a more intuitive explanation of how the LDO 100 of this application achieves high power supply noise suppression capability from another perspective: Since the LDO 100 uses an NMOS transistor as the first power transistor M... pass The source output current I of the NMOS transistor out Mainly related to the output voltage V out The second feedback voltage V input to the gate fb2 Related to the power supply voltage V received at the drain of the NMOS transistor. dd For output current I out The impact is almost negligible; correspondingly, the power supply voltage V dd Changes in output voltage V due to factors such as noise out It has almost no impact, therefore, the LDO 100 can largely isolate the power supply voltage V. dd The adverse effects of power supply noise, compared to Figure 1 The LDO with the CAS FVF architecture shown further improves noise performance.

[0084] Furthermore, Figure 6 It shows Figure 3 The diagram shown is a small-signal schematic of an LDO 100. Based on... Figure 6As can be seen, the LDO 100 provided in this application embodiment is actually a three-stage gain negative feedback system, wherein the first-stage gain A1 = g mp / [g mp +1 / (r L / / r op )];Second-stage gain A2=(g m1 r o1 +1)*r b1 / (r b1 +r o1 Third-stage gain A3 = -g mp *(r mp / / r L ), where r o1 r is the internal resistance of the error amplifier M1. o2 r is the internal resistance of the loop gain amplifier M2. op For the first power transistor M pass The internal resistance, g m1 For the transconductance of error amplifier M1, g m2 The transconductance of the loop gain amplifier M2 is given; the remaining equivalent circuit can be referred to the description in the foregoing embodiments. Therefore, at low frequencies, the LDO 100 can achieve a high loop gain A. v This allows the LDO100 to have a high PSRR at low frequencies, while at high frequencies, it achieves this by using a small A. dd This also achieves a high PSRR.

[0085] It should be noted that in this application, the first power transistor M of the LDO 100 pass The pressure drop, compared to Figure 1 The LDO with the CAS-FVF structure shown has a larger voltage drop because the first power transistor M of the LDO 100 is larger. pass The voltage drop includes its threshold voltage. However, in high-frequency applications, for devices sensitive to high-frequency PSRR, it is feasible to achieve higher high-frequency PSRR performance than the CAS-FVF structure LDO while sacrificing a small amount of voltage drop. Therefore, using the LDO 100 provided in this application embodiment will bring a better balance in integrated circuit design.

[0086] Furthermore, this application in Figure 3 Based on the LDO 100 shown, a further improvement was made, providing the LDO 200 with higher PSRR at higher frequencies. For example... Figure 7 As shown, the LDO 200 includes: a first power transistor M pass The system includes an error amplifier M1, a loop gain amplifier M2, and a second power transistor M3.

[0087] Among them, the first power transistor M pass It is an NMOS transistor, the first power transistor M pass The drain is coupled to the power supply terminal to receive the power supply voltage V. dd The first power transistor M pass As a power transistor, the second feedback voltage V input at the gate fb2 Under the action of the source electrode, the output current I is provided through the load at "node A". out .

[0088] Figure 7 In the diagram, error amplifier M1 is a PMOS-based common-gate amplifier. The source of error amplifier M1 is connected to the first power transistor M. pass The source of the error amplifier M1 is coupled to node A, and the drain of the error amplifier M1 is connected to the first bias current source I. bias1 The gate of error amplifier M1 is connected to the first bias voltage source V. set Among them, the first bias voltage source V set Used to provide a reference voltage, first bias current source I bias1 This is used to provide bias current for error amplifier M1. Error amplifier M1 is used to receive the output voltage V of LDO at "node A" through its source. out and the reference voltage V coupled to the gate of M1 set The comparison is performed, and the output voltage V is reflected by the drain output of the error amplifier M1. out The change in the first feedback voltage V fb1 That is, to provide negative feedback.

[0089] The loop gain amplifier M2 is a common-source amplifier. The gate of the loop gain amplifier M2 is coupled to the drain of the error amplifier M1 at "node B". The source of the loop gain amplifier M2 is grounded, and the drain of the loop gain amplifier M2 is connected to the second bias current source I. bias2 Coupled to power supply terminal V dd The loop gain amplifier M2 receives the first feedback voltage V from the drain of the error amplifier M1 through its gate. fb1 After gain amplification, the second feedback voltage V is output from the drain of the self-loop gain amplifier M2. fb2 .

[0090] At node C, the second feedback voltage V fb2 Input to the first power transistor M pass The gate of the first power transistor M, thereby controlling the first power transistor M pass The output current is controlled by feedback.

[0091] The aforementioned first power transistor M pass The structure and function of error amplifier M1 and loop gain amplifier M2 are similar toFigure 3 The components are basically similar and can be used as a reference.

[0092] and Figure 3 The difference between the LDO 100 shown is that the first power transistor M pass The drain receives the power supply voltage V through the second power transistor M3. dd Specifically, the second power transistor M3 is an NMOS transistor, and the first power transistor M... pass The drain of the first transistor is coupled to the source of the second power transistor M3, and the drain of the second power transistor M3 is coupled to the power supply terminal. The second power transistor M3 receives the power supply voltage V through its drain. dd And through its source, the first power transistor M pass Provides operating voltage.

[0093] Figure 7 The LDO 200 shown also includes a low-pass filter, which is coupled to the power supply terminal to regulate the power supply voltage V. dd After low-pass filtering, the gate control voltage is provided for the second power transistor M3.

[0094] For example, the low-pass filter may include a first impedance r M1 and the first capacitor C M1 Wherein, the first impedance r M1 The first end is coupled to the power supply terminal, and the first impedance r M1 The second end is coupled to the first capacitor C M1 The first terminal, the first capacitor C M1 The second terminal is coupled to ground. Through the first impedance r... M1 The second terminal is connected to the first capacitor C M1 A point on the connection between the first and second terminals provides the gate control voltage for the second power transistor M3. Those skilled in the art should know that inductors can transmit low-frequency components, while capacitors can transmit high-frequency components. Therefore, the power supply voltage V... dd The high-frequency components in the first impedance r M1 After filtering, the remaining high-frequency components are then passed through the first capacitor C. M1 Coupling grounding allows the power supply voltage V to be coupled to ground. dd The low-frequency component is provided to the second power transistor M3 as the gate control voltage.

[0095] It should be understood that low-pass filters can also be implemented by other circuit structures, and prior art can be referenced for details. This application does not limit the scope of such implementation.

[0096] By adopting the above design, the LDO 200 provided in this embodiment can further isolate the power supply voltage V. ddThe power supply noise existing in the system is reduced, and the noise performance of the system is improved.

[0097] In the LDO 200, the second power transistor M3 can further reduce A dd , and its working principle is similar to that of the first power transistor M1 for reducing A dd . For details, please refer to the foregoing analysis of how the first power transistor M1 reduces A dd . Since the first power transistor M1 and the second power transistor M3 are used to jointly reduce A dd , the LDO 200 can achieve a higher PSRR at a high frequency band. It should be noted that although the LDOs shown in Figure 3 and Figure 7 have a high PSRR at a high frequency band compared with the existing CAS-FVF structure LDO, since the LDOs shown in Figure 3 and Figure 7 are all three-gain negative feedback systems, at a low frequency, the PSRR of the system can also be improved by increasing the loop gain A v , and therefore, Figure 3 and Figure 7 are also suitable for low-frequency application scenarios.

[0098] As shown in Figure 8 , the application further provides a chip 300 applicable to a high frequency band, which can include a power supply voltage input end V in , a low-dropout regulator 301, and an analog circuit 302. Wherein:

[0099] The power supply voltage input end V in is configured to provide an input voltage for the chip, and the input voltage can be transformed by a power management unit (not shown in the figure) to generate the aforementioned power supply voltage V dd ;

[0100] The low-dropout regulator 301 is coupled to the power supply voltage input end V in , and is configured to provide an output voltage V dd and an output current I out for the analog circuit 302 after low-dropout regulation of the power supply voltage V out . Wherein, the low-dropout regulator 301 can refer to the LDO 100 or LDO 200 provided in the foregoing embodiments, and the analog circuit 302 is the load shown in Figure 3 or Figure 7 . It should be noted that the low-dropout regulator 301 can also be integrated with the power management unit.

[0101] For example, the chip 300 can be a radio frequency transceiver chip for high frequency communication, and the analog circuit 302 can be at least one of an LNA, a VCO, a mixer, etc. in the radio frequency transceiver. By using the low-dropout regulator 301 shown in the present application Figure 3 or Figure 7 , the PSRR of the chip 300 at a high frequency band can be improved, so that the chip 300 has good PSRR performance at both low and high frequency bands, and meets the performance requirements of analog devices such as LNA, VCO, PLL, and mixer, which are sensitive to high frequency PSRR. In addition, the chip 300 can also be a wireless communication chip such as a wireless fidelity (Wi-Fi) chip, which is sensitive to residual ripple in the output voltage, or an optical image sensor.

[0102] Further, the chip 300 can further include a digital circuit 303 powered by the power supply voltage input end V in . The power supply voltage V dd provided by the low-dropout regulator 301 can power the digital circuit 303. That is, the chip 300 can be a digital-analog hybrid chip. With the development of communication technology, the future design of SoC chips will gradually integrate radio frequency front-end and analog front-end devices, such as the aforementioned radio frequency transceiver or Wi-Fi chip, which will also be integrated into the SoC. In addition, there are a large number of digital logic circuits in the SoC, such as digital baseband, etc. Due to the characteristics of high and low level jumps of the working voltage of the digital circuit, the power supply voltage V dd is usually obtained by adjusting the input voltage provided by the power supply voltage input end V in by a power management unit based on a BUCK or BOOST switching circuit, resulting in a power supply voltage V dd with a large power supply noise. The low-dropout regulator 301 provided in the present application has the function of isolating the power supply noise and the output voltage V out , which can significantly reduce the impact of the power supply noise on the output voltage V out , and thus has good power supply noise suppression capability at both low and high frequencies, which can bring more choices for the design of digital-analog hybrid SoC chips.

[0103] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any skilled person in the art can make changes or substitutions based on the principles disclosed in the present application within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A low dropout voltage regulator, characterized by, Comprising: a first power transistor, the first power transistor being a first NMOS transistor, a drain of the first NMOS transistor being coupled to a power supply terminal, a source of the first NMOS transistor being configured to provide an output current to a load, a gate of the first NMOS transistor being configured to receive a second feedback voltage; an error amplifier, the error amplifier being a common-gate amplifier, configured to generate the first feedback voltage according to a reference voltage and an output voltage provided to the load; a loop gain amplifier, the loop gain amplifier being a common-source amplifier, configured to generate the second feedback voltage based on the first feedback voltage; a first bias current source, configured to provide a bias current to the error amplifier; a second bias current source, the loop gain amplifier being coupled to the second bias current source.

2. The low dropout regulator of claim 1, wherein, The error amplifier is a PMOS transistor, a source of the PMOS transistor being coupled to a point at which a source of the first NMOS transistor and the load are coupled, a gate of the PMOS transistor being coupled to a first bias voltage source, a drain of the PMOS transistor being configured to output the first feedback voltage, wherein the first bias voltage source is configured to provide the reference voltage.

3. The low dropout regulator of claim 2, wherein, The loop gain amplifier is a second NMOS transistor, a gate of the second NMOS transistor being coupled to a drain of the PMOS transistor, a source of the second NMOS transistor being coupled to ground, a drain of the second NMOS transistor being configured to output the second feedback voltage.

4. The low dropout regulator of claim 3, wherein, The drain of the second NMOS transistor is coupled to the gate of the first NMOS transistor.

5. The low dropout regulator of claim 2, wherein, One end of the first bias current source is coupled to the drain of the PMOS transistor, and the other end of the first bias current source is coupled to ground.

6. The low dropout regulator of claim 3, wherein, One end of the second bias current source is coupled to the power supply terminal, and the other end of the second bias current source is coupled to a point at which the drain of the second NMOS transistor and the gate of the first NMOS transistor are coupled.

7. The low dropout regulator of any of claims 1-6, wherein, Further comprising: a second power transistor, the second power transistor being a third NMOS transistor, a drain of the first NMOS transistor being coupled to the power supply terminal through the third NMOS transistor.

8. The low dropout regulator of claim 7, wherein, The drain of the first NMOS transistor is coupled to a source of the third NMOS transistor, and a drain of the third NMOS transistor is coupled to the power supply terminal.

9. The low dropout regulator of claim 8, wherein, Further comprising: a low-pass filter; The low-pass filter is coupled to the power supply terminal and a gate of the third NMOS transistor, respectively.

10. The low dropout regulator of claim 9, wherein, The low-pass filter comprises a first impedance and a first capacitor, a first end of the first impedance being coupled to the power supply terminal, a second end of the first impedance and a first end of the first capacitor being coupled to a point at which the gate of the third NMOS transistor is coupled, and a second end of the first capacitor being coupled to ground.

11. A chip, characterized by Comprising: a power voltage input terminal, a low-dropout regulator according to any one of claims 1-10, and an analog circuit; wherein: The power voltage input terminal is configured to provide a power voltage; The low-dropout regulator is configured to perform low-drop regulation on the power voltage to generate an output voltage, and to use the output voltage to power the analog circuit.

12. The chip of claim 11, wherein, The chip is a radio frequency transceiver.

13. The chip of claim 11, wherein, The chip is a Wi-Fi chip.

14. The chip according to claim 12 or 13, characterized in that, The analog circuit is at least one of a low noise amplifier, a voltage controlled oscillator, a phase locked loop, or a mixer.

15. The chip according to any of claims 11-14, characterized by Also included are: a digital circuit coupled to the power supply voltage input.

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