Semiconductor device and method with increased attachment angle of conductive wire

Abstract

Semiconductor devices and methods with increased attachment angle of conductive lines. A semiconductor device includes a shield line formed across a semiconductor die and an auxiliary line supporting the shield line, thereby reducing a size of a package while shielding electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted to the substrate, a shield line spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary line supporting the shield line under the shield line and formed perpendicular to the shield line. In another embodiment, a bump structure is used to support the shield line. In yet another embodiment, an auxiliary line includes a bump structure portion and a line portion, and both the bump structure portion and the line portion are used to support the shield line.

Description

[0001] This application is a divisional application of the invention patent application filed on March 6, 2017, with a priority date of March 10, 2016, application number 201710128412.7, entitled "Semiconductor device and method for conductive wires having an increased attachment angle". Technical Field

[0002] Some embodiments of the present invention relate to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0003] Because various semiconductor devices with different configurations and electronic devices for exchanging various signals are integrated into various electronic devices, it is well known that semiconductor devices and electronic devices emit electromagnetic interference during electrical operation.

[0004] Electromagnetic interference can be emitted from semiconductor devices and electronic devices mounted on a motherboard at narrow intervals, and adjacent semiconductor devices can be directly or indirectly affected by electromagnetic interference.

[0005] Therefore, wires or shielding layers can be used to partially shield semiconductor devices. However, using wires or shielding layers in this case may increase the size of the semiconductor device. Summary of the Invention

[0006] The present invention provides a semiconductor device comprising a shielding line formed across a semiconductor die and an auxiliary structure supporting the shielding line, thereby reducing the size of the semiconductor package while shielding electromagnetic interference generated from the semiconductor die.

[0007] The above and other objectives of the present invention will be set forth in or apparent from the following description of several embodiments.

[0008] According to one aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a substrate on which at least one circuit means is mounted; a semiconductor die spaced apart from and mounted on the substrate of the circuit means; a shielding line spaced apart from and formed across the semiconductor die; and an auxiliary structure supporting the shielding line below the shielding line. In some embodiments, the auxiliary structure includes an auxiliary line formed substantially perpendicular to the shielding line.

[0009] According to another aspect of an embodiment of the invention, a substrate is provided; a semiconductor die is mounted adjacent to the substrate; an auxiliary structure is connected to the substrate; and a conductive line is connected at a first end to a first portion of the substrate and physically contacts the auxiliary structure to increase the angle at which the conductive line is connected to the substrate. According to another embodiment, a method includes providing a substrate having a semiconductor die connected to a surface of the substrate. The method includes forming an auxiliary structure coupled to the substrate and connecting a conductive line to the substrate, wherein the conductive line physically contacts the auxiliary structure to increase the angle at which the conductive line is connected to the substrate.

[0010] As described above, according to an embodiment of the present invention, because the semiconductor device includes a shielding line spaced apart from and spanning the semiconductor die and an auxiliary structure supporting the shielding line below the shielding line, the distance between the semiconductor die and the circuit device can be reduced, and electromagnetic interference generated from the semiconductor die can be shielded, thereby reducing the size of the semiconductor device according to the present invention.

[0011] In another embodiment, the size of the semiconductor device can be reduced because the semiconductor device includes conductive lines electrically connecting the semiconductor die to the substrate and auxiliary structures supporting the conductive lines below the conductive lines.

[0012] Furthermore, according to another embodiment, the auxiliary structure includes a bump structure disposed adjacent to the conductive line to facilitate the conductive line having a steeper tilt angle. In yet another embodiment, the auxiliary structure includes a bump structure portion and a line portion, and both the bump structure portion and the line portion are used to facilitate a bonding line having an even steeper tilt angle. Attached Figure Description

[0013] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0014] Figure 2 for Figure 1 A plan view of the semiconductor device described herein;

[0015] Figure 3A and 3B for Figure 2 Part of the photo of "A";

[0016] Figure 4 This is a plan view of a semiconductor device according to another embodiment of the present invention;

[0017] Figure 5 This is a plan view of a semiconductor device according to an embodiment of the present invention;

[0018] Figure 6A A cross-sectional view of a semiconductor device using auxiliary lines according to an embodiment of the present invention;

[0019] Figure 6B and 6C for Figure 6A A plan view of the semiconductor device described herein;

[0020] Figure 7A This is a front view of an auxiliary line according to an embodiment of the present invention;

[0021] Figure 7B For application Figure 7A A perspective view of a semiconductor device with auxiliary lines as illustrated in the diagram;

[0022] Figure 8A This is a front view of an auxiliary line according to an embodiment of the present invention;

[0023] Figure 8B For application Figure 8A A perspective view of a semiconductor device with auxiliary lines as illustrated in the diagram;

[0024] Figure 9 A cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0025] Figure 10 This is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0026] Figure 11 for Figure 10 Part of the photo of "B";

[0027] Figure 12 This is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention; and

[0028] Figure 13 for Figure 12 A partial photo of the "C". Detailed Implementation

[0029] This application claims priority to U.S. Patent Application No. 15 / 368,583, filed December 3, 2016, and Korean Patent Application No. 10-2016-0028899, filed March 10, 2016, the entire contents of which are incorporated herein by reference.

[0030] In the following, examples of various embodiments will be described in detail with reference to the accompanying drawings, so that they can be made and used by those skilled in the art.

[0031] Various aspects of the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In fact, these exemplary embodiments of the invention are provided so that the invention will be fully and completely understood, and will convey various aspects of the invention to those skilled in the art.

[0032] In the diagrams, the thickness of layers and regions may be enlarged for clarity. Here, similar reference numerals refer to similar elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Furthermore, it should be understood that when element A is referred to as "connected to" element B, element A may be directly connected to element B, or element C may be inserted between element A and element B so that element A can be indirectly connected to element B.

[0033] Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. It will be further understood that the terms comprises / comprising and / or includes / including, when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0034] It should be understood that while the terms first, second, etc., may be used herein to describe various parts, elements, regions, layers, and / or sections, these parts, elements, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one part, element, region, layer, and / or section from another part, element, region, layer, and / or section. Thus, by way of example, the first part, first element, first region, first layer, and / or first section discussed below may be referred to as the second part, second element, second region, second layer, and / or second section without departing from the teachings of the invention. Unless otherwise specified, the terms “on top of” or “on” as used herein include orientation, placement, or relationship in which the specified elements may be in direct or indirect physical contact. Unless otherwise specified, the terms “overlapping with” as used herein include orientation, placement, or relationship in which the specified elements may at least partially or completely coincide or align in the same or different planes. It should be further understood that the embodiments illustrated and described below may suitably be practiced with embodiments and / or without any elements precisely disclosed herein.

[0035] Figure 1 This is a cross-sectional view of a semiconductor device 100 according to one embodiment. Figure 2 for Figure 1The plan view of the semiconductor device described herein, Figure 3A and 3B For filming Figure 2 Part of the photo of "A", and Figure 4 This is a plan view of a semiconductor device 100 according to another embodiment.

[0036] refer to Figure 1 and 2 According to one embodiment, a semiconductor device 100 includes a substrate 110, a semiconductor die 120, a circuit arrangement 130, a shielding line 140 or a shielding line structure 140, and auxiliary structures such as an auxiliary line 150.

[0037] In one embodiment, the semiconductor die 120 is mounted adjacent to or on the substrate 110. The substrate 110 may be, for example, a printed circuit board (PCB) including an insulating layer and multiple circuit patterns formed on and / or within the insulating layer. Alternatively, the substrate 110 may be one of the group consisting of rigid printed circuit boards, flexible printed circuit boards, ceramic circuit boards, in-circuit inserts, and similar structures known to those skilled in the art. Rigid printed circuit boards typically comprise phenolic resin or epoxy resin as a base material and may have multiple circuit patterns formed on and / or adjacent to the surface and / or surface and / or surface of the rigid printed circuit board. Flexible printed circuit boards typically comprise polyimide resin as a base material and may have multiple circuit patterns formed on and / or adjacent to the surface and / or surface of the flexible printed circuit board. Ceramic circuit boards typically comprise ceramic as a base material and may have multiple circuit patterns formed on and / or adjacent to the surface and / or surface of the ceramic circuit board. In-circuit inserts may be silicon-based or dielectric-based. In addition, various types of substrates can be used in embodiments of the present invention, but the present invention does not particularly limit the type of substrate 110.

[0038] In some embodiments, the semiconductor die 120 is mounted on or adjacent to the substrate 110. The semiconductor die 120 may be electrically connected to the substrate 110 via conductive bumps (not shown) or other connection structures as known to those skilled in the art. The semiconductor die 120 may be electrically connected to the circuit pattern of the substrate 110 via, for example, a large-scale reflow process, a thermal compression process, or a laser bonding process. The semiconductor die 120 may feature characteristics of different types of semiconductor dies. The semiconductor die 120 may include, for example, processor dies, memory dies, application-specific integrated circuit dies, general-purpose logic dies, active semiconductor components, and other electronic devices as known to those skilled in the art. In some embodiments, the conductive bumps of the semiconductor die 120 may include, for example, conductive balls (e.g., solder balls), conductive pillars (e.g., copper pillars), and / or conductive posts having solder caps formed on the copper pillars.

[0039] In some embodiments, the circuit device 130 is mounted on or adjacent to the substrate 110 and positioned near or close to the semiconductor die 120. The circuit device 130 may be, for example, a passive device, an active device, and / or a semiconductor die. The circuit device 130 may comprise a plurality of circuit devices formed near the semiconductor die 120. The circuit device 130 may be electrically connected to the circuit pattern of the substrate 110 via, for example, a large-scale reflow process, a thermal compression process, or a laser bonding process.

[0040] According to an embodiment of the present invention, the shielding line 140 is spaced apart from the semiconductor die 120 and formed to surround the semiconductor die 120. The shielding line 140 may be configured to shield electromagnetic interference generated from the semiconductor die 120 from being emitted to the outside, or to prevent external electromagnetic interference from penetrating into the semiconductor die 120. Additionally, the shielding line 140 is used to prevent electromagnetic interference from occurring between the semiconductor die 120 and the circuit arrangement 130 of the semiconductor device 100. Therefore, the shielding line 140 may include multiple shielding lines and may surround the semiconductor die 120. Here, as the number of shielding lines 140 increases, the EMI shielding performance can be improved.

[0041] According to an embodiment of the invention, one end of the shielding line 140 is bonded to a substrate 110 located on one side of the semiconductor die 120, and the other or opposite end of the shielding line 140 is bonded to a substrate 110 located on the other side of the semiconductor die 120. More specifically, the shielding line 140 is spaced apart from the semiconductor die 120 and is formed across the semiconductor die 120 to overlap with it. In some embodiments, the shielding line 140 may be bonded to or attached to bonding pads 111 and 112 formed on the substrate 110. The bonding pad located on one side of the semiconductor die 120 may be referred to as the first bonding pad 111, and the bonding pad located on the other side of the semiconductor die 120 may be referred to as the second bonding pad 112. More specifically, in some embodiments, one end of the shielding line 140 is bonded to the first bonding pad 111, and then the other end of the shielding line 140 is bonded across the semiconductor die 120 to the second bonding pad 112. According to an embodiment of the invention, the shielding line 140 may be coupled to the second bonding pad 112 while forming a sharp or steep angle with the auxiliary line 150, which will be described in more detail later in the description of the auxiliary line 150.

[0042] The second bonding pad 112 is positioned between the semiconductor die 120 and the circuit arrangement 130. In one embodiment, the first bonding pad 111 and the second bonding pad 112 may be electrically connected to the ground of the substrate 110. Therefore, the shielding wire 140 bonded to the first bonding pad 111 and the second bonding pad 112 may also be electrically connected to the ground of the substrate 110. Although in Figure 2 The first bonding pad 111 is described as a single unit, but it can be composed of multiple units formed spaced apart from each other or laterally separated so as to correspond to multiple shielding lines 140 respectively. Similarly, although in Figure 2 The second bonding pad 112 is described as a single unit, but it may be composed of multiple units formed spaced apart or laterally separated from each other to correspond to multiple shielding lines 140 respectively. However, since the first bonding pad 111 and the second bonding pad 112 are connected to ground, each of the first bonding pad 111 and the second bonding pad 112 is more preferably formed as a single unit. The shielding lines 140 may be made of gold (Au), silver (Ag), copper (Cu) and / or other materials as known to those skilled in the art. In addition, in some embodiments, the shielding lines 140 may be formed by additionally coating an insulating material onto the aforementioned metal forming the shielding lines 140. Thus, short-circuiting of the shielding lines 140 to elements disposed in the semiconductor device 100 can be prevented. Here, the insulating material coated on the shielding lines 140 may be made of, for example, one selected from the group consisting of polypropylene, polyethylene, polyimide, polycarbonate and / or equivalents, but aspects of the invention are not limited thereto.

[0043] According to an embodiment of the invention, the auxiliary line 150 is positioned below the shielding line 140 and formed to intersect the shielding line 140. In some embodiments, the auxiliary line 150 is positioned substantially perpendicular to the shielding line 140 and formed near the second bonding pad 112. More specifically, the auxiliary line 150 is positioned between the semiconductor die 120 and the second bonding pad 112. Furthermore, because the auxiliary line 150 is formed in each of the plurality of shielding lines 140, the auxiliary lines 150 can be arranged in lines to be substantially parallel to each other. In some embodiments, the auxiliary line 150 has a smaller width than the shielding line 140 and is formed in an arc shape. Additionally, in other embodiments, the thickness of the auxiliary line 150 may be equal to or greater than the thickness of the shielding line 140. However, because the auxiliary line 150 needs to support the shielding line 140, the auxiliary line 150 is more preferably thicker than the shielding line 140.

[0044] According to an embodiment of the invention, the auxiliary line 150 supports the shielding line 140 and increases the angle at which the shielding line 140 engages with the second bonding pad 112. More precisely, as Figure 1 As described, one end of the shielding line 140 is bonded to the first bonding pad 111, and the other end of the shielding line 140 crosses the semiconductor die 120 and is bonded to the second bonding pad 112. When no auxiliary line is present, the shielding line 140 needs to be bonded to... Figure 1The portion at the end of the dashed line. For example, when no auxiliary line is present, the shielding line can be engaged to the second bonding pad at an angle of approximately 45 degrees. According to an embodiment of the invention, the auxiliary line 150 is formed under the shielding line 140 such that the shielding line 140 contacts the auxiliary line 150. Therefore, the angle (a) at which the shielding line 140 engages with the second bonding pad 112 increases rapidly or slopes more steeply. According to an embodiment of the invention, the shielding line can be engaged or attached to the second bonding pad 112 at an angle greater than 45 degrees. According to an embodiment of the invention, the shielding line 140 can be engaged to the second bonding pad 112 at an angle in the range of approximately 70 degrees to approximately 90 degrees. Furthermore, according to an embodiment of the invention, as the auxiliary line 150 supports the shielding line 140 with an increased force, that is, as the thickness of the auxiliary line 150 becomes greater than the thickness of the shielding line 140, the shielding line 140 can be engaged to the second bonding pad 112 at an angle of approximately 90 degrees. Therefore, according to an embodiment of the invention, the distance between the semiconductor die 120 and the circuit device 130 can be reduced, thereby reducing the size of the semiconductor device 100. For example, the distance (t) between the semiconductor die 120 and the circuit device 130 can be about 100 micrometers or less. Additionally, the auxiliary line 150 can be made of gold (Au), silver (Ag), copper (Cu), and / or other materials known to those skilled in the art. Furthermore, the auxiliary line 150 can be formed by additionally coating an insulating material onto the aforementioned metal. Therefore, shorting of the auxiliary line 150 to components disposed in the semiconductor device 100 can be prevented. Here, the insulating material coated on the auxiliary line 150 can be made of, for example, one selected from the group consisting of: polypropylene, polyethylene, polyimide, polycarbonate, and / or other materials known to those skilled in the art.

[0045] like Figure 4 As illustrated, auxiliary lines 250 and their adjacent auxiliary lines can be arranged alternately. More specifically, a first group (e.g., odd-numbered) of auxiliary lines 250 can be arranged to approach the semiconductor die 120, and a second group (e.g., even-numbered) of auxiliary lines 250 can be arranged to approach the second bonding pad 112. According to embodiments of the invention, the shielding lines 140 can be arranged more densely, thereby improving the EMI shielding performance of the semiconductor die 120.

[0046] As described above, a semiconductor device 100 according to an embodiment of the present invention includes a shielding line 140 spaced apart from and surrounding the semiconductor die 120; and an auxiliary line 150 supporting the shielding line 140 below the shielding line 140, thereby reducing the distance between the semiconductor die 120 and the circuit arrangement 130 while shielding electromagnetic interference generated from the semiconductor die 120. Therefore, the size of the semiconductor device 100 according to an embodiment of the present invention can be reduced compared to related devices.

[0047] Figure 5 This is a plan view of a semiconductor device 300 according to another embodiment. (See reference...) Figure 5 In some embodiments, the semiconductor device 300 includes a substrate 110, a semiconductor die 120, a circuit arrangement 130, a shielding line 340, and auxiliary structures such as an auxiliary line 150. Figure 5 The semiconductor device 300 described herein and Figure 2 The semiconductor device 100 described herein is substantially the same, and the following description will focus on the differences between semiconductor device 100 and semiconductor device 300.

[0048] According to an embodiment of the present invention, a shielding line 340 is configured to be spaced apart from and surrounding the semiconductor die 120. The shielding line 340 includes a first shielding line 341 formed across the semiconductor die 120 from one side to the other and a second shielding line 342 formed substantially perpendicular to the first shielding line 341. More specifically, compared to Figure 2 The semiconductor device 100 described herein, Figure 5 The semiconductor device 300 described further includes a second shielding line 342 formed substantially perpendicular to the first shielding line 341, the first shielding line 341 corresponding to Figure 2 The shielding line 140 of the semiconductor device 100 described herein. Therefore, compared to Figure 2 The semiconductor device 100 described herein, Figure 5 The semiconductor die 120 of the semiconductor device 300 described herein can exhibit improved EMI shielding performance. According to embodiments of the invention, the first shielding line 341 and the second shielding line 342 respectively comprise a plurality of first shielding lines and a plurality of second shielding lines. In some embodiments, when the second shielding line 342 is formed after the first shielding line 341 is formed, the second shielding line 342 may contact the first shielding line 341. Additionally, the first shielding line 341 and the second shielding line 342 may be electrically connected to the ground of the substrate 110. In some embodiments, the shielding line 340 may be configured to... Figure 2 The shielding line 140 described herein is generally the same, except that it includes a first shielding line 341 and a second shielding line 342 formed generally perpendicular to the first shielding line 341, and its detailed description will not be repeated.

[0049] Figure 6A This is a cross-sectional view of a semiconductor device 600 with an application auxiliary structure (e.g., auxiliary line 350) according to another embodiment, and Figure 6B and 6C for Figure 6A The semiconductor device 600 described herein is a plan view.

[0050] refer to Figure 6AAuxiliary line 350 may include one or more auxiliary lines. For example, such as Figure 6A As explained, two auxiliary lines 350 can support a single shielding line 140. Therefore, the auxiliary lines 350 can support the shielding line 140 more firmly than when using a single auxiliary line. According to one embodiment, the auxiliary lines 350 can be formed to be generally parallel to each other, such as... Figure 6B As explained in the text. Alternatively, as... Figure 6C As explained, auxiliary lines 350 can be formed by crossing each other or overlapping each other. Additionally, although in Figures 6A to 6C The specification states that an auxiliary line 350 contains two auxiliary lines, but it may contain more than two auxiliary lines.

[0051] Figure 7A This is a front view of an auxiliary structure (e.g., auxiliary line 450) according to one embodiment, and Figure 7B For application Figure 7A A perspective view of the semiconductor device 700 with auxiliary line 450 as described in the figure.

[0052] refer to Figure 7A and 7B The auxiliary line 450 includes a first support portion 451, a second support portion 452 spaced apart from the first support portion 451, and a planar portion 453 connecting the first support portion 451 and the second support portion 452 and formed as a plane. According to an embodiment of the invention, the planar portion 453 is configured to support one or more shielding lines 140. Therefore, one or more shielding lines 140 can contact the planar portion 453 in a planar manner. The first support portion 451 may be formed substantially perpendicular to the substrate 710, and the second support portion 452 may be formed inclined relative to the substrate 710.

[0053] Figure 8A This is a front view of the auxiliary line 450 according to another embodiment, and Figure 8B For application Figure 8A A perspective view of the semiconductor device 800 with auxiliary line 450 as illustrated.

[0054] refer to Figure 8A and 8B According to another embodiment of the invention, the auxiliary line includes a first auxiliary line 450 and a second auxiliary line 460. The first auxiliary line 450 and the second auxiliary line 460 are connected to each other and are formed symmetrically. Here, the first auxiliary line 450 is similar to... Figure 7A The auxiliary line 450 is shown in the diagram.

[0055] The first auxiliary line 450 includes a first support portion 451, a second support portion 452 spaced apart from the first support portion 451, and a planar portion 453 connecting the first support portion 451 and the second support portion 452 and formed as a plane. The second auxiliary line 460 includes a first support portion 461, a second support portion 462 spaced apart from the first support portion 461, and a planar portion 463 connecting the first support portion 461 and the second support portion 462 and formed as a plane. The first support portions 451 and 461 may be formed substantially perpendicular to the substrate 810, and the second support portions 452 and 462 may be formed inclined relative to the substrate 810. Furthermore, the first auxiliary line 450 and the second auxiliary line 460 may be coupled to each other, such that the second support portions 452 of the first auxiliary line 450 and the second support portions 462 of the second auxiliary line 460 are connected or in contact with each other. Additionally, each of the planar portions 453 of the first auxiliary line 450 and the second auxiliary line 460 supports one or more shielding lines 140. Therefore, one or more shielding lines 140 can contact the planar portions 453 of the first auxiliary line 450 and the second auxiliary line 460 in a planar manner. Furthermore, although in Figure 8A and 8B The diagram illustrates two intersecting auxiliary lines, 45° and 46°, but two or more auxiliary lines can be set. More precisely, an auxiliary line may contain multiple auxiliary lines that can intersect each other and can be arranged (for example) into a line.

[0056] Figure 9 This is a cross-sectional view of a semiconductor device 500 according to another embodiment. (Reference) Figure 9 The semiconductor device 500 includes a substrate 510, a semiconductor die 520, conductive lines 540, and auxiliary structures such as auxiliary lines 550.

[0057] In some embodiments, the semiconductor die 520 is mounted on or adjacent to the substrate 510. For example, the substrate 510 may be a printed circuit board (PCB) including an insulating layer and a plurality of circuit patterns formed on and / or within the insulating layer. Alternatively, the substrate 510 may be one of the group consisting of rigid printed circuit boards, flexible printed circuit boards, ceramic circuit boards, in-circuit inserts, and other structures as known to those skilled in the art. Furthermore, various types of substrates may be used in embodiments of the invention. In embodiments of the invention, a plurality of bonding pads 511 are formed on or adjacent to the substrate 510.

[0058] Semiconductor die 520 is mounted on or adjacent to substrate 510. In one embodiment, an adhesive member may be used to mount semiconductor die 520 onto substrate 510. Semiconductor die 520 may have the characteristics of different types of semiconductor dies. For example, semiconductor die 520 may include processor die, memory die, application-specific integrated circuit die, general-purpose logic die, active semiconductor assembly, and other electronic devices as known to those skilled in the art. Additionally, a plurality of bonding pads 521 are formed on or adjacent to the top surface of semiconductor die 520.

[0059] In embodiments of the invention, conductive wire 540 electrically connects semiconductor die 520 to substrate 510. More specifically, one end of conductive wire 540 is bonded to bonding pad 521 of semiconductor die 520, and the other and opposite end of conductive wire 540 is bonded to bonding pad 511 of substrate 510. Here, conductive wire 540 may be bonded to bonding pad 511 of substrate 510 while forming a sharper or steeper angle with auxiliary wire 550, which will be described in more detail later. In some embodiments, conductive wire 540 may comprise a plurality of conductive wires. Conductive wire 540 may be made of gold (Au), silver (Ag), copper (Cu) and / or other materials as known to those skilled in the art.

[0060] According to an embodiment of the invention, an auxiliary line 550 is positioned below and intersects with a conductive line 540. The auxiliary line 550 is formed substantially perpendicular to the conductive line 540 and positioned between the bonding pad 511 of the semiconductor die 520 and the substrate 510. Furthermore, because the auxiliary line 550 is formed below each of the plurality of conductive lines 540, the auxiliary lines 550 can be arranged in lines to be substantially parallel to each other. In some embodiments, the auxiliary line 550 has a width smaller than that of the conductive line 540 and is formed in an arc shape. Additionally, the thickness of the auxiliary line 550 may be equal to or greater than the thickness of the conductive line 540. In other embodiments, the auxiliary line 550 may be thicker than the conductive line 540.

[0061] According to an embodiment of the invention, the auxiliary line 550 supports the conductive line 540 and increases the angle at which the conductive line 540 is bonded to the bonding pad 511 of the substrate 510. More precisely, as Figure 9 As described, one end of the conductive line 540 is bonded to the bonding pad 521 of the semiconductor die 520, and the other end of the conductive line 540 is bonded to the bonding pad 511 of the substrate 510. When no auxiliary lines are present, the conductive line 540 needs to be bonded to... Figure 9The portion ending with the dashed line. For example, when no auxiliary line is present, the conductive line can be bonded to the bonding pad of the substrate at an angle of approximately 45 degrees. However, in this invention, the auxiliary line 550 is formed under the conductive line 540 so that the conductive line 540 contacts the auxiliary line 550. Therefore, the angle (a) at which the conductive line 540 bonds to the bonding pad 511 of the substrate 510 is increased more rapidly or sharply. More precisely, the conductive line 540 can be bonded to the bonding pad 511 of the substrate 510 at an angle in the range of approximately 70 degrees to approximately 90 degrees. In addition, according to an embodiment of the invention, as the auxiliary line 550 supports the conductive line 540 with an increased force, that is, as the thickness of the auxiliary line 550 becomes greater than the thickness of the conductive line 540, the conductive line 540 can be bonded to the bonding pad 511 of the substrate 510 at an angle of approximately 90 degrees. Therefore, according to an embodiment of the invention, the width of the conductive line 540 connecting the semiconductor die 520 to the substrate 510 can be reduced, thereby reducing the size of the semiconductor device 500. The auxiliary line 550 may be made of gold (Au), silver (Ag), copper (Cu), and / or other materials known to those skilled in the art. Alternatively, the auxiliary line 550 may be formed by further coating an insulating material onto the aforementioned metal. Therefore, short-circuiting of the auxiliary line 550 to components disposed in the semiconductor device 500 is prevented. Here, the insulating material coated on the auxiliary line 550 may be made of, for example, one selected from the group consisting of: polypropylene, polyethylene, polyimide, polycarbonate, and / or other materials known to those skilled in the art.

[0062] Alternatively, the auxiliary line 550 can also be formed in various shapes, including (for example) Figures 6A to 8B The shape described in the text.

[0063] Figure 10 This illustration shows a partial cross-sectional view of a semiconductor device 900 according to yet another embodiment, and... Figure 11 For filming Figure 10 A partial photo of "B". (Reference) Figure 10 The semiconductor device 900 includes a substrate 110, a semiconductor die 120, conductive lines (e.g., shielding lines 140), and auxiliary structures including a bump structure 160.

[0064] According to an embodiment of the invention, the bump structure 160 is formed adjacent to the substrate 110, such that the shielding wire 140 is positioned abutting against the bump structure 160 near or adjacent to the substrate 110 where it is attached to the second bonding pad 112. In a preferred embodiment, a portion of the shielding wire 140 directly contacts the bump structure 160 such that the bump structure 160 supports, sets, or facilitates a rapidly increasing or steeper angle at which the shielding wire 140 engages with the second bonding pad 112. According to an embodiment of the invention, the shielding wire 140 may engage with the second bonding pad 112 at an angle greater than about 50 degrees. For example, when no bump structure is present, the shielding wire may engage with the second bonding pad at an angle less than about 45 degrees.

[0065] In some embodiments, the bump structure 160 may be a bump ball formed on the second bonding pad 112 prior to the application of the shielding wire 140. The bump structure 160 may be made of gold (Au), silver (Ag), copper (Cu), and / or other materials known to those skilled in the art, and may be formed using, for example, ball bonding and tail removal techniques. In some embodiments, the second bonding pad 112 has a width of approximately 100 micrometers to accommodate the bump structure 160. It should be understood that the bump structure 160 may be used in combination with any of the embodiments described herein. For example, the shielding wire 140 may alternatively be a conductive interconnect, such as... Figure 10 The description further illustrates the conductive line 540 that is attached to one end of the bonding pad 521 on the semiconductor die 120.

[0066] As described above, a semiconductor device 900 according to an embodiment of the present invention includes a shielding line 140 spaced apart from a semiconductor die 120, and the shielding line may surround the semiconductor die 120, such as (for example). Figure 2 , 4 As further explained in section 5, the bump structure 160 is positioned against a portion of the shielding line 140, thereby reducing the distance between the semiconductor die 120 and other circuit devices (e.g., ...). Figure 1 The distance between the circuit devices 130 described herein serves to shield against electromagnetic interference generated from the semiconductor die 120. In one embodiment, this distance may be 100 micrometers or less. Therefore, the size of the semiconductor device 900 according to an embodiment of the invention can be reduced.

[0067] Figure 12 A partial cross-sectional view of a semiconductor device 1000 according to yet another embodiment is shown, and Figure 13 For filming Figure 12 A partial photo of the letter "C". (Reference) Figure 12The semiconductor device 1000 includes a substrate 110, a semiconductor die 120, conductive lines (e.g., shielding lines 140), and auxiliary structures (e.g., auxiliary lines 650), the auxiliary lines 650 having bump structure portions 260 and line portions 261 connected to the bump structure portions 260.

[0068] According to an embodiment of the invention, the bump structure portion 260 and the line portion 261 of the auxiliary line 650 together support the shielding line 140 and increase the angle at which the shielding line 140 engages with the second bonding pad 112. When no auxiliary line and bump structure are present, the shielding line can engage with the second bonding pad at an angle less than about 45 degrees. According to an embodiment of the invention, the line portion 261 of the auxiliary line 650 is formed under the shielding line 140, and the bump structure portion 260 of the auxiliary line 650 and the base of the shielding line 140 are formed adjacent to the second bonding pad 112, such that the shielding line 140 contacts both the line portion 261 and the bump structure portion 260. Therefore, the angle at which the shielding line 140 engages with the second bonding pad 112 increases rapidly or slopes more steeply. According to an embodiment of the invention, the shielding line 140 can engage with the second bonding pad 112 at an angle greater than about 80 degrees. In other embodiments, the shielding line 140 can engage with the second bonding pad at an angle in the range of about 70 degrees to about 90 degrees.

[0069] Furthermore, according to an embodiment of the invention, as the line portion 261 of the auxiliary line 150 supports the shielding line 140 with increased force, that is, as the thickness of the line portion 261 of the auxiliary line 150 becomes greater than the thickness of the shielding line 140, the shielding line 140 can be bonded to the second bonding pad 112 at an angle of approximately 90 degrees. Therefore, according to an embodiment of the invention, the distance between the semiconductor die 120 and adjacent circuit devices (e.g., Figure 1 The distance between the circuit devices 130 described herein reduces the size of the semiconductor device 1000. In one embodiment, this distance is 100 micrometers or less.

[0070] In some embodiments, the auxiliary line 650 includes a bump structure portion 260, and the line portion 261 may be made of gold (Au), silver (Ag), copper (Cu), and / or other materials known to those skilled in the art. Additionally, in some embodiments, the auxiliary line 650 may be formed by additionally coating an insulating material onto the aforementioned metal forming the auxiliary line 650. This prevents the auxiliary line 650 from shorting to elements disposed in the semiconductor device 1000. Here, the insulating material coated on the auxiliary line 650 may be made of, for example, one selected from the group consisting of: polypropylene, polyethylene, polyimide, polycarbonate, and / or other materials known to those skilled in the art. It should be understood that the auxiliary line 650 having the bump structure portion 260 and the line portion 261 may be used in combination with any of the embodiments described herein. For example, the shielding wire 140 may alternatively be a conductive interconnect, for example as... Figure 12 The description further illustrates a conductive line 540 that is attached to one opposite end of a bonding pad 521 on a semiconductor die 120. In some embodiments, a bump structure 260 is attached to a second bonding pad 112, and a line portion 261 is connected at one end to the bump structure 260 and at the other end to the second bonding pad 112.

[0071] In forming the embodiments described herein, it has been found that a capillary wire bonding tool with an extended bottleneck height is preferably used when forming conductive wires at steeper angles (e.g., conductive wires 140, 340, 540). Furthermore, this avoids contact with the wire itself or adjacent circuitry during the wire bonding process. In one embodiment, a capillary bottleneck height greater than about 450 micrometers has been found to be preferred compared to a conventional bottleneck height of about 250 micrometers.

[0072] From all the foregoing, those skilled in the art will recognize that, according to one embodiment of the semiconductor device, an auxiliary line is formed between the semiconductor die and the second bonding pad. In another embodiment, a shielding line is connected to the second bonding pad at an angle ranging from about 70 degrees to about 90 degrees. In yet another embodiment, the second bonding pad is positioned between the semiconductor die and the circuit device. In still another embodiment, the distance between the semiconductor die and the circuit device where the second bonding pad is positioned is less than about 100 micrometers.

[0073] In another embodiment, the auxiliary structure includes an auxiliary line; a shielding line physically contacts the auxiliary line; the shielding line is electrically connected to the ground of the substrate; the auxiliary line is thicker than the shielding line; both the shielding line and the auxiliary line are made of metal; and the auxiliary line further includes an insulating material coated on the metal.

[0074] In another embodiment, the auxiliary structure includes one or more auxiliary lines formed in an arc shape; and the one or more auxiliary lines are formed to be parallel to each other or intersect each other. In yet another embodiment, the auxiliary structure includes auxiliary lines including a first support portion perpendicular to the substrate; a second support portion spaced apart from the first support portion and formed to be inclined relative to the substrate; and a planar portion connecting the first support portion and the second support portion and formed as a plane.

[0075] In another embodiment, the planar portion supports one or more shielding lines. In yet another embodiment, the auxiliary lines comprise a plurality of auxiliary lines, and second supporting portions of the plurality of auxiliary lines are formed to intersect each other. In still another embodiment, the auxiliary structure includes a bump structure.

[0076] While various aspects of semiconductor devices according to the invention have been described with reference to certain supporting embodiments, those skilled in the art will understand that the invention is not limited to the specific embodiments disclosed, but rather should encompass all embodiments falling within the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Semiconductor components are mounted on the substrate; An auxiliary structure is attached to the substrate only along one side of the semiconductor component, the auxiliary structure including a portion that is detached from the substrate and extends upward away from the substrate; as well as The first shielding line includes an opposite end attached to the substrate, wherein: The first shielding line includes a loop formed above the main surface of the semiconductor component and spaced apart from the main surface of the semiconductor component; and The first shielding line extends through the main surface of the semiconductor component; The first shielding wire physically contacts the auxiliary structure at a location that is not at either of the opposite ends; and The auxiliary structure contacts the first shielding wire at a point laterally offset from the maximum height of the first shielding wire.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A circuit device, coupled to the substrate and spaced apart from the semiconductor component to provide space between the semiconductor component and the circuit device, wherein: The substrate includes a first bonding pad located on one side of the semiconductor component and a second bonding pad located on the opposite side of the semiconductor component; The auxiliary structure includes an auxiliary line, which includes a first end and an opposite second end; The first end and the opposite second end of the auxiliary line are attached to the substrate within the space; and The first shielding wire includes one end attached to the first bonding pad and the other end attached to the second bonding pad.

3. The semiconductor device as claimed in claim 1, characterized in that: The auxiliary structure includes: A first auxiliary line includes opposite ends attached to a first portion of the substrate along said side of the semiconductor assembly; and The second auxiliary line includes opposite ends attached to the second portion of the substrate; and The first shielding wire is in physical contact with the first auxiliary wire.

4. The semiconductor device as claimed in claim 3, characterized in that: The first shielding wire is in physical contact with the second auxiliary wire.

5. The semiconductor device as claimed in claim 3, characterized in that, Also includes: A second shielding line is attached to the substrate such that the second shielding line extends through the main surface of the semiconductor component, perpendicular to the first shielding line, and in physical contact with the second auxiliary line.

6. The semiconductor device as claimed in claim 3, characterized in that: One or more of the first auxiliary line and the second auxiliary line have an arched shape.

7. The semiconductor device as claimed in claim 3, characterized in that: The first auxiliary line overlaps with the second auxiliary line.

8. The semiconductor device as claimed in claim 1, characterized in that: The auxiliary structure includes auxiliary lines, which include: The bump structure part; and The line portion, which connects to the bump structure portion; and The first shielding wire makes physical contact with the bump structure portion.

9. The semiconductor device as claimed in claim 1, characterized in that: The substrate includes a main surface; and The first shielding line contacts the auxiliary structure and forms an angle with the main surface of the substrate.

10. The semiconductor device as claimed in claim 9, characterized in that: The angle is in the range of 70 to 90 degrees.

11. The semiconductor device as claimed in claim 1, characterized in that: The first shielding line contacts the auxiliary structure at a location different from the location covering the semiconductor component.

12. A semiconductor device, characterized in that, include: A substrate having a semiconductor component coupled to a surface of the substrate; An auxiliary line, coupled to the substrate, the auxiliary line including an arched line portion that is separated from the substrate and higher than the substrate; as well as A shielding line, comprising a loop spaced apart from the semiconductor component and connected to the substrate, wherein the shielding line physically contacts the auxiliary line to increase the angle at which the shielding line is connected to the substrate, wherein: The shielding line contacts the auxiliary line at a point where it is laterally offset from the maximum height of the shielding line.

13. The semiconductor device as claimed in claim 12, characterized in that: The semiconductor component includes a semiconductor die.

14. The semiconductor device as claimed in claim 12, characterized in that: The opposite ends of the auxiliary line are attached to the substrate such that a portion of the auxiliary line includes an arch.

15. The semiconductor device as claimed in claim 12, characterized in that: The auxiliary line includes a bump structure portion and a line portion connected to the bump structure portion.

16. The semiconductor device as claimed in claim 12, characterized in that: A portion of the shielding line is perpendicular to a portion of the auxiliary line.

17. A semiconductor device, characterized in that, include: Substrate, including the first side; Semiconductor components are mounted on the first side; A first auxiliary line is coupled adjacent to the first side, and the first auxiliary line includes a portion that is separated from the substrate and extends upward away from the first side; as well as The first shielding line includes an opposite end adjacent to and supported by the first side of the substrate. in: The first shielding line is spaced apart from and across the main surface of the semiconductor component. The first shielding wire is physically in contact with the first auxiliary wire at a location other than either end of the opposite ends of the first shielding wire; as well as The first shielding wire physically contacts the first auxiliary wire at a point where it is laterally offset from the maximum height of the first shielding wire.

18. The semiconductor device as claimed in claim 17, characterized in that: The first auxiliary line includes: The first support portion is perpendicular to the first side of the substrate; A second support portion, spaced apart from the first support portion and formed to be inclined relative to the first side of the substrate; and A third support portion, which connects the first support portion and the second support portion; and The third support portion is parallel to the first side of the substrate.

19. The semiconductor device as claimed in claim 17, characterized in that, Also includes: A second auxiliary line, which is adjacent to and coupled to the first side and close to the first auxiliary line, such that the first auxiliary line and the second auxiliary line intersect each other in the plan view, wherein: The location is close to where the first auxiliary line and the second auxiliary line intersect each other.

20. The semiconductor device as claimed in claim 17, characterized in that, Also includes: A second auxiliary line is coupled to the first side; as well as The second shielding wire includes an opposite end that is adjacent to and coupled to the first side and physically contacts the second auxiliary wire, such that the second auxiliary wire supports the second shielding wire, wherein: The first auxiliary line and the second auxiliary line are alternately connected to the first side of the substrate on the same side as the semiconductor component, such that one of the first auxiliary line or the second auxiliary line is laterally closer to the semiconductor component.

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