Radiation hardened triple modular redundant latch

Abstract

The application discloses an anti-radiation three-mode redundant latch, and belongs to the field of anti-radiation design of special integrated circuits. The application designs a novel main-stage latch and a novel redundant voting circuit, which comprises a first transistor-stage voting circuit, a second transistor-stage voting circuit and a protection gate circuit. The application reinforces the main-stage latch and the voting circuit from the circuit structure, enhances the resistance of the main-stage latch to SNU and DNU, reduces the influence of SNU of the voting circuit itself on the output result, and enhances the stability of the three-mode redundant system. The total number of MOS tubes of the redundant voting circuit of the application is only 30% of the total number of MOS tubes of the full three-mode redundant voting circuit, effectively reduces the area cost of the three-mode redundant system, and is more suitable for the anti-radiation design of super large scale integrated circuits.

Description

Technical Field

[0001] This invention relates to a radiation-resistant triple-modular redundancy latch, belonging to the field of radiation-resistant design of application-specific integrated circuits. Background Technology

[0002] Using electronic components in harsh space environments presents numerous reliability challenges. One of the main causes of failures in space CMOS integrated circuits is radiation-induced effects, which can be categorized into total iodine (TOD) and single-event effects (SEE). Advanced nanoscale process technologies offer greater tolerance to TOD, but as process technology advances, system complexity increases, leading to a higher error rate due to SEE. SEE primarily includes single-event pulse (SET) and single-event upset (SEU). A SET is a voltage spike generated at the combined gate output when incident particles deposit sufficient charge in the gate-sensitive region. These spikes can propagate to sequential cells and eventually cause the stored logic value to flip, known as a SEE. SEE SEE can be further classified as single-node upset (SNU), double-node upset (DNU), and CLK signal toggling. Since standard cell designs in any process cannot resist soft errors, radiation-hardened designs are employed to reduce the impact of SEE on integrated circuits.

[0003] Triple mode redundancy (TMR) technology, a common radiation protection technique, is widely used in industrial testing, space exploration, aerospace, and other fields. The principle of TMR is to duplicate the data requiring redundant protection three times and store them in a latch, then send the three identical sets of data to a majority voting circuit for voting and output. TMR increases circuit area in exchange for system stability. TMR is often used in applications with high stability requirements. Traditional TMR structures have poor resistance to single-event effects, offering only resistance to some SNUs (Signal Nullable Nullables) and offering no resistance to DNUs (Distributed Nullable Nullables) or CLK (Clearing and Throwing) signal toggles. Therefore, it is necessary to research and design TMR latches.

[0004] Triple-redundant latches can be divided into master-level latches and secondary voting circuits. Traditional triple-redundant latches use standard D latches as the master-level latch, which has the advantage of a smaller area but offers no resistance to single-event effects (SEE). The latch is only reinforced by the voting circuit. Traditional voting circuits consist of combinational logic circuits, which are highly susceptible to settling events (SET). If an SET occurs in the voting circuit, it directly causes the triple-redundant system output to flip incorrectly, leading to system malfunction. To increase the radiation resistance of the voting circuit, it would need to be replicated three times (i.e., a full triple-redundant latch), requiring at least 82 MOSFETs. This is unacceptable under strict area constraints. In existing designs, traditional triple-redundant voting circuits lack radiation resistance and are highly susceptible to SET, while full triple-redundant voting circuits consume a significant amount of area. Therefore, it is necessary to reinforce the triple-redundant latch to improve its reliability. Summary of the Invention

[0005] To increase the radiation resistance of the triple-modulus redundancy voting circuit while reducing its area, thereby increasing the reliability of the triple-modulus redundancy system, this invention provides a radiation-resistant triple-modulus redundancy latch, the technical solution of which is as follows:

[0006] The first objective of this invention is to provide a latch comprising: a first transmission gate 101, a second transmission gate 102, a DELAY delay unit 103, a first inverter 104, a second inverter 105, a third inverter 106, and a C unit 107 for increasing the discharge path.

[0007] The input terminal of the first transmission gate 101 is the latch input terminal, and the output terminal is connected to the input terminal of the second transmission gate 102, the input terminal of the DELAY delay unit 103, and the C unit 107 that adds a discharge path; the P-transistor control terminal and the N-transistor control terminal of the first transmission gate 101 are respectively connected to the clock inversion signal CLKN and the clock signal CLK.

[0008] The input terminal of the second transmission gate 102 is connected to the output terminal of the first transmission gate 101, the input terminal of the DELAY delay unit 103, and one of the input terminals of the C unit 107 that adds a discharge path; the output terminal of the second transmission gate 102 is connected to the output terminal of the first inverter 104; the P-transistor control terminal and the N-transistor control terminal of the second transmission gate 102 are respectively connected to the clock signal CLK and the clock inversion signal CLKN;

[0009] The input terminal of the DELAY delay unit 103 is connected to the output terminal of the first transmission gate 101 and the input terminal of the second transmission gate 102. The output terminal of the DELAY delay unit 103 is connected to another input terminal of the C unit 107 which adds a discharge path.

[0010] The output terminal of the C unit 107, which increases the discharge path, is connected to the input terminal of the first inverter 104, the input terminal of the second inverter 105, and the output terminal of the third inverter 106, and serves as the output terminal of the latch.

[0011] The output of the second inverter 105 is connected to the input of the third inverter 106, and their input and output are interconnected to form a holding circuit.

[0012] Optionally, the internal components of the C unit 107, which adds a discharge path, include: two PMOS transistors and two NMOS transistors; a discharge PMOS transistor drain is connected at the source-drain connection of the two PMOS transistors as a discharge path, and a discharge NMOS transistor drain is connected at the source-drain connection of the two NMOS transistors as a discharge path; the source of the discharge PMOS transistor is connected to GND, its gate is connected to the gate of the discharge path NMOS transistor, and the source of the discharge NMOS transistor is connected to VDD.

[0013] Optionally, for short-term toggling of the CLK signal:

[0014] If CLK is high and CLKN is low, the first transmission gate 101 is closed and the second transmission gate 102 is turned on, and the data is latched; if the single event effect causes CLK to flip to a transparent state for a short time, the DELAY delay unit 103 is combined with the C unit 107 which increases the discharge path, and the erroneous data pulse cannot pass through.

[0015] If CLK is low and CLKN is high, the first transmission gate 101 is turned on and the second transmission gate 102 is turned off, and the data is transparent. If the single-event effect causes CLK to flip to the latched state for a short time, the data is incorrectly latched. If the erroneous data pulse is too short, the two input terminals of the C unit 107 with the added discharge path are different, and the erroneous data cannot pass through.

[0016] Optionally, for a single-point flip SNU, if a single-particle pulse occurs inside the latch, the charge is discharged through two discharge paths.

[0017] Optionally, for a single-point flip SNU, if a single-particle pulse occurs at the input, and if the input is a normal data signal, it will not affect the data output. If the input pulse signal has a pulse width of 400ps or less, the output of the C unit 107 with the bleed path will be in a high-impedance state, and the erroneous flip signal cannot pass through the latch and will be filtered out in the latch.

[0018] The second objective of this invention is to provide a redundant voting circuit, comprising: a first transistor-level voting circuit, a second transistor-level voting circuit, and a protection gate circuit; the first transistor-level voting circuit and the second transistor-level voting circuit have the same structure, are connected in parallel, have an input terminal connected to an input signal, and have an output terminal connected to a protection gate circuit;

[0019] The first transistor-level voting circuit includes: a first PMOS transistor 201, a second PMOS transistor 202, a third PMOS transistor 203, a fourth PMOS transistor 204, a fifth PMOS transistor 205, a first NMOS transistor 206, a second NMOS transistor 207, a third NMOS transistor 208, a fourth NMOS transistor 209, and a fifth NMOS transistor 210;

[0020] The gate terminals of the first PMOS transistor 201, the second PMOS transistor 202, the third NMOS transistor 208, and the fourth NMOS transistor 209 are connected to the input signal A as input terminals of the redundant voting circuit; the gate terminals of the third PMOS transistor 203 and the fifth NMOS transistor 210 are connected to the input signal B as input terminals of the redundant voting circuit; the gate terminals of the fourth PMOS transistor 204, the fifth PMOS transistor 205, the first NMOS transistor 206, and the second NMOS transistor 207 are connected to the input signal C as input terminals of the redundant voting circuit.

[0021] The source terminals of the first PMOS transistor 201, the second PMOS transistor 202, and the third PMOS transistor 203 are interconnected to VDD, and the source terminals of the third NMOS transistor 208, the fourth NMOS transistor 209, and the fifth NMOS transistor 210 are interconnected to GND.

[0022] The source of the first PMOS transistor 201 is connected to the drain of the fourth PMOS transistor 204; the sources of the second PMOS transistor 202 and the third PMOS transistor 203 are connected to the drain of the fifth PMOS transistor 205; the source of the first NMOS transistor 206 is connected to the drain of the third NMOS transistor 208; and the source of the second NMOS transistor 207 is connected to the drain of the fourth NMOS transistor 209 and the fifth NMOS transistor 210.

[0023] The source terminals of the fourth PMOS transistor 204 and the fifth PMOS transistor 205 are connected to the drain terminals of the first NMOS transistor 206 and the second NMOS transistor 207 to serve as the output terminal OUT1 of the first transistor-level voting circuit.

[0024] Optionally, the protection gate circuit includes: a first MOSFET P201, a second MOSFET P202, a third MOSFET N201, and a fourth MOSFET N202;

[0025] The output terminal OUT1 of the first transistor-level voting circuit is connected to the gates of the first MOS transistor P201 and the third MOS transistor N201, and the output terminal OUT2 of the second transistor-level voting circuit is connected to the gates of the second MOS transistor P202 and the fourth MOS transistor N202.

[0026] The source of the second MOSFET P202 is connected to the drain of the fourth MOSFET N202 and serves as the output OUT of the redundant voting circuit.

[0027] A third objective of the present invention is to provide a radiation-resistant triple-modulus redundant latch, comprising: a latch of any of the above-mentioned types, and / or a redundant voting circuit of any of the above-mentioned types.

[0028] Optionally, the radiation-resistant triple-mode redundancy latch includes: a master latch and a redundant voting circuit;

[0029] The master-level latch includes: a first latch, a second latch, and a third latch; the first latch, the second latch, and the third latch are latches according to any one of claims 1-5;

[0030] The first latch, the second latch, and the third latch are connected in parallel. Their input terminals are all connected to the data input, and their output terminals are connected to the first transistor-level voting circuit and the second transistor-level voting circuit.

[0031] Optionally, the output of the first latch is connected to the first input terminal of the first transistor-level voting circuit and the second transistor-level voting circuit, the output terminal of the second latch is connected to the second input terminal of the first transistor-level voting circuit and the second transistor-level voting circuit, and the output terminal of the third latch is connected to the third output terminal of the first transistor-level voting circuit and the second transistor-level voting circuit.

[0032] The beneficial effects of this invention are:

[0033] First, this invention strengthens the main-stage latch and voting circuit with radiation resistance through circuit structure enhancement, improving the main-stage latch's resistance to SNU and DNU, reducing the impact of the voting circuit's own SNU on the output result, and enhancing the stability of the triple-modulus redundancy system. Second, the total number of MOSFETs in the novel redundant voting circuit of this invention is only a fraction of the total number of MOSFETs in a fully triple-modulus redundancy voting circuit. Figure 4 The 30% reduction shown effectively lowers the area overhead of the triple redundancy system, making it more suitable for radiation-resistant design of VLSI integrated circuits. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the novel master-level latch structure in this invention.

[0036] Figure 2 This is a schematic diagram of a transistor-level voting circuit.

[0037] Figure 3 This is a schematic diagram of the redundant voting circuit structure in this invention.

[0038] Figure 4 This is a schematic diagram of the radiation-resistant triple-mode redundancy latch structure in this invention.

[0039] Figure 5 This is a schematic diagram of the voting circuit in a traditional triple-modular redundancy system, along with the truth table of the voting circuit.

[0040] Figure 6 This is a schematic diagram of a fully triple-modulus redundant voting circuit.

[0041] Figure 7 The waveform diagrams are of the double exponential pulse current source required to simulate the single-event effect, where (a) is the transient current of the double exponential pulse current source and (b) is the voltage pulse generated by the pulse current across the source and drain terminals of the MOS transistor.

[0042] Figure 8 This is a waveform diagram of the latch after simulating the addition of a single-particle pulse.

[0043] Wherein, 101: first transmission gate; 102: second transmission gate; 103: DELAY delay unit; 104: first inverter; 105: second inverter; 106: third inverter;

[0044] 201: First PMOS transistor; 202: Second PMOS transistor; 203: Third PMOS transistor; 204: Fourth PMOS transistor; 205: Fifth PMOS transistor; 206: First NMOS transistor; 207: Second NMOS transistor; 208: Third NMOS transistor; 209: Fourth NMOS transistor; 210: Fifth NMOS transistor;

[0045] 211~220: The same as the components represented by 201~210 in the first transistor-level voting circuit;

[0046] P201: First MOSFET; P202: Second MOSFET; N201: Third MOSFET; N202: Fourth MOSFET. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0048] Example 1:

[0049] This embodiment provides a latch, such as Figure 1 As shown, it includes: a first transmission gate 101, a second transmission gate 102, a DELAY delay unit 103, a first inverter 104, a second inverter 105, a third inverter 106, and a C unit 107 for increasing the discharge path;

[0050] The input terminal of the first transmission gate 101 is the latch input terminal, and the output terminal is connected to the input terminal of the second transmission gate 102, the input terminal of the DELAY delay unit 103, and the C unit 107 that adds a discharge path; the P-transistor control terminal and the N-transistor control terminal of the first transmission gate 101 are respectively connected to the clock inversion signal CLKN and the clock signal CLK.

[0051] The input terminal of the second transmission gate 102 is connected to the output terminal of the first transmission gate 101, the input terminal of the DELAY delay unit 103, and one of the input terminals of the C unit 107 that adds a discharge path; the output terminal of the second transmission gate 102 is connected to the output terminal of the first inverter 104; the P-transistor control terminal and the N-transistor control terminal of the second transmission gate 102 are respectively connected to the clock signal CLK and the clock inversion signal CLKN;

[0052] The input terminal of the DELAY delay unit 103 is connected to the output terminal of the first transmission gate 101 and the input terminal of the second transmission gate 102. The output terminal of the DELAY delay unit 103 is connected to another input terminal of the C unit 107 which adds a discharge path.

[0053] The output terminal of the C unit 107, which increases the discharge path, is connected to the input terminal of the first inverter 104, the input terminal of the second inverter 105, and the output terminal of the third inverter 106, and serves as the output terminal of the latch.

[0054] The output of the second inverter 105 is connected to the input of the third inverter 106, and their input and output are interconnected to form a holding circuit.

[0055] The internal components of the C unit 107, which adds a discharge path, include two PMOS transistors and two NMOS transistors. A discharge PMOS transistor is connected to the drain of the two PMOS transistors at the source-drain connection point as a discharge path, and a discharge NMOS transistor is connected to the drain of the two NMOS transistors at the source-drain connection point as a discharge path. The source of the discharge PMOS transistor is connected to GND, and its gate is connected to the gate of the discharge path NMOS transistor. The source of the discharge NMOS transistor is connected to VDD.

[0056] In this embodiment, the latch is designed for short-term toggling of the CLK signal. If CLK is high and CLKN is low, transmission gate 101 is closed and transmission gate 102 is open, latching the data. If a single-event event causes CLK to briefly flip into a transparent state, the delay unit and C unit combine to prevent erroneous data pulses from passing through. If CLK is low and CLKN is high, transmission gate 101 is open and transmission gate 102 is closed, making the data transparent. If a single-event event causes CLK to briefly flip into a latched state, the data is incorrectly latched. Since the erroneous data pulse is too short, the two inputs of the C unit are different, preventing the erroneous data from passing through.

[0057] For single-point flipping SNUs, if the single-particle pulse occurs inside the latch, two pulse current discharge paths are added at the source-drain connection between the two P transistors in the C unit and at the source-drain connection between the two N transistors. This reduces charge accumulation and prevents the flipping of the C unit output from affecting the latch output. A hold circuit (composed of interconnected dual inverters) is added to the latch output to enhance output stability.

[0058] For a single-point toggle SNU, if a single-event pulse occurs at the input, the pulse width of the error toggle signal is within 400ps, while the clock period of the normal data signal is at least 20ns. The normal branch and the delay branch cannot simultaneously reach the input of the C unit. If the input normal data signal does not affect the data output, but if the input pulse signal has a pulse width of 400ps or less, the C unit output will be in a high-impedance state, and the error toggle signal cannot pass through the latch and will be filtered out in the latch.

[0059] Example 2:

[0060] This embodiment provides a redundant voting circuit, such as Figure 4 As shown, it includes: a first transistor-level voting circuit, a second transistor-level voting circuit, and a protection gate circuit; the first transistor-level voting circuit and the second transistor-level voting circuit have the same structure, are connected in parallel, have their input terminals connected to the input signal, and have their output terminals connected to the protection gate circuit;

[0061] The first transistor-level voting circuit is as follows: Figure 2 As shown, it includes: a first PMOS transistor 201, a second PMOS transistor 202, a third PMOS transistor 203, a fourth PMOS transistor 204, a fifth PMOS transistor 205, a first NMOS transistor 206, a second NMOS transistor 207, a third NMOS transistor 208, a fourth NMOS transistor 209, and a fifth NMOS transistor 210;

[0062] The gate terminals of the first PMOS transistor 201, the second PMOS transistor 202, the third NMOS transistor 208, and the fourth NMOS transistor 209 are connected to the input signal A as input terminals of the redundant voting circuit; the gate terminals of the third PMOS transistor 203 and the fifth NMOS transistor 210 are connected to the input signal B as input terminals of the redundant voting circuit; the gate terminals of the fourth PMOS transistor 204, the fifth PMOS transistor 205, the first NMOS transistor 206, and the second NMOS transistor 207 are connected to the input signal C as input terminals of the redundant voting circuit.

[0063] The source terminals of the first PMOS transistor 201, the second PMOS transistor 202, and the third PMOS transistor 203 are interconnected to VDD, and the source terminals of the third NMOS transistor 208, the fourth NMOS transistor 209, and the fifth NMOS transistor 210 are interconnected to GND.

[0064] The source of the first PMOS transistor 201 is connected to the drain of the fourth PMOS transistor 204; the sources of the second PMOS transistor 202 and the third PMOS transistor 203 are connected to the drain of the fifth PMOS transistor 205; the source of the first NMOS transistor 206 is connected to the drain of the third NMOS transistor 208; and the source of the second NMOS transistor 207 is connected to the drain of the fourth NMOS transistor 209 and the fifth NMOS transistor 210.

[0065] The source terminals of the fourth PMOS transistor 204 and the fifth PMOS transistor 205 are connected to the drain terminals of the first NMOS transistor 206 and the second NMOS transistor 207 to serve as the output terminal OUT1 of the first transistor-level voting circuit.

[0066] Protective gate circuits such as Figure 4 As shown, it includes: a first MOSFET P201, a second MOSFET P202, a third MOSFET N201, and a fourth MOSFET N202;

[0067] The output terminal OUT1 of the first transistor-level voting circuit is connected to the gates of the first MOS transistor P201 and the third MOS transistor N201, and the output terminal OUT2 of the second transistor-level voting circuit is connected to the gates of the second MOS transistor P202 and the fourth MOS transistor N202.

[0068] The source of the second MOSFET P202 is connected to the drain of the fourth MOSFET N202 and serves as the output OUT of the redundant voting circuit.

[0069] Implemented using standard CMOS 55nm process, traditional AND-OR voting circuits, such as Figure 5 As shown, in a standard digital library unit, a two-input AND gate uses 6 MOSFETs, and a three-input OR gate uses 8 MOSFETs. A traditional AND-OR voting circuit requires a total of 26 MOSFETs. The transistor-level voting circuit in this embodiment is as follows: Figure 2 The circuit shown uses a total of 10 MOSFETs, and the full triple-modulus redundancy voting circuit is as follows: Figure 6 As shown, the system consists of three parallel AND-OR voting circuits plus a protection gate circuit, using a total of 82 MOSFETs. The redundant voting circuit in this embodiment is as follows: Figure 3 A total of 24 MOSFETs are used. The area of ​​the novel redundant voting circuit mentioned in this embodiment is smaller than that of the traditional AND-OR type voting circuit and the full tri-mode redundant voting circuit, while the voting circuit is reinforced with redundancy.

[0070] The delay index, obtained from circuit simulation using a standard CMOS 55nm process, is the time difference between the input and output signals of the voting circuit, measured in ps. The simulation results are shown in Table 1. Figure 5The conventional AND-OR voting circuit shown has a delay of 41 ps, while the transistor-level voting circuit in this embodiment has a delay of 22 ps. Figure 6 The full tri-mode redundancy voting circuit shown has a delay of 63 ps, while the redundant voting circuit in this embodiment has a delay of 47 ps. The redundant voting circuit described in this invention has a reduced delay compared to the full tri-mode redundancy voting circuit, and it does not employ delay units, registers, or other time-domain hardening units, thus meeting the hardening design requirements for medium- and high-speed circuits.

[0071] Table 1 Comparison of simulation results

[0072]

[0073] As can be seen from the table above, the voting circuit in this embodiment achieves lower delay with fewer MOS transistors compared to existing voting circuits, thus effectively reducing area overhead while improving circuit stability.

[0074] Example 3:

[0075] This embodiment provides a radiation-resistant triple-mode redundancy latch, such as Figure 4 As shown, it includes: a master-level latch and a redundant voting circuit;

[0076] The master-level latch includes: a first latch, a second latch, and a third latch; the first latch, the second latch, and the third latch all adopt the latch described in Embodiment 1;

[0077] The first latch, the second latch, and the third latch are connected in parallel. Their input terminals are all connected to the data input, and their output terminals are connected to the first transistor-level voting circuit and the second transistor-level voting circuit.

[0078] The output of the first latch is connected to the first input terminal A of the first transistor-level voting circuit and the second transistor-level voting circuit. The output terminal of the second latch is connected to the second input terminal B of the first transistor-level voting circuit and the second transistor-level voting circuit. The output terminal of the third latch is connected to the third output terminal C of the first transistor-level voting circuit and the second transistor-level voting circuit.

[0079] The output OUT1 of the first transistor-level voting circuit is connected to the gate terminals of PMOS transistor P201 and NMOS transistor N201 in the protection gate circuit. The output OUT2 of the second transistor-level voting circuit is connected to the gate terminals of PMOS transistor P202 and NMOS transistor N202 in the protection gate circuit. The output OUT in the protection gate circuit serves as the output terminal of the redundant voting circuit.

[0080] To further verify the radiation resistance capability of the radiation-resistant triple-mode redundancy latch in this invention, this embodiment uses the Cadence Virtuoso simulator to simulate and verify the novel master-level latch in this embodiment under standard CMOS 55nm process.

[0081] Using a double exponential pulse current source, such as Figure 7 To simulate the level change caused by SET. The formula for the double exponential pulse current source model is as follows:

[0082]

[0083]

[0084]

[0085] Among them, I max Q is the peak current; tot α represents the total charge ionized when high-energy particles are incident on the semiconductor material; α is the time constant for charge collection of excess carriers; and β is the time constant for the initial establishment of the particle ionization track. In silicon devices, 1 pC / μm of charge corresponds to 96.608 MeV·cm⁻¹. 2 LET is the linear transfer quantity per mg. LET values ​​in the cosmic radiation environment range from 20 to 120 MeV·cm⁻¹. 2 Between / mg. The larger the linear transfer quantity (LET), the higher the corresponding radiation intensity. In the double exponential pulse current source model, LET is taken as 80 MeV·cm. 2 / mg. The radiation resistance of the novel master-level latch in this invention was verified by observing the level change at the output terminal of the novel master-level latch through simulation.

[0086] An HSPICE model was established and simulations were performed on a double exponential pulse current source. The simulation results are as follows: Figure 7 As shown. Figure 7 (a) represents the transient current of the double exponential pulse current source. Figure 7 (b) is the voltage pulse generated by the pulse current across the source and drain terminals of the MOS transistor, with a pulse width of approximately 400 ps.

[0087] Applying a double exponential pulse current source to the CLKN signal is equivalent to Figure 4The radiation-hardened triple-modulus redundant latch shown has multiple-point toggling, equivalent to latches 1, 2, and 3 simultaneously toggling their CLK signals from transparent to latched states. Short-pulse erroneous data cannot simultaneously reach both inputs of cell C. If a double-exponential pulse current source is applied to cell C, the pulse current generated by the P-transistor is discharged to GND, and the discharge current generated by the N-transistor is discharged to VDD, ensuring stable operation of cell C. If the pulse current source is applied to any transistor-level voting circuit within the redundant voting circuit, the two inputs of cell C in the redundant voting circuit will differ, maintaining the current state. The simulation diagram shows a 400ps pulse at the CLKN input of the main-stage latch circuit. However, the output OUT of the radiation-hardened triple-modulus redundant latch remains normal. Similarly, applying a pulse current source to the main-stage latch and the transistor voting circuit does not affect the output of the triple-modulus redundant system. As can be seen from the above, the radiation-resistant triple-mode redundancy latch in this invention can tolerate most SNU and CLK signal flips and some DNUs, thus enhancing the stability of the triple-mode redundancy system. The comparison results between this invention and existing latches are shown in Table 2.

[0088] Table 2. Tolerance of the radiation-resistant triple-modular redundancy latch of the present invention to SNU, CLK signal toggles and DNU compared with existing latches.

[0089] Tolerance SNU Tolerance DNU Tolerating short-term CLK flips Full Triple Redundancy Latch yes yes no Traditional triple-redundant latch yes no no DICE latch yes no no D latch no no No The structure proposed in this invention yes yes yes

[0090] Because the radiation-resistant triple-mode redundancy latch in this invention has a small area footprint and good radiation resistance, it is very suitable for use in ruggedized design of very large-scale integrated circuits.

[0091] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0092] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A latch, comprising: The latch includes: a first transmission gate (101), a second transmission gate (102), a DELAY delay unit (103), a first inverter (104), a second inverter (105), a third inverter (106), and a C unit (107) that increases the discharge path; The input terminal of the first transmission gate (101) is the input terminal of the latch, and the output terminal is connected to the input terminal of the second transmission gate (102), the input terminal of the DELAY delay unit (103), and the C unit (107) that increases the discharge path; the P-transistor control terminal and the N-transistor control terminal of the first transmission gate (101) are respectively connected to the clock inversion signal CLKN and the clock signal CLK; The input terminal of the second transmission gate (102) is connected to the output terminal of the first transmission gate (101), the input terminal of the DELAY delay unit (103), and one of the input terminals of the C unit (107) that adds a discharge path; the output terminal of the second transmission gate (102) is connected to the output terminal of the first inverter (104); the P-transistor control terminal and the N-transistor control terminal of the second transmission gate (102) are respectively connected to the clock signal CLK and the clock inversion signal CLKN; The input terminal of the DELAY delay unit (103) is connected to the output terminal of the first transmission gate (101) and the input terminal of the second transmission gate (102), and the output terminal of the DELAY delay unit (103) is connected to the other input terminal of the C unit (107) that increases the discharge path. The output terminal of the C unit (107) that increases the discharge path is connected to the input terminal of the first inverter (104), the input terminal of the second inverter (105) and the output terminal of the third inverter (106), and serves as the output terminal of the latch. The output terminal of the second inverter (105) is connected to the input terminal of the third inverter (106), and their input and output are interconnected to form a holding circuit.

2. The latch of claim 1, wherein, The internal components of the C unit (107) with the added discharge path include: two PMOS transistors and two NMOS transistors; a discharge PMOS transistor drain is connected at the source-drain connection of the two PMOS transistors as a discharge path, and a discharge NMOS transistor drain is connected at the source-drain connection of the two NMOS transistors as a discharge path; the source of the discharge PMOS transistor is connected to GND, the gate of which is connected to the gate of the discharge path NMOS transistor, and the source of the discharge NMOS transistor is connected to VDD.

3. The latch of claim 2, wherein, Regarding the short-term flipping of the CLK signal: If CLK is high and CLKN is low, the first transmission gate (101) is closed and the second transmission gate (102) is turned on, and the data is latched; if the single-event effect causes CLK to flip to a transparent state for a short time, the DELAY delay unit (103) and the C unit (107) that increases the discharge path are combined, and the erroneous data pulse cannot pass through; If the first transmission gate (101) is turned on and the second transmission gate (102) is turned off when CLK is low and CLKN is high, the data is transparent; if the single event effect causes CLK to flip to the latched state for a short time, the data is incorrectly latched, the erroneous data pulse is too short, the two input terminals of the C unit (107) that increases the discharge path are different, and the erroneous data cannot pass through.

4. The latch of claim 2, wherein, For a single-point flip SNU, if a single-particle pulse occurs inside the latch, the charge is discharged through the two discharge paths.

5. The latch according to claim 2, characterized in that, For a single-point flip SNU, if a single-particle pulse occurs at the input end, if the input normal data signal does not affect the data output, and if the input pulse signal has a pulse width of 400ps or less, the output of the C unit (107) that increases the discharge path will be in a high-impedance state, and the erroneous flip signal cannot pass through the latch and will be filtered out in the latch.

6. A redundant voting circuit, comprising: The redundant voting circuit includes: a first transistor-level voting circuit, a second transistor-level voting circuit, and a protection gate circuit; the first transistor-level voting circuit and the second transistor-level voting circuit have the same structure, are connected in parallel, have an input terminal connected to an input signal, and have an output terminal connected to the protection gate circuit. The first transistor-level voting circuit includes: a first PMOS transistor (201), a second PMOS transistor (202), a third PMOS transistor (203), a fourth PMOS transistor (204), a fifth PMOS transistor (205), a first NMOS transistor (206), a second NMOS transistor (207), a third NMOS transistor (208), a fourth NMOS transistor (209), and a fifth NMOS transistor (210); The gate terminals of the first PMOS transistor (201), the second PMOS transistor (202), the third NMOS transistor (208), and the fourth NMOS transistor (209) are connected to the input signal A as input terminals of the redundant voting circuit; the gate terminals of the third PMOS transistor (203) and the fifth NMOS transistor (210) are connected to the input signal B as input terminals of the redundant voting circuit; the gate terminals of the fourth PMOS transistor (204), the fifth PMOS transistor (205), the first NMOS transistor (206), and the second NMOS transistor (207) are connected to the input signal C as input terminals of the redundant voting circuit. The source terminals of the first PMOS transistor (201), the second PMOS transistor (202), and the third PMOS transistor (203) are interconnected to VDD, and the source terminals of the third NMOS transistor (208), the fourth NMOS transistor (209), and the fifth NMOS transistor (210) are interconnected to GND. The source of the first PMOS transistor (201) is connected to the drain of the fourth PMOS transistor (204), the source of the second PMOS transistor (202) and the third PMOS transistor (203) is connected to the drain of the fifth PMOS transistor (205), the source of the first NMOS transistor (206) is connected to the drain of the third NMOS transistor (208), and the source of the second NMOS transistor (207) is connected to the drain of the fourth NMOS transistor (209) and the fifth NMOS transistor (210). The source terminals of the fourth PMOS transistor (204) and the fifth PMOS transistor (205) are connected to the drain terminals of the first NMOS transistor (206) and the second NMOS transistor (207) to serve as the output terminal OUT1 of the first transistor-level voting circuit.

7. The redundant voting circuit of claim 6, wherein, The protection gate circuit includes: a first MOSFET (P201), a second MOSFET (P202), a third MOSFET (N201), and a fourth MOSFET (N202); The output terminal OUT1 of the first transistor-level voting circuit is connected to the gates of the first MOS transistor (P201) and the third MOS transistor (N201), and the output terminal OUT2 of the second transistor-level voting circuit is connected to the gates of the second MOS transistor (P202) and the fourth MOS transistor (N202). The source of the second MOS transistor (P202) is connected to the drain of the fourth MOS transistor (N202) and serves as the output OUT of the redundant voting circuit.

8. A radiation-hardened triple modular redundant latch, comprising: The radiation-resistant triple-mode redundancy latch includes: the latch according to any one of claims 1-5, and / or the redundant voting circuit according to any one of claims 6-7.

9. The radiation-resistant triple-mode redundancy latch according to claim 8, characterized in that, The radiation-resistant triple-mode redundancy latch includes: a master latch and a redundant voting circuit; The master-level latch includes: a first latch, a second latch, and a third latch; the first latch, the second latch, and the third latch are the latches described in any one of claims 1-5; The first latch, the second latch, and the third latch are connected in parallel, with their input terminals all connected to the data input and their output terminals connected to the first transistor-level voting circuit and the second transistor-level voting circuit.

10. The radiation-hardened triple modular redundant latch of claim 9, wherein, The output of the first latch is connected to the first input terminal of the first transistor-level voting circuit and the second transistor-level voting circuit, the output terminal of the second latch is connected to the second input terminal of the first transistor-level voting circuit and the second transistor-level voting circuit, and the output terminal of the third latch is connected to the third output terminal of the first transistor-level voting circuit and the second transistor-level voting circuit.

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