A speed limit mode switching method and device, electronic equipment and storage medium

Abstract

The application discloses a speed-limiting mode switching method and device, electronic equipment and a storage medium. The method comprises the following steps: matching the messages sent to the CPU in different types of messages, and keeping the messages sent to the CPU in each type at a corresponding speed; mapping the messages sent to the CPU in different types to the same message queue; and configuring the traffic shaping parameter value of the message queue, so as to switch the speed-limiting mode to a separate speed-limiting mode or a whole speed-limiting mode. The application can quickly and stably complete the switching between the separate speed-limiting mode and the whole speed-limiting mode, shorten the switching time, and ensure the stability of the network environment.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and in particular to a method for switching between individual rate limiting modes and an overall rate limiting module, as well as an apparatus, electronic device, and storage medium for implementing the method. Background Technology

[0002] In communication networks, switches are common packet forwarding devices. Internally, multiple different types of chips work together to forward packets. For example... Figure 1 As shown, these chips mainly include CPU chips, switching and forwarding chips, and physical media-related chips. The packets processed by the switch can be divided into protocol packets and service packets. Protocol packets refer to the packets required for protocol operation, which usually need to be sent to the CPU for processing; while service packets refer to the packets that need to be transmitted for a specific service, which are usually forwarded directly by the switching and forwarding chips. However, the number of packets that a CPU can process per unit of time is limited. A large influx of protocol packets can easily cause excessive CPU utilization, leading to system performance degradation or even crashes. Therefore, it is necessary to rate-limit the packets sent to the CPU to ensure that CPU utilization remains within a reasonable range.

[0003] Currently, rate limiting for packets sent to the CPU typically employs CoPP (Control Plain Protection) and CPU Traffic (CPU Traffic Control) rate limiting methods. CoPP rate limiting uses ACL (Access Control List) entries to achieve this. Different packet types can be matched with different ACL entries. If different flow rate limiting action templates are bound, each packet type is rate-limited individually; if the same flow rate limiting action template is bound, all packets of different types are rate-limited. For example, if packets sent to the CPU are packet 1, packet 2, and packet 3, the corresponding matching access control list entries would be ACL entry 1, ACL entry 2, and ACL entry 3, respectively. Figure 2 As shown, if the flow rate limiting action templates corresponding to the three ACL entries are flow rate limiting action template 1, flow rate limiting action template 2, and flow rate limiting action template 3, then different types of packets are rate-limited separately; for example... Figure 3 As shown, if the flow rate limiting action templates corresponding to the rate limiting actions of the three ACL entries are all flow rate limiting action template 2, then the overall rate limiting of different types of packets is achieved.

[0004] like Figure 4As shown, in practical applications, the switching between individual rate limiting mode and overall rate limiting mode is as follows: unbind from the original flow rate limiting action template, and then rebind to the corresponding flow rate limiting action template. For example, when switching from individual rate limiting mode to overall rate limiting mode, firstly, each access control list entry is unbound from the original flow rate limiting action template, and finally, each access control list entry is bound to the same flow rate limiting action template. When switching from overall rate limiting mode to individual rate limiting mode, firstly, each access control list entry is unbound from the original flow rate limiting action template, and finally, each access control list entry is bound to its corresponding flow rate limiting action template. However, each flow state switch requires two actions: unbinding the existing template and rebinding the new one. Assuming the time required for one binding action is t1, and the time required for one unbinding action is t2, with n flows, the time required to complete one switch between individual and overall rate limiting is T = (n-1)*(t1+t2). Therefore, the more types of flows there are, the longer the switching time, the longer the intermediate state, the worse the convergence, and the more uncertainties are generated. Furthermore, during the transition from overall rate limiting to individual rate limiting, the increased number of required flow rate limiting action templates may lead to switching failure due to insufficient template resources.

[0005] Combination Figure 5 and Figure 6 As shown, CPU Traffic achieves rate limiting by shaping the queues through which packets pass. Through mapping configurations, different types of packets can enter different queues or the same queue. Traffic shaping can be configured based on queues; if packets enter different queues, rate limiting can be applied individually; if they enter the same queue, rate limiting can be applied to all packets of different types. Figure 5 As shown, the packets sent to the CPU are packet header 1, packet 2, and packet 3. When implementing individual rate limiting, they are mapped to different packet queues, namely packet queue 1, packet queue 2, and packet queue 3. The traffic shaping parameters for these three packet queues are configured as traffic shaping parameter 1, traffic shaping parameter 2, and traffic shaping parameter 3, respectively, thus enabling individual rate limiting for different types of traffic sent to the CPU. When implementing overall rate limiting, the three types of packets are mapped to the same packet queue, namely packet queue 1. Therefore, only traffic shaping parameter 1 will take effect, ultimately achieving overall rate limiting for different types of traffic sent to the CPU.

[0006] like Figure 7As shown, in practical applications, the switching between individual rate limiting mode and overall rate limiting mode involves readjusting the mapping relationship between packet types and packet queues. For example, when switching from individual rate limiting mode to overall rate limiting mode, different types of packets are first mapped to the same packet queue, and finally, queue traffic shaping is configured for that packet queue. When switching from overall rate limiting mode to individual rate limiting mode, different types of packets are first mapped to different packet queues, and finally, queue traffic shaping is configured for each packet queue separately. However, each flow's state transition requires one action: reconfiguring the mapping relationship between packet types and packet queues. Assuming the time required for one mapping action is t, with n flows, the time to complete one individual rate limiting and overall rate limiting cycle is T = (n-1)*t. Therefore, the more types of flows there are, the longer the switching time, the longer the intermediate state, the worse the convergence, and the more uncertainties arise.

[0007] As can be seen from the above, in both CoPP rate limiting and CPU Traffic rate limiting methods, as the types of traffic increase, the switching time becomes longer, the intermediate state becomes longer, the convergence becomes worse, and the number of uncertainties increases.

[0008] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0009] The purpose of this invention is to provide a method, device, electronic device, and storage medium for switching speed limiting modes, which can quickly and stably complete the switching between individual speed limiting modes and overall speed limiting modes, shorten the switching time, and ensure the stability of the network environment.

[0010] To achieve the above objectives, embodiments of the present invention provide a rate limiting mode switching method. The rate limiting modes include a separate rate limiting mode for maintaining a corresponding rate for each type of packet and an overall rate limiting mode for maintaining the same rate for all types of packets. The rate limiting mode switching method includes:

[0011] Match the different types of messages sent to the CPU, and ensure that each type of message sent to the CPU maintains the corresponding speed;

[0012] Map different types of messages sent to the CPU to the same message queue;

[0013] Configure the traffic shaping parameter value of the packet queue to switch the rate limiting mode to individual rate limiting mode or overall rate limiting mode.

[0014] In one or more embodiments of the present invention, the step of matching different types of messages sent to the CPU and maintaining a corresponding speed for each type of message sent to the CPU includes:

[0015] The ACL entries are used to match different types of packets sent to the CPU. Different types of packets are matched with corresponding ACL entries. Each ACL entry is used to ensure that the matched packets sent to the CPU maintain a certain speed.

[0016] In one or more embodiments of the present invention, the packets sent to the CPU by the matched ACL entries may be at the same or different speeds.

[0017] In one or more embodiments of the present invention, configuring the traffic shaping parameter value of the packet queue to switch the rate limiting mode to a separate rate limiting mode or an overall rate limiting mode includes:

[0018] When the traffic shaping parameter of the packet queue is configured to the maximum value, the rate limiting mode is switched to the individual rate limiting mode;

[0019] When the traffic shaping parameter of the packet queue is configured to the desired value, the rate limiting mode is switched to the overall rate limiting mode, where the desired value is less than the maximum value.

[0020] Embodiments of the present invention also provide a rate limiting mode switching device, wherein the rate limiting modes include a separate rate limiting mode for maintaining a corresponding rate for each type of packet and an overall rate limiting mode for maintaining the same rate for all types of packets, and the rate limiting mode switching device includes:

[0021] The matching module is used to match different types of messages sent to the CPU and ensure that each type of message sent to the CPU maintains the corresponding speed.

[0022] The mapping module is used to map different types of packets sent to the CPU to the same packet queue;

[0023] The configuration module is used to configure the traffic shaping parameter value of the packet queue to switch the rate limiting mode to individual rate limiting mode or overall rate limiting mode.

[0024] In one or more embodiments of the present invention, the matching module matches different types of packets sent to the CPU through ACL entries. Different types of packets are matched with corresponding ACL entries, and each ACL entry is used to keep the matched packets sent to the CPU at a corresponding speed.

[0025] In one or more embodiments of the present invention, the packets sent to the CPU by the matched ACL entries may be at the same or different speeds.

[0026] In one or more embodiments of the present invention, when the configuration module configures the traffic shaping parameter value of the packet queue to the maximum value, the rate limiting mode is switched to individual rate limiting mode; when the configuration module configures the traffic shaping parameter value of the packet queue to the expected value, the rate limiting mode is switched to overall rate limiting mode, wherein the expected value is less than the maximum value.

[0027] An embodiment of the present invention also provides an electronic device, characterized in that the electronic device comprises:

[0028] At least one processor;

[0029] At least one memory is coupled to the at least one processor and stores a computer program for execution by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform the method described above.

[0030] Embodiments of the present invention also provide a computer-readable storage medium, characterized in that it stores a computer program thereon, which, when executed by a machine, implements the method described above.

[0031] Compared with the prior art, the present invention has the following advantages:

[0032] (1) Switching between individual rate limiting mode and overall rate limiting mode can be achieved simply by configuring the traffic shaping parameter value of the packet queue, making the operation process simple. Furthermore, the switching between individual rate limiting mode and overall rate limiting mode is not affected by the flow rate limiting action template resources, making it applicable to more scenarios.

[0033] (2) The switching time between individual rate limiting mode and overall rate limiting mode is constant and does not change with the number of packet types. The intermediate state is short, which is beneficial to the stability of the network environment. In addition, corresponding packets enter the same packet queue, and other packet queues are not affected, resulting in lower coupling.

[0034] (3) In the individual rate limiting mode, the individual rate limiting values ​​of various messages can be configured separately. In the overall rate limiting mode, the overall rate limiting value can also be configured separately, making the configuration more flexible. Attached Figure Description

[0035] Figure 1 This is a diagram illustrating how a switching device processes messages.

[0036] Figure 2 This is a schematic diagram of the individual speed limiting process in the CoPP speed limiting method;

[0037] Figure 3 This is a schematic diagram of the overall speed limiting process in the CoPP speed limiting method;

[0038] Figure 4This is a flowchart showing the switching process between individual speed limiting and overall speed limiting in the CoPP speed limiting method;

[0039] Figure 5 This is a schematic diagram of the separate rate limiting process in CPU Traffic shaping.

[0040] Figure 6 This is a schematic diagram of the overall rate limiting process in CPU Traffic shaping.

[0041] Figure 7 This is a flowchart showing the switching process between individual rate limiting and overall rate limiting in CPU Traffic shaping.

[0042] Figure 8 This is a flowchart of a speed limiting mode switching method in one embodiment of the present invention;

[0043] Figure 9 This is a schematic diagram of the switching chip structure;

[0044] Figure 10 This is a flowchart illustrating the process of switching the speed limiting mode to a separate speed limiting mode in one embodiment of the present invention;

[0045] Figure 11 This is a flowchart of switching the speed limiting mode to overall speed limiting in one embodiment of the present invention;

[0046] Figure 12 This is a structural block diagram of a speed limiting mode switching device in one embodiment of the present invention;

[0047] Figure 13 This is a block diagram of an electronic device structure according to an embodiment of the present invention. Detailed Implementation

[0048] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0049] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0050] like Figure 8As shown, a rate limiting mode switching method according to a preferred embodiment of the present invention can quickly and stably complete the switching between individual rate limiting mode and overall rate limiting mode, shorten the switching time, and ensure the stability of the network environment. Here, individual rate limiting mode is a rate limiting mode used to maintain a corresponding speed for each type of packet. For example, for packets 1, 2, and 3, in individual rate limiting mode, the speed corresponding to packet 1 is speed one, the speed corresponding to packet 2 is speed two, and the speed corresponding to packet 3 is speed three. Overall rate limiting mode is a rate limiting mode that maintains a corresponding speed for all types of packets. For example, for packets 1, 2, and 3, in overall rate limiting mode, the speed corresponding to packets 1, 2, and 3 is all speed four.

[0051] The rate limiting mode switching method described in this invention is implemented by combining CoPP rate limiting and CPU Traffic shaping. This rate limiting mode switching method includes the following steps:

[0052] First, the different types of messages sent to the CPU are matched, and each type of message sent to the CPU is kept at the corresponding speed.

[0053] Specifically, in a network, there are various types of messages, each with its own unique characteristics. Some messages, such as protocol messages, need to be sent to the CPU for processing, while others, such as service messages, do not. Due to the diversity of messages, the messages sent to the CPU for processing also exhibit diversity.

[0054] To achieve rapid and stable switching between individual rate limiting mode and overall rate limiting mode, this invention first performs CoPP rate limiting, which involves matching different types of packets that need to be sent to the CPU for processing, and setting corresponding speeds for the matched packets sent to the CPU based on their different types. In other words, different types of packets sent to the CPU are rate-limited separately. For example, if packets 1, 2, and 3 are matched and need to be sent to the CPU for processing, then three different speeds can be set for each of the three types of packets.

[0055] In this embodiment, as Figure 9 As shown, the CoPP rate limiting process described above is performed in the inbound direction parsing module of the switching chip, specifically in the latter part of the inbound direction parsing module.

[0056] Furthermore, during matching, packets can be matched using ACL entries to identify packets sent to the CPU and set corresponding rates for them. For example, packets 1, 2, and 3 correspond to ACL entries 1, 2, and 3, respectively. Each ACL entry can apply a rate-limiting action to the matched packets sent to the CPU. For example, the flow rate-limiting action templates corresponding to the rate-limiting actions of the three ACL entries are Flow Rate-Limiting Action Template 1, Flow Rate-Limiting Action Template 2, and Flow Rate-Limiting Action Template 3. That is, Flow Rate-Limiting Action Template 1 limits the rate of packet 1, Flow Rate-Limiting Action Template 2 limits the rate of packet 2, and Flow Rate-Limiting Action Template 3 limits the rate of packet 3.

[0057] Secondly, different types of messages sent to the CPU are mapped to the same message queue;

[0058] Finally, configure the traffic shaping parameter value of the message queue to switch the rate limiting mode to individual rate limiting mode or overall rate limiting mode.

[0059] Specifically, after CoPP rate limiting, CPU Traffic shaping is further performed, that is, after different types of packets are individually rate-limited, CPU Traffic shaping is further performed on them.

[0060] When performing CPU traffic shaping, different types of rate-limited packets are mapped to the same packet queue. In other words, rate-limited packets of different types are sent to the same queue; for example, rate-limited packets 1, 2, and 3 are all mapped to the packet queue_x. During implementation, any individual packet queue can have attributes set for the packets entering it, such as configuring high scheduling priority or configuring traffic shaping actions.

[0061] When rate-limited packets of different types are mapped to the same packet queue, corresponding traffic shaping parameters are configured for that packet queue to switch the rate-limiting mode to either individual rate-limiting or overall rate-limiting. In other words, switching between individual and overall rate-limiting modes is achieved by configuring the traffic shaping parameters of the packet queue. For example, configuring traffic shaping parameters for the packet queue_x enables switching between individual and overall rate-limiting modes.

[0062] In this invention, such as Figure 10As shown, when switching from rate limiting mode to individual rate limiting mode, simply set the traffic shaping parameter value of the packet queue to the maximum value (maximum rate limiting is equivalent to no rate limiting). That is to say, since different types of packets sent to the CPU have already undergone individual rate limiting during CoPP rate limiting, and no further rate limiting is performed during CPU Traffic shaping, the effect of individual rate limiting for different types of traffic sent to the CPU can be achieved, thus switching the rate limiting mode to individual rate limiting mode.

[0063] like Figure 11 As shown, when switching from rate limiting mode to overall rate limiting mode, simply set the traffic shaping parameter value of the packet queue to the desired value, which is less than the maximum value. In other words, since different types of packets sent to the CPU have already undergone individual rate limiting during CoPP rate limiting, performing rate limiting again during CPU Traffic shaping achieves the effect of overall rate limiting for different types of traffic sent to the CPU, thus switching from rate limiting mode to overall rate limiting mode.

[0064] In this invention, when using a combination of CoPP rate limiting and CPU Traffic shaping for rate limiting, the essential difference between individual rate limiting and overall rate limiting lies in whether the mapped packet queue is configured with the maximum traffic shaping parameter value. If the maximum traffic shaping parameter value is configured, it is individual rate limiting; if the user-desired traffic shaping parameter value is configured, it is overall rate limiting. Therefore, the method for switching between individual and overall rate limiting is to readjust the traffic shaping parameter value of the mapped packet queue. To switch from individual rate limiting to overall rate limiting, the original packet queue's traffic shaping parameter value needs to be configured to a user-desired rate limiting value; to switch from overall rate limiting to individual rate limiting, the original packet queue's traffic shaping parameter value needs to be configured to the maximum value.

[0065] The rate limiting mode switching method described in this invention only requires configuring the traffic shaping parameter value of the packet queue when switching between individual rate limiting mode and overall rate limiting mode, making the operation simple. Furthermore, the switching between individual and overall rate limiting modes is not affected by flow rate limiting action template resources, making it applicable to a wider range of scenarios.

[0066] Furthermore, in this invention, the switching time between individual rate limiting mode and overall rate limiting mode is constant and does not change based on the number of packet types. The short intermediate state is beneficial for network stability. Moreover, corresponding packets enter the same packet queue, while other packet queues are unaffected, resulting in lower coupling.

[0067] Furthermore, in this invention, in the individual rate limiting mode, the individual rate limiting values ​​for various messages can be configured individually, and in the overall rate limiting mode, the overall rate limiting value can also be configured individually, making the configuration more flexible.

[0068] like Figure 12 As shown, a rate limiting mode switching device according to a preferred embodiment of the present invention can realize the rate limiting mode switching method described above, and can quickly and stably complete the switching between individual rate limiting mode and overall rate limiting mode, shorten the switching time, and ensure the stability of the network environment. Specifically, the rate limiting mode switching device includes a matching module, a mapping module, and a configuration module. The matching module is used to match packets of different types sent to the CPU and maintain the corresponding speed for each type of packet sent to the CPU; the mapping module is used to map packets of different types sent to the CPU to the same packet queue; the configuration module is used to set the traffic shaping parameter values ​​of the packet queue to switch the rate limiting mode to individual rate limiting mode or overall rate limiting mode. How each module implements its corresponding function is detailed above and will not be repeated here.

[0069] In this embodiment, the matching module is preferably located in the ingress direction parsing module; the mapping module and the configuration module are preferably located in the scheduling module.

[0070] like Figure 13 As shown, an electronic device according to a preferred embodiment of the present invention can implement the above-described rate-limiting mode switching method. The electronic device may include, but is not limited to, personal computers, server computers, workstations, desktop computers, laptop computers, notebook computers, mobile electronic devices, smartphones, tablet computers, cellular phones, personal digital assistants (PDAs), handheld devices, messaging devices, wearable electronic devices, consumer electronic devices, etc. This electronic device can implement the above-described rate-limiting mode switching method, quickly and stably completing the switching between individual rate-limiting modes and overall rate-limiting modes, shortening the switching time, and ensuring the stability of the network environment. Specifically, the electronic device includes at least one memory, at least one processor, and a computer program. The at least one memory is coupled to the at least one processor, wherein the computer program is stored in the memory and can be run in the processor, such as the rate-limiting mode switching program. In implementation, when the processor executes the computer program, it can implement various steps in the above method, such as matching different types of messages sent to the CPU and maintaining a corresponding speed for each type of message sent to the CPU, etc.

[0071] The computer program here can be divided into one or more units, which are stored in the memory and executed by the memory to complete the present invention. The one or more units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the electronic device.

[0072] It should be noted that the electronic devices mentioned here include, but are not limited to, the memory, processor, and computer program described above. They may also include other devices, such as input devices (e.g., keyboards) for inputting predictive information, communication interfaces, etc. These components communicate with each other via a bus.

[0073] This invention also discloses a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the aforementioned speed-limiting mode switching method. The computer program includes computer program code, which can be in the form of source code, an executable file, or some intermediate form. The computer-readable medium can include any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), etc.

[0074] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0076] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0077] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0078] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A method for switching speed limiting modes, characterized in that, The rate limiting modes include a separate rate limiting mode for maintaining a corresponding rate for each type of message and an overall rate limiting mode for maintaining the same rate for all types of messages. The rate limiting mode switching method includes: Match the different types of messages sent to the CPU, and ensure that each type of message sent to the CPU maintains the corresponding speed; Map different types of messages sent to the CPU to the same message queue; Configure the traffic shaping parameter value of the packet queue to switch the rate limiting mode to individual rate limiting mode or overall rate limiting mode, wherein, The process of matching different types of messages sent to the CPU and maintaining a corresponding speed for each type of message sent to the CPU includes: The ACL entries are used to match different types of packets sent to the CPU. Different types of packets are matched with corresponding ACL entries. Each ACL entry is used to ensure that the matched packets sent to the CPU maintain a corresponding speed. Configuring the traffic shaping parameter values ​​of the packet queue to switch the rate limiting mode to a separate rate limiting mode or an overall rate limiting mode includes: When the traffic shaping parameter of the packet queue is configured to the maximum value, the rate limiting mode is switched to the individual rate limiting mode; When the traffic shaping parameter of the packet queue is configured to the desired value, the rate limiting mode is switched to the overall rate limiting mode, where the desired value is less than the maximum value.

2. The speed limiting mode switching method as described in claim 1, characterized in that, The packets sent to the CPU by several of the ACL entries matched may be at the same or different speeds.

3. A speed limiting mode switching device, characterized in that, The rate limiting modes include a separate rate limiting mode for maintaining a corresponding rate for each type of message and an overall rate limiting mode for maintaining the same rate for all types of messages. The rate limiting mode switching device includes: The matching module is used to match different types of packets sent to the CPU and to maintain the corresponding speed for each type of packet sent to the CPU. The matching module matches different types of packets sent to the CPU through ACL entries. Different types of packets are matched with corresponding ACL entries. Each ACL entry is used to maintain the corresponding speed for the matched packets sent to the CPU. The mapping module is used to map different types of packets sent to the CPU to the same packet queue; The configuration module is used to configure the traffic shaping parameter value of the packet queue to switch the rate limiting mode to a separate rate limiting mode or an overall rate limiting mode. When the configuration module configures the traffic shaping parameter value of the packet queue to the maximum value, the rate limiting mode is switched to a separate rate limiting mode. When the configuration module configures the traffic shaping parameter value of the packet queue to the expected value, the rate limiting mode is switched to an overall rate limiting mode. The expected value is less than the maximum value.

4. The speed limiting mode switching device as described in claim 3, characterized in that, The packets sent to the CPU by several of the ACL entries matched may be at the same or different speeds.

5. An electronic device, characterized in that, The electronic device includes: At least one processor; At least one memory coupled to the at least one processor and storing a computer program for execution by the at least one processor, the computer program, when executed by the at least one processor, causing the electronic device to perform the method according to any one of claims 1 to 2.

6. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a machine, implements the method according to any one of claims 1 to 2.

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