A method for obtaining parasitic capacitance fluctuation model of FinFET

Abstract

The present invention discloses a method for obtaining a parasitic capacitance fluctuation model of a FinFET. The parasitic capacitance analytical model is obtained by using the electric field distribution of the FinFET obtained through TCAD simulation, and then the statistical impedance field method is used to obtain data on the parasitic capacitance affected by process fluctuations. After the simulation data is calibrated and fitted, a parasitic capacitance fluctuation model that takes into account process fluctuations is generated. This method can reduce the large amount of calculations required to simulate process fluctuations, and can more accurately express the impact of process fluctuations on parasitic capacitance in the form of statistical distribution. Through the FinFET parasitic capacitance fluctuation model, the fluctuation of parasitic capacitance can be estimated without a large amount of calculations, solving problems such as threshold, failure rate, and yield rate of circuit design under process fluctuation conditions.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor TCAD (Technology Computer Aided Design) and particularly relates to a method for obtaining a FinFET parasitic capacitance fluctuation model by using simulation. Background Art

[0002] The advent of Fin Field-Effect Transistors (FinFETs) has enabled transistors to shrink to the nanoscale, reaching levels below 10 nanometers. However, this reduction in size has significantly increased the impact of process fluctuations on nanoscale devices. Lattice defects and uneven doping, caused by physical uncertainty and randomness, have become non-negligible due to the reduction in the atomic base, and have even become major factors affecting device performance, limiting further device size expansion. Randomized process fluctuations are based on statistical distributions at the atomic level and cannot be directly controlled. To assess their impact on devices, the only option is to model the fluctuations. By analyzing the distribution of a certain number of sample data points to characterize the dispersion of the fluctuations, a statistical and quantitative analysis can be performed. Based on the results, devices and circuits can be optimized, or relevant process conditions can be controlled to guide device fabrication.

[0003] However, due to the three-dimensional structure and process of FinFETs, software simulation design is inherently computationally intensive. Furthermore, the number of samples required to simulate process fluctuations must be in the thousands, requiring significant computing power and a significant amount of time. This makes it difficult to directly assess the impact of process fluctuations on parameters such as FinFET parasitic capacitance. By combining a standard analytical model for parasitic capacitance with discrete data extracted from simulation data, a statistical fluctuation model of FinFET parasitic capacitance that accounts for process fluctuations can be derived. This model can provide a reference for improving device structures and processes at current node sizes. Furthermore, the data used in this method comes from the TCAD software itself, and the data processing methods can be easily ported to the software, significantly impacting the development of TCAD software. This method reduces the extensive computation required to simulate process fluctuations and accurately represents the impact of process fluctuations on parasitic capacitance using a statistical distribution. This FinFET parasitic capacitance fluctuation model allows for the estimation of parasitic capacitance fluctuations without requiring extensive computation, addressing issues such as threshold, failure rate, and yield in circuit designs that consider process fluctuations. Summary of the Invention

[0004] Technical Problem: Due to the significantly increased impact of process fluctuations on nanometer-scale FinFET devices, this paper proposes a method for obtaining a parasitic capacitance fluctuation model for FinFETs. This method can estimate the fluctuations in parasitic capacitance of non-ideal devices without requiring extensive calculations, addressing issues such as threshold, failure rate, and yield in circuit design under process fluctuations. Furthermore, the data for this method comes from the TCAD software itself, and the data processing algorithm can be easily ported to the software, providing a simple and efficient method for TCAD software to handle process fluctuations.

[0005] Technical solution: To achieve the above-mentioned purpose, a method for obtaining a parasitic capacitance fluctuation model of a FinFET of the present invention comprises the following steps:

[0006] Step S01: obtaining a standard FinFET parasitic capacitance analytical model based on the FinFET simulated electric field distribution and the BSIM-CMG (Berkeley Short Channel FET Model Set - Common Multi-Gate) compact model;

[0007] Step S02: using a TCAD simulation tool in combination with a statistical impedance field method to obtain multiple sets of FinFET electromagnetic simulation data under process fluctuation conditions as samples; wherein the process fluctuations considered in the simulation include random doping fluctuations, oxide layer thickness fluctuations, interface trap state fluctuations, and metal work function fluctuations;

[0008] Step S03: Extracting sample statistical data of parasitic capacitance that takes into account process fluctuations from the sample simulation data using a gate voltage drain bias sweep method. Processing the sample data of parasitic capacitance involves obtaining statistical parameters such as the significance difference, mathematical expectation, and mean square error of the samples. A single-sample Kolmogorov–Smirnov test (KS test) is then performed to determine the distribution type to which the samples conform.

[0009] Step S04: combining the sample statistical data of the parasitic capacitance with the standard FinFET parasitic capacitance analytical model, substituting into the probability density formula of the probability distribution type obtained by the single-sample KS test, to obtain a parasitic capacitance fluctuation model considering process fluctuations.

[0010] in,

[0011] The parasitic capacitance of the FinFET is divided into two parts according to the distribution of the FinFET electric field lines. One part is the parallel plate parasitic capacitance, which includes the capacitance C between the gate and the source / drain opposite surface. cg1 and the capacitance C between the top surface of the gate and the top surface of the source and drain cg2 The other part is the vertical plate parasitic capacitance, including the parasitic capacitance C between the gate and the fin.fg and the capacitance C between the gate side and the source and drain top cg3 , that is, the overall parasitic capacitance C p Expressed as:

[0012] C p =C fg +C cg1 +C cg2 +C cg3 .

[0013] The step S01 is specifically as follows:

[0014] Parasitic capacitance C between gate and fin fg for:

[0015]

[0016] The capacitance C between the gate and the source / drain cg1 for:

[0017]

[0018] The capacitance C between the top surface of the gate and the top surface of the source and drain cg2 for:

[0019]

[0020] The capacitance C between the gate sidewall and the source and drain top surfaces cg3 for:

[0021]

[0022] Among them, H Fin is the height of Fin, H g is the gate height, H c is the source / drain height, H max is the major axis length of the elliptical electric field line formed by the gate and the fin, R is the radius of the quarter-circular electric field line formed by the gate sidewall and the source and drain top surface; L ext is the length of the expansion area, L c is the source-drain length, L g is the gate length, T ox is the oxide layer thickness, ε sp is the relative dielectric constant of the material, C fgsat 、C fglog are C in linear and saturation states respectively. fg Reference value, C fgsat 、C fglog 、H max , R are obtained from simulation results; k1 and k2 are fitting parameters.

[0023] The sample statistics of the parasitic capacitance are calculated by scanning the gate voltage and drain bias in the TCAD simulation results. i Extract it to obtain the parasitic capacitance value that is not affected by gate voltage and drain bias, extract the parasitic capacitance of all samples, and form a parasitic capacitance sample set C N ={C0, C1, C3...C i …C n}; where C i ∈C N , find the sample set C N The mean E C , standard deviation σ C , maximum value, 95% confidence interval statistical parameters, perform a single sample KS test on the sample set based on the parameters, and judge whether it obeys the tested distribution based on the significance level α obtained by the test; the main distributions are normal distribution, exponential distribution, uniform distribution, and Poisson distribution.

[0024] In step S04, since the parasitic capacitance obeys the normal distribution, the parasitic capacitance fluctuation model is:

[0025]

[0026] E f =C p +β1(E c -C p )β1∈[0,1]

[0027]

[0028] Among them, f(c f ) is the probability density function obeyed by the parasitic capacitance, C f is the parasitic capacitance, E c is the mean of the sample data, is the variance of the sample data, E f is the mean of the volatility model, is the variance of the volatility model, C p is the exact value of the parasitic capacitance analytical model, and β1 and β2 are fitting parameters.

[0029] The parasitic capacitance fluctuation model is explained as follows: In a standard device, the FinFET parasitic capacitance is C f, if the device parameters are fixed, the value is an exact value; when considering random devices under process fluctuation conditions, the parasitic capacitance will randomly change around the exact value. According to the discrete values ​​obtained by simulation, the distribution obeyed by the random change of parasitic capacitance is judged. The probability density function of the distribution is determined by the distribution of discrete parasitic capacitance, the expectation of the distribution is determined by the standard value and the mean value of discrete parasitic capacitance, and the degree of discreteness of the distribution is determined by the variance of discrete parasitic capacitance; through the FinFET parasitic capacitance fluctuation model, the threshold, failure rate and yield rate of circuit design under process fluctuation conditions are obtained.

[0030] The statistical impedance field method described above obtains multiple sets of FinFET electromagnetic simulation data under process fluctuation conditions, and is a numerical method that uses Green's function to quickly solve process fluctuations. By using the Green's function of the standard device, the fluctuation amount of the random process fluctuation device is regarded as a perturbation, and the relationship between voltage, current, Green's function and perturbation is obtained, and the electrical parameters of multiple sets of sample devices are quickly solved.

[0031] Beneficial effects: The method for obtaining the parasitic capacitance fluctuation model of the FinFET can reduce the large amount of calculations required for simulating process fluctuations, and can more accurately express the impact of process fluctuations on parasitic capacitance in the form of statistical distribution. Through the FinFET parasitic capacitance fluctuation model, the fluctuation of the parasitic capacitance of non-ideal devices can be estimated without the need for a large amount of calculations, and the problems of performance margin, failure rate, and yield rate of circuit design under process fluctuation conditions can be solved. At the same time, the data of this method comes from the TCAD software itself, and the data processing algorithm can be easily transplanted into the software, providing a simple and efficient method for TCAD software to deal with process fluctuations. It is very meaningful for the development of TCAD software. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a typical schematic diagram of a three-dimensional FinFET device structure;

[0033] Figure 2 This is a flow chart of a method for obtaining a FinFET parasitic capacitance fluctuation model according to the present invention;

[0034] Figure 3 is a schematic diagram of the shape of the parasitic capacitor electric field line; where a is the electric field line distribution of the parallel plate capacitor, b is the electric field line distribution of the non-parallel plate capacitor, and c is the electric field line distribution of the perpendicular capacitor;

[0035] Figure 4 This is a schematic diagram of the main components of parasitic capacitance;

[0036] Figure 5 It is a schematic diagram of the FinFET parasitic capacitance fluctuation model. DETAILED DESCRIPTION

[0037] The technical solution of the present invention is described in detail below with reference to the accompanying drawings:

[0038] It should be noted that in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly represent the structure of the present invention for the convenience of explanation, the structures in the accompanying drawings are not drawn according to general proportions, and are partially enlarged, deformed and simplified. Therefore, it should be avoided to understand this as a limitation of the present invention.

[0039] In the following specific embodiments of the present invention, please refer to Figure 2 , Figure 2 This is a flow chart of a method for obtaining a FinFET parasitic capacitance fluctuation model according to the present invention. Figure 2 As shown, a method for obtaining a FinFET parasitic capacitance fluctuation model of the present invention includes the following steps:

[0040] Execute step S01: determine the type, structure and location of the parasitic capacitor based on the electric field distribution obtained from FinFET simulation. Figure 1 , which is a typical three-dimensional FinFET device structure diagram, as shown Figure 1 As shown, the gate wraps around the protruding channel, that is, the side and top surfaces of the fin, forming a three-dimensional structure, and the source and drain are still at both ends of the channel and connected to the channel.

[0041] The distribution of the parasitic capacitance electric field lines in FinFET can be Figure 3 To judge. Figure 3 As shown in the figure, parasitic capacitors are divided into two categories according to the electric field distribution. The first is parallel parasitic capacitors and the second is vertical parasitic capacitors. Parallel plate parasitic capacitors also include two types: facing parallel and non-facing parallel. The facing parallel capacitors are facing each other in the positive direction, and the electric field lines are parallel to each other. Figure 3 As shown in (a) in the figure. For capacitors that are not facing each other, there is no effective facing area, so the electric field lines are asymmetric U-shaped, as shown in Figure 3 As shown in (b). The vertical parasitic capacitance electric field lines are as follows Figure 3 As shown in (c), it is fan-shaped, and the electric field lines near the foot are denser and tassel-shaped.

[0042] like Figure 4 As shown, the parallel plate parasitic capacitance includes the parallel capacitance C between the gate and the source / drain opposite surfaces. cg1 and the non-parallel capacitance C between the top surface of the gate and the top surface of the source and drain cg2 The other part is the vertical plate parasitic capacitance, including the parasitic capacitance C between the gate and the fin. fg and the capacitance C between the gate side and the source and drain top cg3 , the overall parasitic capacitance:

[0043] C p =C fg +C cg1 +C cg2 +C cg3

[0044] According to the BSIM-CMG standard, we can get

[0045] Parasitic capacitance C between gate and Fin fg for:

[0046]

[0047] The capacitance C between the gate and the source / drain cg1 for:

[0048]

[0049] The capacitance C between the top surface of the gate and the top surface of the source and drain cg2 for:

[0050]

[0051] The capacitance C between the gate sidewall and the source and drain top surfaces cg3 for:

[0052]

[0053] Among them, H Fin is the height of Fin, H g is the gate height, H max L is the major axis length of the elliptical electric field line formed by the gate and Fin, and R is the radius of the quarter-circular electric field line formed by the gate sidewall and the source and drain top surface. ext is the length of the expansion area, L c is the source-drain length, L g is the gate length, T ox is the oxide layer thickness, ε sp is the relative dielectric constant of the material, C fgsat 、C fglog are C in linear and saturation states respectively. fg Reference value, C fgsat 、C fglog 、H max and R are obtained from simulation results. k1 and k2 are fitting parameters.

[0054] Execute step S02 to simulate the FinFET model with process fluctuations using the statistical impedance field method to obtain FinFET simulation data with process fluctuations. This step is not affected by the previous steps and can be performed independently or before step S01. Its purpose is to obtain electromagnetic simulation data for a large number of FinFET samples under process fluctuations, mainly including steady-state and small-signal simulation results of FinFETs under fluctuation sources such as random doping fluctuations, metal work function fluctuations, interface trap state fluctuations, and oxide layer thickness fluctuations.

[0055] Execute step S03: extract the capacitance matrix between each electrode from the TCAD simulation results, and extract the value of the parasitic capacitance by gate voltage drain bias scanning method to form a parasitic capacitance random sample C N ={C0, C1, C3...C i …C n}. Among them C i ∈C N , find the sample set C N The mean E C , standard deviation σ C , maximum value, 95% confidence interval and other statistical parameters, perform a single-sample KS test on the sample set based on the parameters, and judge the distribution type obeyed by the sample based on the significance level α obtained by the test.

[0056] Execute step S04: according to the probability distribution type obeyed by the sample, in combination with the analytical parasitic capacitance model, substitute the probability density formula of the distribution into it to obtain the fluctuation model of the parasitic capacitance.

[0057] like Figure 5 As shown: FinFET parasitic capacitance is C f , the device parameters are fixed, then the value is an exact value, that is, Figure 5 The dashed line value in the middle; when considering random devices under process fluctuation conditions, the parasitic capacitance will randomly change around the exact value. According to the histogram of discrete values ​​obtained by simulation, the distribution of the random change of parasitic capacitance is determined, that is, Figure 5 In the middle gray part, the normal curve is fitted by the histogram, with the mean Ec and the standard deviation σ C The probability density function of the distribution is f(c f ) As shown by the black curve in the figure, the curve type is determined by the distribution of discrete parasitic capacitances. The expected F f The distribution of the FinFET parasitic capacitance fluctuation model is determined by the precise value Cp of the parasitic capacitance analytical model, the mean value Ec of the discrete parasitic capacitance, and the fitted value β1. The degree of dispersion of the distribution is determined by the variance of the discrete parasitic capacitance and the fitted value β2, forming the following:

[0058]

[0059] E f =C p +β1(E c -C p )β1∈[0,1]

[0060]

[0061] Among them, f(c f ) is the probability density function obeyed by the parasitic capacitance, E c is the mean of the sample data, is the variance of the sample data, E f is the mean of the volatility model, is the variance of the volatility model, C p is the exact value of the parasitic capacitance analytical model, and β1 and β2 are fitting parameters.

[0062] Example:

[0063] Taking the FinFET simulation model as a specific example, the key parameters of the simulated standard device are: fin aspect ratio Hfin / Wfin is 40 / 17, channel length Lg is 25nm, polysilicon thickness Tpoly is 80nm, oxide layer thickness Tox is 1nm, metal work function is 4.2eV, substrate thickness is 1um, threshold voltage is 0.312V, subthreshold swing reaches more than 80, and off current reaches 10 -9 Magnitude.

[0064] According to step S01, the overall parasitic capacitance is divided into two parts. One part is the parallel plate parasitic capacitance, which includes the capacitance C between the gate and the source / drain opposite surfaces. cg1 and the capacitance C between the top surface of the gate and the top surface of the source and drain cg2 The other part is the vertical plate parasitic capacitance, including the parasitic capacitance C between the gate and the fin. fg and the capacitance C between the gate side and the source and drain top cg3 , according to the BSIM-CMG standard, we can get

[0065] Parasitic capacitance C between gate and Fin fg for:

[0066]

[0067] The capacitance C between the gate and the source / drain cg1 for:

[0068]

[0069] The capacitance C between the top surface of the gate and the top surface of the source and drain cg2 for:

[0070]

[0071] The capacitance C between the gate sidewall and the source and drain top surfaces cg3 for:

[0072]

[0073] Among them, H Fin is the height of Fin, H g is the gate height, H max L is the major axis length of the elliptical electric field line formed by the gate and Fin, and R is the radius of the quarter-circular electric field line formed by the gate sidewall and the source and drain top surface. ext is the length of the expansion area, L c is the source-drain length, L g is the gate length, T ox is the oxide layer thickness, ε sp is the relative dielectric constant of the material, C fgsat 、C fglog are C in linear and saturation states respectively. fg Reference value, C fgsat 、C fglog 、H max and R are obtained from simulation results. k1 and k2 are fitting parameters.

[0074] Therefore, the overall parasitic capacitance of FinFET can be calculated as:

[0075] C p =C fg +C cg1 +C cg2 +C cg3

[0076] Next, step S02 is executed to add four fluctuation sources, namely random doping fluctuation, metal work function fluctuation, interface trap state fluctuation, and oxide layer thickness fluctuation, to the standard FinFET device simulation model. 10,000 random samples are set for each fluctuation source, and the simulation is performed ten times, with 1,000 samples each time. Under the conditions of the four fluctuation sources acting separately and the four fluctuation sources acting together, a total of 50,000 random samples (5*10*1000) are simulated and calculated using the statistical impedance field method to obtain 5*10 groups of FinFET simulation data with 1,000 samples in each group.

[0077] Then, step S03 is executed to extract the capacitance matrix part in the simulation data of 50 groups of samples, scan the gate voltage and drain bias, and extract 50 groups of parasitic capacitance sample sets C N ={C0, C1, C3...C i …C n}. Among them C i ∈C N, N∈[1,50], n∈[1,1000]; find the sample set C N The mean E C , standard deviation σ C , maximum value, 95% confidence interval and other statistical parameters, and perform a single-sample KS test on the sample set to determine whether it conforms to the normal distribution based on the parameters. If the significance level α obtained by the test is ≤ 0.05, then the sample obeys the normal distribution; if the significance level α> 0.05, then the sample does not conform to the normal distribution, and it is necessary to re-test the exponential distribution, uniform distribution, and Poisson distribution in turn, and finally obtain the distribution type that the sample conforms to.

[0078] Finally, step S04 is executed. After testing, the sample set C N ={C0, C1, C3...C i …C n The significance level of α is ≤ 0.05, which means it obeys the normal distribution. Based on this, it can be judged that the basic form of the fluctuation model of FinFET parasitic capacitance is the form of normal distribution. Calculate the mean E of the sample data c , the variance of the sample data Substitute the device parameters to calculate the exact value of the parasitic capacitance analytical model C p Under each fluctuation source condition, 10 sets of data were tested separately to obtain the fitting parameters β1 and β2. From this, the expected value, variance and other parameters describing the fluctuation model distribution were calculated. The final parasitic capacitance fluctuation model can be expressed as:

[0079]

[0080] Among them, f(c f ) is the probability density function obeyed by the parasitic capacitance, E c is the mean of the sample data, is the variance of the sample data, E f is the mean of the volatility model, is the variance of the volatility model, C p is the exact value of the parasitic capacitance analytical model, and β1 and β2 are fitting parameters.

[0081] Through this FinFET parasitic capacitance fluctuation model, the fluctuation of parasitic capacitance can be estimated without a lot of calculations, solving problems such as threshold, failure rate, and yield rate of circuit design under process fluctuation conditions.

Claims

1. A method for obtaining a parasitic capacitance fluctuation model of a FinFET, characterized in that: The method comprises the following steps: Step S01: obtaining a standard FinFET parasitic capacitance analytical model based on a FinFET simulation electric field distribution and a BSIM-CMG compact model; Step S02: using a TCAD simulation tool in combination with a statistical impedance field method to obtain multiple sets of FinFET electromagnetic simulation data under process fluctuation conditions as samples; wherein the process fluctuations considered in the simulation include random doping fluctuations, oxide layer thickness fluctuations, interface trap state fluctuations, and metal work function fluctuations; Step S03: Extracting sample statistical data of parasitic capacitance that takes into account process fluctuations from the sample simulation data using a gate voltage drain bias scanning method. Processing the sample data of parasitic capacitance: Obtaining statistical parameters of the sample's significance difference, mathematical expectation, and mean square error. A single-sample Kolmogorov-Smilov (KS) test is then performed to determine the distribution type to which the sample conforms. Step S04: combining the sample statistical data of the parasitic capacitance with the standard FinFET parasitic capacitance analytical model, substituting the data into the probability density formula of the probability distribution type obtained by the single-sample KS test, and obtaining a parasitic capacitance fluctuation model considering process fluctuations; in, The step S01 is specifically as follows: Parasitic capacitance C between gate and fin fg for: The capacitance C between the gate and the source / drain cg1 for: The capacitance C between the top surface of the gate and the top surface of the source and drain cg2 for: The capacitance C between the gate sidewall and the source and drain top surfaces cg3 for: Among them, H Fin is the height of Fin, H g is the gate height, H c is the source / drain height, H max is the major axis length of the elliptical electric field line formed by the gate and the fin, R is the radius of the quarter-circular electric field line formed by the gate sidewall and the source and drain top surface; L ext is the length of the expansion area, L c is the source-drain length, L g is the gate length, T ox is the oxide layer thickness, ε sp is the relative dielectric constant of the material, C fgsat 、C fglog are C in linear and saturation states respectively. fg Reference value, C fgsat 、C fglog 、H max , R are obtained from simulation results; k1, k2 are fitting parameters; In step S04, since the parasitic capacitance obeys the normal distribution, the parasitic capacitance fluctuation model is: AND f =C p +β1(E c -W p )β1∈[0,1] Among them, f(c f ) is the probability density function obeyed by the parasitic capacitance, C f is the parasitic capacitance, E c is the mean of the sample data, is the variance of the sample data, E f is the mean of the volatility model, is the variance of the volatility model, C p is the exact value of the parasitic capacitance analytical model, and β1 and β2 are fitting parameters.

2. The method for obtaining a parasitic capacitance fluctuation model of a FinFET according to claim 1, wherein: The parasitic capacitance of the FinFET is divided into two parts according to the distribution of the FinFET electric field lines. One part is the parallel plate parasitic capacitance, which includes the capacitance C between the gate and the source / drain opposite surface. cg1 and the capacitance C between the top surface of the gate and the top surface of the source and drain cg2 The other part is the vertical plate parasitic capacitance, including the parasitic capacitance C between the gate and the fin. fg and the capacitance C between the gate side and the source and drain top cg3 , that is, the overall parasitic capacitance C p Expressed as: C p =C fg +C cg1 +C cg2 +C cg3 。 3. The method for obtaining a parasitic capacitance fluctuation model of a FinFET according to claim 1, wherein: The sample statistics of the parasitic capacitance are calculated by scanning the gate voltage and drain bias in the TCAD simulation results. i Extract it to obtain the parasitic capacitance value that is not affected by gate voltage and drain bias, extract the parasitic capacitance of all samples, and form a parasitic capacitance sample set C N ={C0, C1, C3...C i …C n }; where C i ∈C N , find the sample set C N The mean E C , standard deviation σ C , maximum value, 95% confidence interval statistical parameters, perform a single sample KS test on the sample set based on the parameters, and judge whether it obeys the tested distribution based on the significance level α obtained by the test; the main distributions are normal distribution, exponential distribution, uniform distribution, and Poisson distribution.

4. The method for obtaining a parasitic capacitance fluctuation model of a FinFET according to claim 1, wherein: The parasitic capacitance fluctuation model is explained as follows: In a standard device, the FinFET parasitic capacitance is C f , if the device parameters are fixed, then this value is an exact value; when considering random devices under process fluctuation conditions, the parasitic capacitance will randomly vary around the exact value. Based on the discrete values ​​obtained by simulation, the distribution obeyed by the random variation of the parasitic capacitance is determined. The probability density function of the distribution is determined by the distribution of the discrete parasitic capacitance, the expectation of the distribution is determined by the standard value and the mean value of the discrete parasitic capacitance, and the degree of dispersion of the distribution is determined by the variance of the discrete parasitic capacitance. Through the FinFET parasitic capacitance fluctuation model, the threshold, failure rate, and yield issues of circuit design under process fluctuation conditions are obtained.

5. The method for obtaining a parasitic capacitance fluctuation model of a FinFET according to claim 1, wherein: The statistical impedance field method described above obtains multiple sets of FinFET electromagnetic simulation data under process fluctuation conditions, and is a numerical method that uses Green's function to quickly solve process fluctuations. By using the Green's function of the standard device, the fluctuation amount of the random process fluctuation device is regarded as a perturbation, and the relationship between voltage, current, Green's function and perturbation is obtained, and the electrical parameters of multiple sets of sample devices are quickly solved.

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