Panel driving apparatus, panel driving method, and electroluminescent display device

Abstract

The present invention provides a panel driving apparatus, a panel driving method, and an electroluminescent display device. The electroluminescent display device includes a display panel including a first pixel and a second pixel, a data voltage supply unit supplying a first data voltage corresponding to a first gate signal to the first pixel and a second data voltage corresponding to a second gate signal to the second pixel in a vertical active period of a first frame, and continuously supplying a sensing data voltage corresponding to a third gate signal and a recovery data voltage to the second pixel in a vertical blanking period of the first frame, and a sensing circuit sensing an electrical characteristic of the second pixel based on the sensing data voltage in the vertical blanking period. The recovery data voltage is supplied to the second pixel later than the sensing data voltage in the vertical blanking period, and the recovery data voltage supplied to the second pixel in the vertical blanking period includes the first data voltage and the second data voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0185667, filed on December 23, 2021. Technical Field

[0003] This disclosure relates to panel driving apparatus, panel driving method, and electroluminescent display device. Background Technology

[0004] Each pixel of an electroluminescent display device includes a light-emitting device that emits (e.g., self-emits) light, and the amount of light emitted from the light-emitting device is controlled by a data voltage based on the gray level of the image data to adjust the brightness.

[0005] Electroluminescent display devices use external compensation techniques to improve image quality. External compensation techniques are based on sensing pixel voltage or current on a row-by-row basis according to the electrical characteristics of pixels, and modulating the input image data based on the sensing results to compensate for electrical characteristic deviations between pixels.

[0006] However, in existing electroluminescent display devices, there is a problem of brightness deviation between the sensing pixel row and the non-sensing pixel row. Summary of the Invention

[0007] In order to overcome the above-mentioned problems of the prior art, this disclosure provides a panel driving device, a panel driving method, and an electroluminescent display device that reduces the brightness deviation that occurs between sensing pixel rows and non-sensing pixel rows.

[0008] To achieve these and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, an electroluminescent display device includes: a display panel including a first pixel and a second pixel; a data voltage supply unit that supplies a first data voltage corresponding to a first gate signal to the first pixel and a second data voltage corresponding to a second gate signal to the second pixel during a vertical active period of a first frame, and continuously supplies a sensing data voltage and a recovery data voltage corresponding to a third gate signal to the second pixel during a vertical blanking period of the first frame; and a sensing circuit that senses the electrical characteristics of the second pixel based on the sensing data voltage during the vertical blanking period, wherein the recovery data voltage is supplied to the second pixel later than the sensing data voltage during the vertical blanking period, and the recovery data voltage supplied to the second pixel during the vertical blanking period includes the first data voltage and the second data voltage.

[0009] In another aspect of this disclosure, a panel driving apparatus includes: a data voltage supply unit that supplies a first data voltage corresponding to a first gate signal to a first pixel of a display panel and supplies a second data voltage corresponding to a second gate signal to a second pixel of the display panel during a vertical active period of a first frame, and continuously supplies a sensing data voltage and a recovery data voltage corresponding to a third gate signal to the second pixel during a vertical blanking period of the first frame; and a sensing circuit that senses the electrical characteristics of the second pixel based on the sensing data voltage during the vertical blanking period, wherein the recovery data voltage is supplied to the second pixel later than the sensing data voltage during the on-time of the third gate signal included in the vertical blanking period, and the recovery data voltage supplied to the second pixel during the vertical blanking period includes the first data voltage and the second data voltage.

[0010] In another aspect of this disclosure, a panel driving method includes: supplying a first data voltage corresponding to a first gate signal to a first pixel of a display panel and supplying a second data voltage corresponding to a second gate signal to a second pixel of the display panel during a vertical active period of a first frame; supplying a sensing data voltage corresponding to a third gate signal to the second pixel during a vertical blanking period of the first frame, and sensing the electrical characteristics of the second pixel based on the sensing data voltage; and supplying a recovery data voltage corresponding to the third gate signal to the second pixel during a vertical blanking period of the first frame, wherein the recovery data voltage is supplied to the second pixel later than the sensing data voltage during the on-time of the third gate signal included in the vertical blanking period, and the recovery data voltage supplied to the second pixel during the vertical blanking period includes the first data voltage and the second data voltage. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0012] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure;

[0013] Figure 2 It is shown Figure 1 A diagram of the pixel array included in an electroluminescent display device;

[0014] Figure 3 It is shown Figure 2 A diagram showing the pixels included in the pixel array and the sensing circuit connected to them;

[0015] Figure 4 This shows the drive. Figure 2 A diagram illustrating the driving concept of a pixel array;

[0016] Figure 5 It is shown Figure 2 A diagram showing the connection configuration between an unsensitized first pixel and a sensed second pixel in a pixel array;

[0017] Figure 6 It is shown Figure 5 A diagram illustrating an implementation of the driving timing sequence for the first and second pixels;

[0018] Figure 7 It is shown in Figure 6 The image pattern with a large voltage difference between the first data voltage supplied to the first pixel and the second data voltage supplied to the second pixel during the vertical effective period of the first frame;

[0019] Figure 8 It is shown in Figure 6 In the first frame, when displaying Figure 7 The image pattern shown is a diagram of the recovery data voltage and sensing data voltage supplied to the second pixel during the vertical blanking period of the first frame;

[0020] Figure 9 It is shown in Figure 6 A monochrome image pattern in which there is no voltage difference between the first data voltage supplied to the first pixel and the second data voltage supplied to the second pixel during the vertical blanking period of the first frame;

[0021] Figure 10 It is shown in Figure 6 In the first frame, when displaying Figure 9 The monochrome image pattern shown is a graph of the recovery data voltage and sensing data voltage supplied to the second pixel during the vertical blanking period of the first frame; and

[0022] Figure 11 It is shown Figure 5 A diagram of another embodiment of the driving timing of the first and second pixels. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms, and it should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0024] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary and are not limited thereto. The same reference numerals always refer to the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms “comprising,” “containing,” “having,” “with,” “including,” “comprises,” etc., imply that additional parts may be added, unless the term “only” is used. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0025] Even if not explicitly stated otherwise, elements in the various embodiments of this disclosure should be interpreted as including error margins.

[0026] When describing positional relationships, for example, when the positional relationship between two parts is described as "on top of", "above", "below", and "near", one or more other parts can be placed between the two parts, unless "just" or "directly" is used.

[0027] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0028] Similar reference numerals are used throughout the text to refer to similar elements.

[0029] In this specification, the gate drive circuit disposed on the substrate of the display panel can be implemented using a thin-film transistor (TFT) with an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure, but is not limited thereto, and can also be implemented using a TFT with a p-type MOSFET structure. The TFT can be a three-electrode element including a gate, a source, and a drain. The source can be the electrode that provides charge carriers to the transistor. In a TFT, charge carriers can flow from the source. The drain can be the electrode that allows charge carriers to flow out of the TFT. That is, in a MOSFET, charge carriers flow from the source to the drain. In an n-type TFT (NMOS), the charge carriers are electrons, and the source voltage can be lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-type TFT, because electrons flow from the source to the drain, current can flow from the drain to the source. On the other hand, in a p-type TFT (PMOS), the charge carriers are holes, so the source voltage can be higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-type TFT, current can flow from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed, but switch between the two. For example, the source and drain of a MOSFET can switch between the two. Therefore, in the embodiments describing this disclosure, one of the source and drain will be described as a first electrode, and the other of the source and drain will be described as a second electrode.

[0030] In the following description, detailed descriptions of known functions or configurations will be omitted where it is determined that such descriptions unnecessarily obscure the focus of this disclosure. Hereinafter, embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A diagram of the pixel array included in an electroluminescent display device. Figure 3 It is shown Figure 2 The diagram shows the pixels included in the pixel array and the sensing circuit connected to them.

[0032] Reference Figures 1 to 3 An electroluminescent display device according to embodiments of this disclosure may include a display panel 10, a timing controller 11, a data driver 12, a gate driver 13, and a sensing circuit 122. In this disclosure, the data voltage supply unit 121, the gate driver 13, and the sensing circuit 122 can implement a panel driving device. The data voltage supply unit 121 and the sensing circuit 122 can be embedded in the integrated circuit (IC) of the data driver 12.

[0033] The display panel 10 may include multiple data lines 15, multiple readout lines 16, and multiple gate lines 17. Furthermore, multiple pixels PXL may be arranged in multiple intersecting regions between the data lines 15, readout lines 16, and gate lines 17. Figure 2 The pixel array shown may include multiple pixels PXL arranged in a matrix type and may be set in the display area AA of the display panel 10.

[0034] In a pixel array, a pixel row can be implemented using pixels PXL that are adjacent to each other in the direction of extension of the gate line 17 to the pixel array (i.e., the X-axis direction). Each pixel row may include multiple pixels PXL that are adjacent to each other in the X-axis direction. Pixels PXL configured in the same pixel row can be connected to the same gate line 17 and can be connected to different data lines 15. Pixels PXL configured in the same pixel row can be connected to different readout lines 16, but are not limited thereto, and multiple pixels PXL used to implement different colors can share a single readout line 16.

[0035] In the pixel array, each pixel PXL can be connected to the data driver 12 via one of the data lines 15 and one of the readout lines 16, and can be connected to the gate driver 13 via one of the gate lines 17. Furthermore, each pixel PXL can be connected to the high-level pixel power supply EVDD via the high-level power supply line 18.

[0036] In the pixel array, pixel PXL may include pixels implementing a first color, pixels implementing a second color, and pixels implementing a third color, and may also include pixels implementing a fourth color. The first to fourth colors may optionally be one of red, green, blue, and white.

[0037] Each pixel PXL can be like Figure 3 It can be achieved in that way, but is not limited to that.

[0038] like Figure 3 As shown, the pixel PXL arranged in the kth (where k is an integer) pixel row may include a light-emitting device EL, a driving transistor DT, a storage capacitor Cst, a first switching transistor ST1 and a second switching transistor ST2, and the first switching transistor ST1 and the second switching transistor ST2 may be connected to the same gate line 17(k).

[0039] A light-emitting device (EL) can emit light in response to a pixel current applied to it. The EL may include an anode electrode connected to a source node Ns, a cathode electrode connected to a low-level pixel power supply EVSS, and an organic or inorganic compound layer disposed between the anode and cathode electrodes. The organic or inorganic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and / or an electron injection layer (EIL). The EL can be turned on when the voltage applied to the anode electrode is higher than the operating point voltage of the EL compared to the low-level pixel power supply EVSS applied to the cathode electrode. When the EL is turned on, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) can move to the emitter layer (EML) to generate excitons; therefore, light can be emitted from the emitter layer (EML).

[0040] The driving transistor DT can be a driving element. The driving transistor DT can generate a pixel current flowing in the light-emitting device EL based on the voltage difference between the gate node Ng and the source node Ns. The driving transistor DT may include a gate electrode connected to the gate node Ng, a first electrode connected to the high-level pixel power supply EVDD, and a second electrode connected to the source node Ns.

[0041] The storage capacitor Cst can be connected between the gate node Ng and the source node Ns, and can store the gate-source voltage of the driving transistor DT.

[0042] The first switching transistor ST1 can electrically connect the data line 15 to the gate node Ng based on the gate signal SCAN(k) (i.e., in response to the application of the gate signal SCAN(k)), and can apply the data voltage VDATA charged in the data line 15 to the gate node Ng. The first switching transistor ST1 may include a gate electrode connected to the gate line 17(k), a first electrode connected to the data line 15, and a second electrode connected to the gate node Ng.

[0043] The second switching transistor ST2 can electrically connect the readout line 16 to the source node Ns based on the gate signal SCAN(k), and can apply the voltage of the source node Ns to the readout line 16 based on the pixel current, or can apply the reference voltage Vref charged in the readout line 16 to the source node Ns. The second switching transistor ST2 may include a gate electrode connected to the gate line 17(k), a first electrode connected to the source node Ns, and a second electrode connected to the readout line 16.

[0044] Such a pixel structure may be merely an implementation method, and the inventive concept is not limited thereto. It should be noted that the claimed method can be applied to various pixel structures used for sensing the electrical characteristics (threshold voltage or electron mobility) of the driving transistor DT. For example, the claimed method can be applied to any pixel structure supplied with a data voltage, a gate signal, a sensed data voltage, and a recovered data voltage. The timing controller 11 can be connected to the host system 14 via a first interface circuit and to the data driver 12 via a second interface circuit. The first and second interface circuits can be the same or different.

[0045] The timing controller 11 can receive the vertical synchronization signal Vsync, the data enable signal DE, and the input video data DATA from the host system 14 through the first interface circuit. The vertical synchronization signal Vsync is a control signal that defines a frame. The timing controller 11 can receive the input video data DATA during the vertical active period of each frame and can not receive the input video data DATA during the vertical blanking period.

[0046] A frame can be defined by a vertical synchronization signal Vsync and a data enable signal DE. Furthermore, a vertical active period and a vertical blanking period can be defined for a frame. A frame can be defined as the interval between adjacent pulses of the vertical synchronization signal Vsync. The vertical active period can be defined as the period during which the data enable signal DE of a frame shifts between logic high and logic low levels. In some implementations, the vertical active period can be defined as the period during which the data enable signal DE of a frame shifts from logic low to logic high. The vertical blanking period can be defined as the period during which the data enable signal DE of a frame is held at a logic low level.

[0047] The length of the vertical blanking period can vary based on the vertical synchronization signal Vsync and the data enable signal DE. The host system 14 can change the length of the vertical blanking period to alter the driven frame rate based on the complexity of the input video data DATA and the amount of inter-frame variation in the input video data DATA. When the input video data DATA is complex and has a large amount of inter-frame variation, the host system 14 can increase the length of the vertical blanking period set for each frame, thereby reducing the frame rate. When the length of the vertical blanking period varies within a frame, the duration of a frame and the frame rate can vary. This can be referred to as Variable Refresh Rate (VRR) technology. VRR technology can adequately ensure the rendering time for graphics processing in the host system 14 to prevent image tearing and thus provide a smoother image.

[0048] The host system 14 can be mounted on a system board. The host system 14 may include: an input unit that receives user commands / data; a main power unit that generates main power; a VRR control circuit that changes the frame rate based on the input image; and an output unit that outputs transmission signals. The host system 14 may be implemented using an application processor, a personal computer (PC), a set-top box, or a graphics processing unit, but is not limited thereto.

[0049] The timing controller 11 can control the control drive to display-drive the display panel 10, and thus can reproduce the input image on the display panel 10. The timing controller 11 can control the control drive to sense-drive the display panel 10 during the vertical blanking period of a frame, and then can resume-drive the display panel 10.

[0050] Sensing drive can be used to sense the electrical characteristics of the driving transistor DT included in pixel PXL and can be performed simultaneously by a row of pixels. In pixel PXL that is sensed to enhance the accuracy of sensing, the light-emitting device can stop emitting light during sensing drive. Sensing drive can be performed sequentially or non-sequentially by a row of pixels during the vertical blanking period of each frame. The row of pixels sensed during the vertical blanking period of each frame, except for one row of pixels, can maintain the display state of the previous vertical active period.

[0051] Recovery driving can be used to restore the luminance (brightness) of pixels PXL in a sensing pixel row to the display state immediately preceding the sensing drive. A recovery data voltage can be applied to pixels PXL in the sensing pixel row for recovery driving. In some embodiments, based on the control of timing controller 11, the panel driver can apply a recovery data voltage having the same level as the display data voltage immediately preceding the sensing drive to pixels PXL in the sensing pixel row, and thus the corresponding pixels PXL can emit light again, thereby restoring the brightness of the sensing pixel row to the state immediately preceding the sensing drive. In some embodiments, the panel driver can generate a recovery data voltage configured by a combination of two display data voltages, and thus can reduce the brightness deviation occurring between sensing and non-sensing pixel rows. This will refer to... Figures 4 to 11 Detailed description.

[0052] The timing controller 11 can generate timing control signals for the panel driving devices required for display driving, sensing driving, and recovery driving, and can provide timing control signals to the data driver 12 and the gate driver 13 through the second interface circuit. The timing control signals for the panel driving devices may include a data timing control signal DDC for controlling the operating timing of the data driver 12 and a gate timing control signal GDC for controlling the operating timing of the gate driver 13.

[0053] The timing controller 11 can receive sensing result data based on sensing drive from the data driver 12 via a second interface circuit. The electrical characteristics of the driving transistor DT included in each sensing pixel PXL can be reflected in the sensing result data. The timing controller 11 can calculate a pixel compensation value based on the sensing result data and can apply the pixel compensation value to the input video data DATA received from the host system 14 to compensate for the electrical characteristic deviation of each driving transistor DT between pixels PXL. The pixel compensation value can be a correction based on the electrical characteristics of each driving transistor included in each sensing pixel PXL reflected in the sensing result data. The correction value can compensate for the electrical characteristic deviation of each driving transistor in each sensing pixel PXL between pixels PXL. The timing controller 11 can supply the image data DATA obtained by the correction based on the pixel compensation value to the data driver 12 via the second interface circuit.

[0054] The timing controller 11 can control the operation of the panel driver based on the timing control signals GDC and DDC during the vertical effective time period of each frame, and thus can realize display driving. In display driving, the panel driver can supply display data voltage for displaying the input image to all pixels PXL of the pixel array.

[0055] The timing controller 11 can also control the operation of the panel driver based on the timing control signals GDC and DDC during the vertical blanking period of each frame, and thus can also implement sensing drive and recovery drive. In sensing drive, the panel driver can supply the sensing data voltage required for sensing to the pixels PXL of the sensing pixel row. In recovery drive, the panel driver can supply the recovery data voltage for restoring the original display state to the pixels PXL of the sensing pixel row, and thus the emission state of the pixels PXL that stopped during sensing drive can be restored by recovery drive.

[0056] The gate driver 13 can be positioned in the non-display area NA of the display panel 10 based on the in-panel gate driver (GIP) type. The gate driver 13 can generate a scan signal SCAN that swings between the turn-on voltage and the turn-off voltage based on the gate timing control signal GDC. The gate driver 13 can sequentially supply the scan signal SCAN to the gate lines 17(1) to 17(4) using a progressive cell during the vertical active period of each frame. The gate driver 13 can also supply the scan signal SCAN to the gate line 17 of the pixel PXL connected to the sensing pixel row during the vertical blanking period of each frame.

[0057] The data driver 12 can be implemented using a data IC. The data driver 12 may include a data voltage supply unit (DAC) 121 and a sensing circuit (SU) 122. The data voltage supply unit (DAC) 121 generates a data voltage VDATA based on a data timing control signal DDC. The data voltage VDATA can be divided into a display data voltage, a sensed data voltage, and a recovered data voltage.

[0058] A data voltage supply unit (DAC) 121 can be connected to the pixel array via one of the data lines 15. The DAC 121 can generate a display data voltage with a level varying based on the grayscale level of the image data DATA during the vertical active period of each frame and can supply the display data voltage to the data line 15. The display data voltage can be supplied to the gate node Ng of the pixel PXL synchronously with the scan signal SCAN. The DAC 121 can also generate a sensing data voltage during the vertical blanking period of each frame and supply the sensing data voltage to the data line 15, and then generate a recovery data voltage and supply the recovery data to the data line 15. The sensing data voltage and the recovery data voltage can be supplied to the gate node Ng of the sensing target pixel PXL (i.e., the pixel to be sensed) synchronously with the scan signal SCAN.

[0059] The sensing circuit (SU) 122 can be connected to the pixel array via one of the readout lines 16. The sensing circuit (SU) 122 can sense, via the readout lines 16, either the pixel current flowing in the target pixel PXL based on the sensing data voltage, or the source node voltage of the target pixel PXL based on the pixel current. The pixel current can sense the electrical characteristics of the target pixel PXL and can vary based on the degree of degradation of the target pixel PXL. The source node voltage can be (or represents) the electrical characteristics of the target pixel PXL and can vary based on the degree of degradation of the target pixel PXL (or the degree of deviation from expected characteristics).

[0060] The sensing circuit (SU) 122 can be implemented as a voltage sensing type that samples the source node voltage, or as a current sensing type that samples the pixel current.

[0061] like Figure 3 The voltage sensing circuit (SU) 122 may include a sampling circuit SAM and an analog-to-digital converter (ADC). The sampling circuit SAM can directly sample the source node voltage of the sensing target pixel PXL stored in the parasitic capacitor of the readout line 16. The analog-to-digital converter (ADC) can convert the analog voltage obtained by the sampling circuit SAM into a digital sensing result value and can transmit the digital sensing result value to the timing controller 11.

[0062] The current-sensing type sensing circuit (SU) 122 may include a current integrator, a sampling circuit, and an analog-to-digital converter. The current integrator integrates the pixel current flowing in the sensing target pixel PXL to output a sensing voltage. The sampling circuit samples the sensing voltage output from the current integrator. The analog-to-digital converter converts the analog voltage obtained by the sampling circuit into a digital sensing result value and transmits the digital sensing result value to the timing controller 11.

[0063] In each of the display driver, sensing driver, and recovery driver, the sensing circuit (SU) 122 can turn on the first switch SW1 to apply a reference voltage Vref to the readout line 16 based on the timing of supplying the data voltage VDATA to the data line 15. The reference voltage Vref charged into the readout line 16 can be supplied to the source node Ns of the pixel PXL in synchronization with the scan signal SCAN.

[0064] Figure 4 This shows the drive. Figure 2 A diagram illustrating the driving concept of the pixel array.

[0065] Reference Figure 4 Each frame may include a vertical active period and a vertical blanking period. The panel driving device, based on the control of a timing controller, sequentially scans all pixel rows of the pixel array during the vertical active period while simultaneously writing display data voltages IVDATA', IVDATA, and IVDATA1 corresponding to image data to all pixels, thus enabling display-driving of the display panel. The panel driving device, based on the control of the timing controller, selects predetermined sensing pixel rows (N, M) during the sensing period of the vertical blanking period, and supplies sensing data voltages SVDATA to the pixels of the sensing pixel rows (N, M) to sense-drive the display panel. Then, during the recovery period of the vertical blanking period, it supplies recovery data voltages VREC to the pixels of the sensing pixel rows (N, M) to recover-drive the display panel. The pixels of the sensing pixel rows (N, M) can be turned on (illuminated) based on display driving, can be turned off (not illuminated) during sensing driving, and can be turned on (illuminated) based on recovery driving. The pixels of the sensing pixel rows (N, M) can be restored to the image data display state immediately preceding the sensing (i.e., the vertical active period) through recovery driving.

[0066] For display recovery, the panel driver can supply display data voltage as recovery data voltage VREC to the pixels of the sensing pixel row (N, M) on which sensing has been completed.

[0067] To reduce the brightness deviation between the sensing pixel row and the non-sensing pixel row, the panel driving device can continuously supply a first display data voltage and a second display data voltage to the target pixel, each selected as the recovery data voltage VREC during the recovery period. Here, the target pixel can be a pixel on which sensing has been completed, the first display data voltage can be a voltage supplied to a non-sensing pixel adjacent to the target pixel in the Y-axis direction, and the second display data voltage can be a voltage supplied to the target pixel.

[0068] For example, when the target pixel (sensing pixel) is in the Nth pixel row and the non-sensing pixel is in the N-1th pixel row in the first frame, during the recovery period, the panel driver can supply the display data voltage IVDATA' of the non-sensing pixel to the target pixel as the recovery data voltage VREC, and can also supply the display data voltage IVDATA of the target pixel as the recovery data voltage VREC.

[0069] In the same method, when the target pixel (sensing pixel) is in the M-th pixel row and the non-sensing pixel is in the M-1-th pixel row in the second frame, the panel driver can supply the display data voltage IVDATA1 of the non-sensing pixel as the recovery data voltage VREC to the target pixel during the recovery period, and can supply the display data voltage IVDATA2 of the target pixel as the recovery data voltage VREC to the target pixel.

[0070] Figure 5 It is shown Figure 2 A diagram showing the connection configuration between the unsensitized first pixel PXL1 and the sensed second pixel PXL2 in the pixel array. Figure 6 It is shown Figure 5 A diagram illustrating an implementation of the driving timing of the first pixel PXL1 and the second pixel PXL2.

[0071] exist Figure 5 In this configuration, the first pixel PXL1 and the second pixel PXL2 can be arranged adjacent to each other in the Y-axis direction and can share data line 15. The first pixel PXL1 can be located in the (N-1)th pixel row and can be supplied with the (N-1)th scan signal SCAN(N-1). The second pixel PXL2 can be located in the Nth pixel row and can be supplied with the Nth scan signal SCAN(N). The first pixel PXL1 can be a non-sensing pixel, and the second pixel PXL2 can be a sensing pixel.

[0072] exist Figure 6In this embodiment, the (N-1)th scan signal SCAN(N-1) can swing between the turn-on voltage and the turn-off voltage. Furthermore, in this embodiment, the (N-1)th scan signal SCAN(N-1) set to the turn-on voltage during the vertical active period can be defined as the first gate signal. Additionally, the Nth scan signal SCAN(N) can swing between the turn-on voltage and the turn-off voltage. In this embodiment, the Nth scan signal SCAN(N) set to the turn-on voltage during the vertical active period can be defined as the second gate signal, and the Nth scan signal SCAN(N) set to the turn-on voltage during the vertical blanking period can be defined as the third gate signal.

[0073] Reference Figure 5 and Figure 6 The data voltage supply unit can supply the first data voltage IVDATA' corresponding to the first gate signal to the first pixel PXL1 during the vertical active period of the first frame, and can supply the second data voltage IVDATA corresponding to the second gate signal to the second pixel PXL2. During the vertical blanking period of the first frame, it can continuously supply the sensing data voltage SVDATA and the recovery data voltage VREC corresponding to the third gate signal to the second pixel PXL2.

[0074] In other words, the data voltage supply unit can supply a first data voltage IVDATA' to the first pixel PXL1 via data line 15 during the on-time of the first gate signal included in the vertical active period, and can supply a second data voltage IVDATA to the second pixel PXL2 via data line 15 during the on-time of the second gate signal included in the vertical active period. Furthermore, the data voltage supply unit can continuously supply sensing data voltage SVDATA and recovery data voltage VREC to the second pixel PXL2 via data line 15 during the on-time of the third gate signal included in the vertical blanking period.

[0075] Here, during the on-time of the third gate signal included in the vertical blanking period, the recovery data voltage VREC may be supplied to the second pixel PXL2 later than the sensing data voltage SVDATA. The vertical blanking period may be temporarily divided into a sensing period Psen and a subsequent recovery period Prec. The sensing data voltage SVDATA may be supplied to the second pixel PXL2 during the sensing period Psen, and the recovery data voltage VREC may be supplied to the second pixel PXL2 during the recovery period Prec. The recovery data voltage VREC supplied to the second pixel PXL2 during the recovery period Prec may include a first data voltage IVDATA' and a second data voltage IVDATA.

[0076] The data voltage supply unit can sequentially supply a first data voltage IVDATA' and a second data voltage IVDATA to the second pixel PXL2 during the recovery period Prec included in the vertical blanking period. During the recovery period Prec, the first data voltage IVDATA' can be supplied to the second pixel PXL2, and then the second data voltage IVDATA can be supplied to the second pixel PXL2, thereby reducing the brightness deviation of the image realized in the (N-1)th pixel row and the Nth pixel row.

[0077] The sensing circuit can sense the electrical characteristics of the second pixel PXL2 based on the sensing data voltage SVDATA during the sensing period Psen in the vertical blanking period.

[0078] The gate driver can generate a first gate signal, a second gate signal, and a third gate signal. The on-time of the first gate signal can be earlier than the on-time of the second gate signal, and the on-time of the second gate signal can be earlier than the on-time of the third gate signal. The gate driver can supply a first gate signal with a first phase to a first pixel PXL1 via a first gate line arranged in the (N-1)th pixel row, and can supply a second gate signal with a second phase and a third gate signal with a third phase to a second pixel PXL2 via a second gate line adjacent to the first gate line and arranged in the Nth pixel row. Here, the first phase can be earlier than the second phase, and the second phase can be earlier than the third phase.

[0079] Figure 7 It is shown in Figure 6 In the first frame of the vertical effective period, the image pattern with a large voltage difference between the first data voltage IVDATA' supplied to the first pixel PXL1 and the second data voltage IVDATA supplied to the second pixel PXL2. Figure 8 It is shown in Figure 6 In the first frame, when displaying Figure 7 The image pattern shown is a diagram of the recovery data voltage and sensing data voltage supplied to the second pixel PXL2 during the vertical blanking period of the first frame.

[0080] exist Figure 7 In a per-image pattern, the first data voltage IVDATA' can represent a black gray level, while the second data voltage IVDATA can represent a white gray level. A per-image pattern can be understood as a pattern in which darker (e.g., black) gray data and lighter (e.g., white) gray data are alternately applied to pixels in adjacent rows.

[0081] like Figure 8In the first frame, when the recovery data voltage VREC (i.e., the first data voltage IVDATA') and the second data voltage IVDATA are sequentially supplied to the second pixel PXL2 during the recovery period Prec of the vertical blanking period while displaying image patterns one by one, the charging voltage waveform of the data line 15 associated with the display operation of the second pixel PXL2 can be the same as the charging voltage waveform of the data line 15 associated with the recovery operation of the second pixel PXL2 in the first frame. The charging voltage waveform can be described as the amount of change in the charged voltage, or voltage waveform. Specifically, the second data voltage IVDATA with a white grayscale level can be supplied to the second pixel PXL2 for the display driving of the second pixel PXL2, and therefore the data line 15 can be charged from the first data voltage VDATA' with a previous black grayscale level to the second data voltage IVDATA with a white grayscale level. A first data voltage IVDATA' having a black grayscale level and a second data voltage IVDATA having a white grayscale level can be continuously supplied to the second pixel PXL2 for the recovery drive of the second pixel PXL2, and thus data line 15 can be charged from the first data voltage IVDATA' having the previous black grayscale level to the second data voltage IVDATA having the white grayscale level. When the charging voltage waveform of data line 15 associated with the display operation of the second pixel PXL2 and the charging voltage waveform of data line 15 associated with the recovery operation of the second pixel PXL2 are the same, the brightness deviation between pixel rows caused by the difference in charging voltage waveforms can be reduced.

[0082] Furthermore, in electroluminescent display devices employing VRR technology, the effect of reducing brightness deviation may be even greater when the recovery data voltage is configured using a combination of two display data voltages. This is because the length of the vertical blanking period, and in this case, the recovery period, can increase with increasing frame rate. The longer the recovery period, the more effective the application of the two display data voltages in reducing brightness deviation.

[0083] Figure 9 It is shown in Figure 6 A monochrome image pattern in which there is no voltage difference between the first data voltage IVDATA' supplied to the first pixel and the second data voltage IVDATA supplied to the second pixel during the vertical blanking period of the first frame. Figure 10 It is shown in Figure 6 In the first frame, when displaying Figure 9 The monochrome image pattern shown is a diagram of the recovery data voltage and sensing data voltage supplied to the second pixel during the vertical blanking period of the first frame.

[0084] exist Figure 9In a monochrome image pattern, the first data voltage IVDATA' and the second data voltage IVDATA can represent the same gray level.

[0085] like Figure 10 In the first frame, when the monochrome image pattern is displayed, the recovery data voltage VREC (i.e., the first data voltage IVDATA') and the second data voltage IVDATA are sequentially supplied to the second pixel PXL2 during the recovery period Prec of the vertical blanking period. The charging voltage waveform of the data line 15 associated with the display operation of the second pixel PXL2 can be the same as the charging voltage waveform of the data line 15 associated with the recovery operation of the second pixel PXL2 in the first frame. Therefore, the brightness deviation between pixel rows caused by the difference in charging voltage waveform can be reduced.

[0086] Figure 11 It is shown Figure 5 A diagram of another embodiment of the driving timing of the first and second pixels.

[0087] exist Figure 11 In this embodiment, the (N-1)th scan signal SCAN(N-1) can swing between the turn-on voltage and the turn-off voltage. Furthermore, in this embodiment, the (N-1)th scan signal SCAN(N-1) with the turn-on voltage set during the vertical active period of the first frame can be defined as the first gate signal. Additionally, the Nth scan signal SCAN(N) can swing between the turn-on voltage and the turn-off voltage. In this embodiment, the Nth scan signal SCAN(N) with the turn-on voltage set during the vertical active period of the first frame can be defined as the second gate signal, and the Nth scan signal SCAN(N) with the turn-on voltage set during the vertical blanking period of the first frame can be defined as the third gate signal. Furthermore, in this embodiment, the Nth scan signal SCAN(N) with the turn-on voltage set during the vertical active period of the second frame can be defined as the fourth gate signal.

[0088] Reference Figure 5 and Figure 11 The data voltage supply unit can supply the first data voltage IVDATA' corresponding to the first gate signal SCAN(N-1) to the first pixel PXL1 during the vertical active period of the first frame, and can supply the second data voltage IVDATA corresponding to the second gate signal SCAN(N) to the second pixel PXL2. During the vertical blanking period of the first frame, it continuously supplies the sensing data voltage SVDATA and the recovery data voltage VREC corresponding to the third gate signal to the second pixel PXL2, and during the vertical active period of the second frame after the first frame, it supplies the fourth data voltage IVDATA-1 corresponding to the fourth gate signal to the second pixel PXL2.

[0089] In other words, the data voltage supply unit can supply a first data voltage IVDATA' to the first pixel PXL1 via data line 15 during the on-time of the first gate signal included in the vertical active period of the first frame, and can supply a second data voltage IVDATA to the second pixel PXL2 via data line 15 during the on-time of the second gate signal included in the vertical active period of the first frame. The data voltage supply unit can continuously supply sensing data voltage SVDATA and recovery data voltage VREC to the second pixel PXL2 via data line 15 during the on-time of the third gate signal included in the vertical blanking period of the first frame. Furthermore, the data voltage supply unit can supply a fourth data voltage IVDATA-1 to the second pixel PXL2 via data line 15 during the on-time of the fourth gate signal included in the vertical active period of the second frame following the first frame.

[0090] The sensing data voltage SVDATA can be supplied to the second pixel PXL2 during the sensing period Psen, and the recovery data voltage VREC can be supplied to the second pixel PXL2 during the recovery period Prec. The recovery data voltage VREC supplied to the second pixel PXL2 during the recovery period Prec may include a first data voltage IVDATA', a second data voltage IVDATA, and a pre-charge voltage PC.

[0091] The data voltage supply unit can sequentially supply a first data voltage IVDATA', a second data voltage IVDATA, and a pre-charge voltage PC to the second pixel PXL2 during the recovery period Prec included in the vertical blanking period. During the recovery period Prec, the first data voltage IVDATA' can be supplied to the second pixel PXL2, and then the second data voltage IVDATA can be supplied to the second pixel PXL2, thereby reducing the brightness deviation of the image realized in the (N-1)th pixel row and the Nth pixel row.

[0092] The pre-charge voltage PC can be supplied to the second pixel PXL2 during the recovery period Prec, after the second data voltage IVDATA is supplied. The pre-charge voltage PC can be used to increase the speed at which the fourth data voltage IVDATA-1 is charged into the second pixel PXL2 during the vertical active period of the second frame. For this purpose, the pre-charge voltage PC can be the average voltage between the second data voltage IVDATA and the fourth data voltage IVDATA-1.

[0093] The sensing circuit can sense the electrical characteristics of the second pixel PXL2 based on the sensing data voltage SVDATA during the sensing period Psen in the vertical blanking period.

[0094] The gate driver can generate a first gate signal, a second gate signal, a third gate signal, and a fourth gate signal. The on-time of the first gate signal can be earlier than the on-time of the second gate signal, and the on-time of the second gate signal can be earlier than the on-time of the third gate signal. Furthermore, the on-time of the third gate signal can be earlier than the on-time of the fourth gate signal. The gate driver can supply a first gate signal with a first phase (the term "phase" as used herein can be understood as "timing" or "on-time") to the first pixel PXL1 via a first gate line arranged in the (N-1)th pixel row, and can supply a second gate signal with a second phase and a third gate signal with a third phase to the second pixel PXL2 via a second gate line adjacent to the first gate line and arranged in the Nth pixel row. Here, the first phase can be earlier than the second phase, the second phase can be earlier than the third phase, and the third phase can be earlier than the fourth phase.

[0095] Furthermore, the gate driver can generate a fifth gate signal with a fifth phase that is later than the third phase and earlier than the fourth phase in the second frame, and can also supply the fifth gate signal to the first pixel PXL1 through the first gate line. The fifth gate signal can be the (N-1)th scan signal SCAN(N-1) with an on-state voltage set during the vertical active period of the second frame.

[0096] The fourth gate signal, the fourth data voltage IVDATA-1 synchronized with the fourth gate signal, the fifth gate signal, and the fifth data voltage IVDATA'-1 synchronized with the fifth gate signal can be signals used to display and drive the second pixel PXL2 and the first pixel PXL1 in the second frame, respectively. That is, the fifth data voltage can be described as the data voltage applied to the first pixel PXL1 in the second effective frame, and the fourth data voltage can be described as the data voltage applied to the second pixel PXL2 in the second effective frame.

[0097] In this embodiment, the recovery data voltage supplied to the sensing pixel during the vertical blanking period of each frame can be configured by a combination of two display data voltages. The two display data voltages may include a first data voltage supplied to adjacent pixels and a second data voltage supplied to the sensing pixel during the vertical active period of each frame. Adjacent pixels (i.e., pixels adjacent to the sensing pixel) may share data lines with the sensing pixel and may be scanned before the sensing pixel.

[0098] Therefore, in this embodiment, the charging voltage waveform of the data line associated with the display operation of the sensing pixel can be the same as the charging voltage waveform of the data line associated with the recovery operation of the sensing pixel in each frame, and thus the brightness deviation between pixel rows caused by the difference in charging voltage waveform can be reduced.

[0099] Furthermore, according to this embodiment, the effect of reducing brightness deviation can be obtained because the recovery data voltage is configured by a combination of two display data voltages, and it can also be increased in electroluminescent display devices based on VRR technology.

[0100] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0101] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the appended claims.

[0102] The following numbering schemes are also described in this article:

[0103] Option 1. An electroluminescent display device, comprising:

[0104] The display panel includes a first pixel and a second pixel;

[0105] A data voltage supply unit, wherein during the vertical active period of the first frame, the data voltage supply unit supplies a first data voltage corresponding to a first gate signal to the first pixel and a second data voltage corresponding to a second gate signal to the second pixel, and during the vertical blanking period of the first frame, continuously supplies a sensing data voltage and a recovery data voltage corresponding to a third gate signal to the second pixel; and

[0106] A sensing circuit that senses the electrical characteristics of the second pixel based on the sensing data voltage during the vertical blanking period;

[0107] During the vertical blanking period, the recovered data voltage is supplied to the second pixel later than the sensed data voltage, and

[0108] The recovery data voltage supplied to the second pixel during the vertical blanking period includes the first data voltage and the second data voltage.

[0109] Option 2. The electroluminescent display device according to Option 1, wherein, during the recovery period included in the vertical blanking period, the first data voltage and the second data voltage are sequentially supplied to the second pixel.

[0110] Option 3. The electroluminescent display device according to Option 1 or Option 2, wherein, during the recovery period included in the vertical blanking period, the first data voltage is supplied to the second pixel, and then the second data voltage is supplied to the second pixel.

[0111] Option 4. The electroluminescent display device according to any of the foregoing options further includes a gate driver for generating the first gate signal, the second gate signal, and the third gate signal.

[0112] The gate driver supplies a first gate signal with a first phase to the first pixel via a first gate line, and supplies a second gate signal with a second phase and a third gate signal with a third phase to the second pixel via a second gate line adjacent to the first gate line.

[0113] The first phase is earlier than the second phase, and

[0114] The second phase is earlier than the third phase.

[0115] Option 5. The electroluminescent display device according to any of the preceding options, wherein the first pixel and the second pixel share the data line of the display panel.

[0116] Solution 6. The electroluminescent display device according to any of the preceding solutions, wherein the data voltage supply unit supplies the first data voltage to the first pixel through the data line during the on-time of the first gate signal included in the vertical effective time period.

[0117] During the on-time of the second gate signal included in the vertical effective period, the second data voltage is supplied to the second pixel through the data line, and

[0118] During the on-time of the third gate signal included in the vertical blanking period, the sensing data voltage and the recovery data voltage are continuously supplied to the second pixel through the data line, and

[0119] The first gate signal is turned on earlier than the second gate signal, and the second gate signal is turned on earlier than the third gate signal.

[0120] Solution 7. The electroluminescent display device according to any of the preceding solutions, wherein the data voltage supply unit further supplies a fourth data voltage corresponding to the fourth gate signal to the second pixel during the vertical effective time period of the second frame following the first frame, and

[0121] The recovery data voltage supplied to the second pixel during the vertical blanking period of the first frame also includes a pre-charge voltage, which is used to increase the speed at which the fourth data voltage is charged into the second pixel during the vertical active period of the second frame.

[0122] Option 8. The electroluminescent display device according to any of the preceding options, wherein the pre-charge voltage is the average voltage between the second data voltage and the fourth data voltage.

[0123] Solution 9. A panel driving device, comprising:

[0124] A data voltage supply unit supplies a first data voltage corresponding to a first gate signal to a first pixel of the display panel and a second data voltage corresponding to a second gate signal to a second pixel of the display panel during the vertical active period of the first frame; and continuously supplies a sensing data voltage and a recovery data voltage corresponding to a third gate signal to the second pixel during the vertical blanking period of the first frame; and

[0125] A sensing circuit that senses the electrical characteristics of the second pixel based on the sensing data voltage during the vertical blanking period;

[0126] Specifically, during the on-time of the third gate signal included in the vertical blanking period, the recovery data voltage is supplied to the second pixel later than the sensing data voltage, and

[0127] The recovery data voltage supplied to the second pixel during the vertical blanking period includes the first data voltage and the second data voltage.

[0128] Solution 10. The panel driving device according to Solution 9, wherein, during the recovery period included in the vertical blanking period, the first data voltage and the second data voltage are sequentially supplied to the second pixel.

[0129] Option 11. The panel driving device according to Option 9 or Option 10, wherein, during the recovery period included in the vertical blanking period, the first data voltage is supplied to the second pixel, and then the second data voltage is supplied to the second pixel.

[0130] Option 12. The panel driving device according to any one of Options 9 to 11, further comprising: a gate driver, the gate driver generating the first gate signal, the second gate signal and the third gate signal;

[0131] The gate driver supplies a first gate signal with a first phase to the first pixel via a first gate line, and supplies a second gate signal with a second phase and a third gate signal with a third phase to the second pixel via a second gate line adjacent to the first gate line.

[0132] The first phase is earlier than the second phase, and

[0133] The second phase is earlier than the third phase.

[0134] Option 13. The panel driving device according to any one of options 9 to 12, wherein the first pixel and the second pixel share a data line.

[0135] Option 14. The panel driving apparatus according to any one of Options 9 to 13, wherein the data voltage supply unit supplies the first data voltage to the first pixel via the data line during the on-time of the first gate signal included in the vertical effective time period.

[0136] During the on-time of the second gate signal included in the vertical effective period, the second data voltage is supplied to the second pixel through the data line, and

[0137] During the on-time of the third gate signal included in the vertical blanking period, the sensing data voltage and the recovery data voltage are continuously supplied to the second pixel through the data line, and

[0138] The first gate signal is turned on earlier than the second gate signal, and the second gate signal is turned on earlier than the third gate signal.

[0139] Solution 15. The panel driving apparatus according to any one of Solutions 9 to 14, wherein the data voltage supply unit further supplies a fourth data voltage corresponding to the fourth gate signal to the second pixel during a vertically active period of a second frame following the first frame, and

[0140] The recovery data voltage supplied to the second pixel during the vertical blanking period of the first frame also includes a pre-charge voltage, which is used to increase the speed at which the fourth data voltage is charged into the second pixel during the vertical active period of the second frame.

[0141] Option 16. The panel driving device according to any one of options 9 to 15, wherein the pre-charge voltage is the average voltage between the second data voltage and the fourth data voltage.

[0142] Solution 17. A panel driving method, comprising:

[0143] During the vertical effective period of the first frame, a first data voltage corresponding to a first gate signal is supplied to the first pixel of the display panel, and a second data voltage corresponding to a second gate signal is supplied to the second pixel of the display panel;

[0144] During the vertical blanking period of the first frame, a sensing data voltage corresponding to the third gate signal is supplied to the second pixel, and the electrical characteristics of the second pixel are sensed based on the sensing data voltage; and

[0145] During the vertical blanking period of the first frame, a recovery data voltage corresponding to the third gate signal is supplied to the second pixel.

[0146] Specifically, during the on-time of the third gate signal included in the vertical blanking period, the recovery data voltage is supplied to the second pixel later than the sensing data voltage, and

[0147] The recovery data voltage supplied to the second pixel during the vertical blanking period includes the first data voltage and the second data voltage.

[0148] Solution 18. The panel driving method according to Solution 17, wherein, during the recovery period included in the vertical blanking period, the first data voltage and the second data voltage are sequentially supplied to the second pixel.

[0149] Option 19. The panel driving method according to Option 17 or Option 18, wherein, during the recovery period included in the vertical blanking period, the first data voltage is supplied to the second pixel, and then the second data voltage is supplied to the second pixel.

Claims

1. A panel driving device, comprising: Data voltage supply unit, the data voltage supply unit being arranged as follows: During the effective time period of the first frame, a first data voltage corresponding to the first gate signal is supplied to the first pixel of the display panel; During the effective time period of the first frame, a second data voltage corresponding to the second gate signal is supplied to the second pixel of the display panel; as well as During the blanking period of the first frame, a sensing data voltage and a recovery data voltage are supplied to the second pixel, the sensing data voltage and the recovery data voltage corresponding to a third gate signal; as well as A sensing circuit, configured to sense the electrical characteristics of the second pixel based on the sensing data voltage during the blanking period. The data voltage supply unit is configured to supply the sensing data voltage to the second pixel during the blanking period, and then supply the recovery data voltage to the second pixel. The recovered data voltage includes the first data voltage and the second data voltage. Wherein, the first pixel is in a non-sensing pixel row, and the second pixel is in a sensing pixel row adjacent to the non-sensing pixel row, and During the recovery period included in the blanking period, the data voltage supply unit is arranged to supply the first data voltage to the second pixel and then supply the second data voltage to the second pixel.

2. The panel driving device according to claim 1, wherein, The data voltage supply unit is further arranged to supply the sensing data voltage to the second pixel during the on-time of the third gate signal included in the blanking period, and then to supply the recovery data voltage to the second pixel.

3. The panel driving apparatus according to claim 1 or 2, further comprising a gate driver, the gate driver being arranged to generate the first gate signal, the second gate signal, and the third gate signal. in, The gate driver is arranged to supply the first gate signal to the first pixel via a first gate line, and to supply the second gate signal and the third gate signal to the second pixel via a second gate line adjacent to the first gate line. The first gate signal is supplied before the second gate signal, and The second gate signal is supplied before the third gate signal.

4. The panel driving device according to claim 1 or 2, wherein, The first pixel and the second pixel share the data line of the display panel.

5. The panel driving device according to claim 4, wherein, The data voltage supply unit is arranged as follows: During the on-time of the first gate signal included in the effective time period, the first data voltage is supplied to the first pixel through the data line; During the on-time of the second gate signal included in the effective time period, the second data voltage is supplied to the second pixel through the data line; and During the blanking period, when the third gate signal is turned on, the sensing data voltage and the recovery data voltage are supplied to the second pixel via the data line. Wherein, the turn-on period of the first gate signal is earlier than the turn-on period of the second gate signal, and the turn-on period of the second gate signal is earlier than the turn-on period of the third gate signal.

6. The panel driving device according to claim 1 or 2, wherein, The data voltage supply unit is further arranged to supply the second pixel with a fourth data voltage corresponding to the fourth gate signal during an effective time period of the second frame following the first frame, and The recovery data voltage also includes a pre-charge voltage, which is used to increase the speed at which the fourth data voltage is charged to the second pixel during the effective period of the second frame.

7. The panel driving device according to claim 6, wherein, The pre-charge voltage is the average voltage between the second data voltage and the fourth data voltage.

8. An electroluminescent display device, comprising: The panel driving device according to any one of claims 1 to 7; as well as The display panel includes the first pixel and the second pixel.

9. A panel driving method, comprising: During the effective time period of the first frame, a first data voltage corresponding to the first gate signal is supplied to the first pixel of the display panel; During the effective time period of the first frame, a second data voltage corresponding to the second gate signal is supplied to the second pixel of the display panel; During the blanking period of the first frame, a sensing data voltage is supplied to the second pixel, and the electrical characteristics of the second pixel are sensed based on the sensing data voltage; as well as During the blanking period of the first frame, a recovery data voltage is supplied to the second pixel. Wherein, the sensed data voltage and the recovered data voltage correspond to the third gate signal. Specifically, after the sensing data voltage is supplied to the second pixel during the blanking period, the recovery data voltage is supplied to the second pixel. The recovery data voltage supplied to the second pixel during the blanking period includes the first data voltage and the second data voltage. Wherein, the first pixel is in a non-sensing pixel row, and the second pixel is in a sensing pixel row adjacent to the non-sensing pixel row, and During the recovery period included in the blanking period, the first data voltage is supplied to the second pixel, and then the second data voltage is supplied to the second pixel.

10. The panel driving method according to claim 9, wherein, After the sensing data voltage is supplied to the second pixel during the on-time of the third gate signal included in the blanking period, the recovery data voltage is supplied to the second pixel.

11. The panel driving method according to claim 9 or 10, further comprising: Generate the first gate signal, the second gate signal, and the third gate signal. The first gate signal is supplied to the first pixel through a first gate line, and the second gate signal and the third gate signal are supplied to the second pixel through a second gate line adjacent to the first gate line. Wherein, the first gate signal is supplied before the second gate signal, and The second gate signal is supplied before the third gate signal.

12. The panel driving method according to claim 9 or 10, wherein, The first pixel and the second pixel share the data line of the display panel.

13. The panel driving method according to claim 12, further comprising: During the on-time of the first gate signal included in the effective time period, the first data voltage is supplied to the first pixel through the data line; During the on-time of the second gate signal included in the effective time period, the second data voltage is supplied to the second pixel through the data line; and During the blanking period, when the third gate signal is turned on, the sensing data voltage and the recovery data voltage are supplied to the second pixel via the data line. Wherein, the turn-on period of the first gate signal is earlier than the turn-on period of the second gate signal, and the turn-on period of the second gate signal is earlier than the turn-on period of the third gate signal.

14. The panel driving method according to claim 9 or 10, further comprising: During the effective time period of the second frame following the first frame, a fourth data voltage corresponding to the fourth gate signal is supplied to the second pixel, and The recovery data voltage also includes a pre-charge voltage, which is used to increase the speed at which the fourth data voltage is charged to the second pixel during the effective period of the second frame.

15. The panel driving method according to claim 14, wherein, The pre-charge voltage is the average voltage between the second data voltage and the fourth data voltage.

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