Panel driving device, panel driving method, and electroluminescent display device

Abstract

The present disclosure relates to a panel driving apparatus, a panel driving method, and an electroluminescent display apparatus. The electroluminescent display apparatus can include a display panel including a pixel, a data voltage supply circuit configured to supply a sensing data voltage to the pixel in a sensing period within a vertical blanking period of a first frame, supply a recovery data voltage to the pixel in a recovery period after the sensing period, and supply a display data voltage to the pixel in a vertical active period of a second frame after the first frame, and a sensing circuit configured to sense an electrical characteristic of the pixel based on the sensing data voltage in the sensing period within the vertical blanking period of the first frame. A level of the display data voltage to be supplied to the pixel in the vertical active period of the second frame can be determined based on a length of the vertical blanking period of the first frame.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0187581, filed on December 24, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to panel driving devices, panel driving methods, and electroluminescent display devices.

[0004] Related technologies

[0005] Each pixel of an electroluminescent display device includes a self-emitting light-emitting device, and the amount of light emitted from the light-emitting device is controlled by a data voltage based on the gray level of the image data to adjust the brightness.

[0006] Electroluminescent display devices use external compensation techniques to improve image quality. External compensation techniques are based on real-time sensing of pixel voltage or current according to the electrical characteristics of the pixels, and modulating the input image data based on the sensing results to compensate for electrical characteristic deviations between pixels.

[0007] An electroluminescent display device, after sensing the electrical characteristics of a corresponding pixel during a vertical blank period of a frame, performs a recovery operation on the corresponding pixel, and thus restores the brightness of the corresponding pixel to display the state immediately before sensing.

[0008] Because the length of the recovery period of the sensing pixel is changed based on the frame rate (i.e., the charging and holding time of the recovery data voltage), electroluminescent display devices of related technologies often have the problem that the display state of the sensing pixel is not properly recovered and brightness distortion occurs. Summary of the Invention

[0009] Therefore, embodiments of this disclosure relate to panel driving apparatus, driving methods thereof, and electroluminescent display devices incorporated herein, which substantially eliminate one or more problems caused by limitations and disadvantages of related technologies. For example, embodiments of this disclosure can reduce luminance distortion in sensing pixels in variable frame rate modes.

[0010] To achieve these and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, an electroluminescent display device may include: a display panel configured to display an image and including pixels; a data voltage supply circuit configured to supply a sensed data voltage to the pixels during a sensing period in a vertical blank period of a first frame, to supply a recovery data voltage to the pixels during a recovery period following the sensing period, and to supply a display data voltage to the pixels during a vertical active period of a second frame following the first frame; and a sensing circuit configured to sense the electrical characteristics of the pixels based on the sensed data voltage during the sensing period in the vertical blank period of the first frame, wherein the level of the display data voltage to be supplied to the pixels during the vertical active period of the second frame may be determined based on the length of the vertical blank period of the first frame.

[0011] In another aspect of this disclosure, a panel driving device for use with a display panel configured to display an image and include pixels is disclosed. The panel driving device may include: a data voltage supply circuit configured to supply a sensed data voltage to the pixel during a sensing period in a vertical blank period of a first frame, to supply a recovery data voltage to the pixel during a recovery period after the sensing period, and to supply a display data voltage to the pixel during a vertical active period of a second frame after the first frame; and a sensing circuit configured to sense the electrical characteristics of the pixel based on the sensed data voltage during the sensing period in the vertical blank period of the first frame, wherein the level of the display data voltage to be supplied to the pixel during the vertical active period of the second frame can be determined based on the length of the vertical blank period.

[0012] In another aspect of this disclosure, a panel driving method for a display panel configured to display an image and including pixels is provided. The panel driving method may include: supplying a sensing data voltage to the pixels during a sensing period in a vertical blank period of a first frame, and sensing the electrical characteristics of the pixels based on the sensing data voltage; supplying a recovery data voltage to the pixels during a recovery period after the sensing period; determining a display data voltage based on the length of the vertical blank period of the first frame; and supplying the display data voltage to the pixels during a vertical active period of a second frame after the first frame. Attached Figure Description

[0013] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0014] Figure 1This is a diagram illustrating an electroluminescent display device including a panel driving device according to an embodiment of the present disclosure;

[0015] Figure 2 It is shown Figure 1 A diagram of the pixel array included in an electroluminescent display device;

[0016] Figure 3 It is shown Figure 2 A diagram showing the pixels included in the pixel array and the sensing circuit connected to them;

[0017] Figure 4 This is a diagram illustrating the operation timing, sensing operation timing, and recovery operation timing in a comparative example of the present disclosure in a fixed frame frequency mode;

[0018] Figure 5 and Figure 6 This is a diagram used to describe the Variable Refresh Rate (VRR) technology, which changes the frame rate based on the input image;

[0019] Figure 7 This is a diagram used to illustrate an example of brightness distortion in the sensing pixel caused by the difference in the length of the vertical blank period in a variable frame rate mode;

[0020] Figure 8 and Figure 9 This is a diagram illustrating an implementation method for reducing luminance distortion in sensing pixels under a variable frame rate mode;

[0021] Figure 10 This is a diagram illustrating the lookup table, where data offset values ​​of different sizes are mapped to each other based on the length of the recovery period; and

[0022] Figure 11 This is a diagram illustrating a panel driving method for reducing luminance distortion in sensing pixels in a variable frame rate mode. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms, and it should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0024] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary, and this disclosure is not limited thereto. The same reference numerals always refer to the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms "comprising," "containing," "including," etc., imply that additional parts may be added, unless the term "only" is used. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0025] Even if not explicitly stated otherwise, elements in the various embodiments of this disclosure should be interpreted as including error margins.

[0026] When describing positional relationships, for example, when the positional relationship between two parts is described as "on top of", "above", "below", and "near", one or more other parts can be placed between the two parts, unless "just" or "directly" is used.

[0027] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0028] Similar reference numerals are used throughout the text to refer to similar elements.

[0029] In this specification, the gate drive circuit disposed on the substrate of the display panel can be implemented using a thin-film transistor (TFT) with an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure, but is not limited thereto, and can also be implemented using a TFT with a p-type MOSFET structure. The TFT can be a three-electrode element including a gate, a source, and a drain. The source can be the electrode that provides charge carriers to the transistor. In a TFT, charge carriers can flow from the source. The drain can be the electrode that allows charge carriers to flow out of the TFT. That is, in a MOSFET, charge carriers flow from the source to the drain. In an n-type TFT (NMOS), because the charge carriers are electrons, the source voltage can be lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-type TFT, because electrons flow from the source to the drain, current can flow from the drain to the source. On the other hand, in a p-type TFT (PMOS), because the charge carriers are holes, the source voltage can be higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-type TFT, current can flow from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed, but switch between the two. For example, the source and drain of a MOSFET can switch between the two. Therefore, in the embodiments describing this disclosure, one of the source and drain will be described as a first electrode, and the other of the source and drain will be described as a second electrode.

[0030] In the following description, detailed descriptions of known functions or configurations will be omitted where it is determined that such descriptions unnecessarily obscure the focus of this disclosure. Hereinafter, embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 This is a diagram illustrating an electroluminescent display device including a panel driving device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A diagram of the pixel array included in an electroluminescent display device. Figure 3 It is shown Figure 2 The diagram shows the pixels included in the pixel array and the sensing circuit connected to them.

[0032] Reference Figures 1 to 3 An electroluminescent display device according to embodiments of this disclosure may include a display panel 10, a timing controller 11, a data driver 12, a gate driver 13, and a sensing circuit 122. In this disclosure, the data voltage supply circuit 121, the gate driver 13, and the sensing circuit 122 can implement a panel driving device. The data voltage supply circuit 121 and the sensing circuit 122 can be embedded in the integrated circuit (IC) of the data driver 12.

[0033] The display panel 10 may include multiple data lines 15, multiple readout lines 16, and multiple gate lines 17. Furthermore, multiple pixels PXL may be arranged in multiple intersecting regions between the data lines 15, readout lines 16, and gate lines 17. Figure 2 The pixel array shown may include multiple pixels PXL arranged in a matrix type and may be set in the display area AA of the display panel 10.

[0034] In a pixel array, a pixel row can be implemented using pixels PXL that are adjacent to each other in the extension direction of gate line 17 (i.e., the X-axis direction). Each pixel row may include multiple pixels PXL that are adjacent to each other in the X-axis direction. Pixels PXL configured in the same pixel row can be connected to the same gate line 17 and can be connected to different data lines 15. Pixels PXL configured in the same pixel row can be connected to different readout lines 16, but are not limited thereto, and multiple pixels PXL used to implement different colors can share a single readout line 16.

[0035] In the pixel array, each pixel PXL can be connected to the data driver 12 via one of the data lines 15 and one of the readout lines 16, and can be connected to the gate driver 13 via one of the gate lines 17. Furthermore, each pixel PXL can be connected to the high-level pixel power supply EVDD via the high-level power supply line 18.

[0036] In the pixel array, pixel PXL may include pixels implementing a first color, pixels implementing a second color, and pixels implementing a third color, and may also include pixels implementing a fourth color. The first to fourth colors may optionally be one of red, green, blue, and white.

[0037] Each pixel PXL can be like Figure 3 It can be achieved in that way, but is not limited to that.

[0038] like Figure 3 As shown, the pixel PXL arranged in the k-th (where k is an integer) pixel row may include a light-emitting device EL, a driving transistor DT, a storage capacitor Cst, a first switching transistor ST1 and a second switching transistor ST2, and the first switching transistor ST1 and the second switching transistor ST2 may be connected to the same gate line 17(k).

[0039] The light-emitting device (EL) can emit light using pixel current. The EL may include an anode electrode connected to the source node Ns, a cathode electrode connected to the low-level pixel power supply EVSS, and an organic or inorganic compound layer disposed between the anode and cathode electrodes. The organic or inorganic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The EL can be turned on when the voltage applied to the anode electrode is higher than the EL operating point voltage compared to the low-level pixel power supply EVSS applied to the cathode electrode. When the EL is turned on, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) can move to the emission layer (EML) to generate excitons; therefore, light can be emitted from the emission layer (EML).

[0040] The driving transistor DT can be a driving element. The driving transistor DT can generate a pixel current flowing in the light-emitting device EL based on the voltage difference between the gate node Ng and the source node Ns. The driving transistor DT may include a gate electrode connected to the gate node Ng, a first electrode connected to the high-level pixel power supply EVDD, and a second electrode connected to the source node Ns.

[0041] The storage capacitor Cst can be connected between the gate node Ng and the source node Ns, and can store the gate-source voltage of the driving transistor DT.

[0042] The first switching transistor ST1 can electrically connect the data line 15 to the gate node Ng based on the gate signal SCAN(k), and can apply the data voltage VDATA charged in the data line 15 to the gate node Ng. The first switching transistor ST1 may include a gate electrode connected to the gate line 17(k), a first electrode connected to the data line 15, and a second electrode connected to the gate node Ng.

[0043] The second switching transistor ST2 can electrically connect the readout line 16 to the source node Ns based on the gate signal SCAN(k), and can apply the voltage of the source node Ns to the readout line 16 based on the pixel current, or can apply the reference voltage Vref charged in the readout line 16 to the source node Ns. The second switching transistor ST2 may include a gate electrode connected to the gate line 17(k), a first electrode connected to the source node Ns, and a second electrode connected to the readout line 16.

[0044] Such a pixel structure may be merely one implementation method, and the inventive concept is not limited thereto. It should be noted that the inventive concept can be applied to various pixel structures used for sensing the electrical characteristics (threshold voltage or electron mobility) of the driving transistor DT.

[0045] The timing controller 11 can be connected to the host system 14 via a first interface circuit and to the data driver 12 via a second interface circuit. The first interface circuit and the second interface circuit can be the same or different.

[0046] The timing controller 11 can receive the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the input video data DATA from the host system 14 through the first interface circuit. The timing controller 11 can receive the input video data DATA during the vertical active period of each frame and can not receive the input video data DATA during the vertical blank period of each frame.

[0047] A frame can be defined by a vertical synchronization signal Vsync and a data enable signal DE. Furthermore, a vertical active period and a vertical blank period within a frame can be defined. A frame can be defined as the interval between adjacent pulses of the vertical synchronization signal Vsync. The vertical active period can be defined as the period within a frame during which the data enable signal DE is shifted between logic high and logic low levels. The vertical blank period can be defined as the period within a frame during which the data enable signal DE is held at a logic low level.

[0048] The length of the vertical blank period can vary based on the vertical synchronization signal Vsync and the data enable signal DE. The host system 14 can change the length of the vertical blank period based on the complexity of the input video data DATA and the amount of inter-frame variation in the input video data DATA, etc., to change the frame rate while the display panel 10 is being driven. When the input video data DATA is complex and has a large amount of inter-frame variation, for example, the host system 14 can lengthen the vertical blank period in each frame, thereby reducing the frame rate. When the length of the vertical blank period varies within a frame, the duration of a frame and the frame rate can vary. This can be referred to as Variable Refresh Rate (VRR) technology. VRR technology can adequately ensure the rendering time for graphics processing in the host system 14 to prevent image tearing and thus provide a smoother image.

[0049] The host system 14 can be mounted on a system board. The host system 14 may include: input circuitry that receives user commands / data; main power circuitry that generates main power; VRR control circuitry that changes the frame rate based on the input image; and output circuitry that outputs a transmission signal. The host system 14 can be implemented using an application processor, a personal computer (PC), a set-top box, or graphics processing circuitry, but is not limited to these.

[0050] The timing controller 11 can control the control drive to display-drive the display panel 10, and thus, the input image can be reproduced in the display panel 10. The timing controller 11 can control the control drive to sense-drive the display panel 10 during a vertical blank period of one frame, and then resume-drive the display panel 10.

[0051] Sensing drive can be used to sense the electrical characteristics of the driving transistor DT included in the pixel PXL and can be performed simultaneously, for example, by a single pixel row unit. In the pixel PXL being sensed, the light-emitting device can stop emitting light during sensing drive to enhance sensing accuracy. Sensing drive can be performed sequentially or non-sequentially by a single pixel row unit during the vertical blank period of each frame. During the vertical blank period of each frame, pixel rows other than the one currently being sensed can maintain the display state of the previous vertically active period.

[0052] The recovery drive can be used to restore the luminance (brightness) of pixels PXL in a row of pixels where the sensing drive has ended (i.e., a row of sensing pixels) to the display state immediately preceding the sensing drive. A recovery data voltage can be applied to pixels PXL in the row of sensing pixels for recovery drive. In this case, based on the control of controller 11, the panel driving device can apply a recovery data voltage with the same level as the display data voltage immediately preceding the sensing drive to pixels PXL in the row of sensing pixels. Therefore, the corresponding pixel PXL in the row of sensing pixels can emit light again, thereby restoring the brightness of the row of sensing pixels to the state immediately preceding the sensing drive.

[0053] The timing controller 11 can generate timing control signals for the panel driving devices used in display driving, sensing driving, and recovery driving. The timing controller 11 can provide timing control signals to the data driver 12 and the gate driver 13 respectively via a second interface circuit. The timing control signals for the panel driving devices may include a data timing control signal DDC for controlling the operating timing of the data driver 12 and a gate timing control signal GDC for controlling the operating timing of the gate driver 13.

[0054] The timing controller 11 can receive sensing result data based on the sensing drive from the data driver 12 via the second interface circuit. The electrical characteristics of the driving transistor DT included in each of the sensing pixels PXL can be reflected in the sensing result data. The timing controller 11 can calculate a pixel compensation value based on the sensing result data and can apply the pixel compensation value to the input video data DATA received from the host system 14, thereby compensating for the deviation in the electrical characteristics of the driving transistor DT between pixels PXL. The timing controller 11 can supply the image data DATA obtained through correction based on the pixel compensation value to the data driver 12 via the second interface circuit.

[0055] The timing controller 11 can control the operation of the panel driver based on the timing control signals GDC and DDC during the vertical effective time period of each frame, and thus can realize display driving. In display driving, the panel driver can supply display data voltage for displaying the input image to all pixels PXL of the pixel array.

[0056] The timing controller 11 can control the operation of the panel driving device based on the timing control signals GDC and DDC during the vertical blank periods of each frame, and thus can realize sensing drive and display drive. In sensing drive, the panel driving device can supply sensing data voltage for sensing to the pixels PXL of the sensing pixel row. In recovery drive, the panel driving device can supply recovery data voltage for restoring the display state immediately preceding the sensing drive to the pixels PXL of the sensing pixel row. Therefore, the emission state of the pixels PXL interrupted in the sensing drive can be restored by the recovery drive.

[0057] The gate driver 13 can be positioned in the non-display area NA of the display panel 10 based on the in-panel gate driver (GIP) type. The gate driver 13 can generate a scan signal SCAN that oscillates between on-state and off-state voltages based on the gate timing control signal GDC. The gate driver 13 can sequentially supply scan signals SCAN(1) to SCAN(4) line by line to each of the gate lines 17 during the vertical active period of each frame, including... Figure 2 Gate lines 17(1) to 17(4) are shown. Gate driver 13 can supply scan signal SCAN to gate line 17 of pixel PXL connected to the sensing pixel row during the vertical blank period of each frame.

[0058] The data driver 12 can be implemented using a data IC. The data driver 12 may include a data voltage supply circuit (DAC) 121 and a sensing circuit (SU) 122. The data voltage supply circuit (DAC) 121 generates a data voltage VDATA based on a data timing control signal DDC. The data voltage VDATA can be divided into a display data voltage, a sensed data voltage, and a recovered data voltage.

[0059] A data voltage supply circuit (DAC) 121 can be connected to the pixel array via one or more data lines 15. The DAC 121 can generate a display data voltage with a level varying based on the grayscale level of the image data DATA during the vertical active period of each frame and can supply the display data voltage to the data lines 15. The display data voltage can be supplied to the gate node Ng of the pixel PXL synchronously with the scan signal SCAN. The DAC 121 can also generate a sensing data voltage during the vertical blank period of each frame and can supply the sensing data voltage to the data lines 15, and then generate a recovery data voltage and supply the recovery data to the data lines 15. The sensing data voltage and the recovery data voltage can be supplied to the gate node Ng of the sensing target pixel PXL synchronously with the scan signal SCAN.

[0060] The sensing circuit (SU) 122 can be connected to the pixel array via one or more readout lines 16. Through the readout lines 16, the sensing circuit (SU) 122 can sense the pixel current flowing in the target pixel PXL in response to a sensing data voltage, or it can sense the source node (Ns) voltage of the target pixel PXL based on the pixel current. The pixel current or source node (Ns) voltage can be an electrical characteristic of the target pixel PXL and can vary based on the degree of degradation of the target pixel PXL.

[0061] The sensing circuit (SU) 122 can be implemented as a voltage sensing type that samples the source node voltage, or as a current sensing type that samples the pixel current.

[0062] like Figure 3 The example voltage-sensing type sensing circuit (SU) 122 shown may include a sampling circuit SAM and an analog-to-digital converter ADC. The sampling circuit SAM can directly sample the source node voltage of the sensing target pixel PXL stored in the parasitic capacitor (not shown) on the readout line 16. The analog-to-digital converter ADC can convert the analog voltage obtained by sampling through the sampling circuit SAM into a digital sensing result value and can transmit the digital sensing result value to the timing controller 11.

[0063] The current-sensing type sensing circuit (SU) 122 may include, for example, a current integrator, a sampling circuit, and an analog-to-digital converter. The current integrator can determine the integral of the pixel current flowing in the sensing target pixel PXL to output a sensing voltage. The sampling circuit can sample the sensing voltage output from the current integrator. The analog-to-digital converter can convert the analog voltage obtained by the sampling circuit into a digital sensing result value, and can transmit the digital sensing result value to the timing controller 11.

[0064] In each of the display driver, sensing driver, and recovery driver, the sensing circuit (SU) 122 can turn on the first switch SW1 to charge the reference voltage Vref to the readout line 16 based on the timing of supplying the data voltage VDATA to the data line 15. The reference voltage Vref charged to the readout line 16 can be supplied to the source node Ns of the pixel PXL synchronously with the scan signal SCAN.

[0065] Figure 4 This is a diagram illustrating the operation timing, sensing operation timing, and recovery operation timing in a comparative example of the present disclosure in a fixed frame frequency mode.

[0066] like Figure 4 As shown, each frame may include a vertical active period and a vertical blank period. Under the control of a timing controller, the panel driving device can sequentially scan all pixel rows of the pixel array during the vertical active period while simultaneously writing display data voltage IVDATA corresponding to image data to all pixels. Therefore, the panel driving device can display-drive the display panel. The panel driving device can select predetermined sensing pixel rows (N, M) during the sensing period RT of the vertical blank period based on the control of the timing controller, and can supply sensing data voltage SVDATA to the pixels of the sensing pixel rows (N, M) to sense-drive the display panel. Then, the panel driving device can supply recovery data voltage VREC to the pixels of the sensing pixel rows (N, M) during the recovery period of the vertical blank period to recover-drive the display panel. The pixels of the sensing pixel rows (N, M) can be turned on (illuminate) based on the display drive, can be turned off (not illuminated) during the sensing drive, and can be turned on again (illuminate) based on the recovery drive. The pixels of the sensing pixel rows (N, M) can be restored to the image data display state immediately preceding the sensing (i.e., the vertical active period) through the recovery drive.

[0067] Furthermore, the Nth pixel row that performs sensing and recovery operations during the vertical blank period of the Nth frame and the Mth pixel row that performs sensing and recovery operations during the vertical blank period of the Mth frame may not emit light when performing sensing operations. Therefore, brightness differences may occur between non-sensing pixel rows, and sensing pixel rows (N, M) can be seen as lines.

[0068] To reduce the visibility of the sensing pixel rows (N, M), the panel driver can supply a recovery data voltage VREC, including recovery compensation values ​​30A and 30B, to the sensing pixel rows (N, M) under the control of a timing controller. The recovery compensation values ​​30A and 30B can vary based on the sensing pixel rows (N, M). This is because the positions of the sensing pixel rows (N, M) in the display panel can be different, and therefore, the charging and holding periods t2 and t4 (i.e., the recovery periods) corresponding to the recovery data voltage VREC can differ between the sensing pixel rows (N, M).

[0069] The Nth pixel row can be positioned closer to the top of the display panel and can have a relatively high scan order during the vertical effective time period. Therefore, a recovery data voltage VREC including a relatively large compensation value 30A can be used to supply the Nth pixel row. On the other hand, the Mth pixel row can be positioned closer to the bottom of the display panel and can have a relatively low scan order during the vertical effective time period. Therefore, a recovery data voltage VREC including a relatively small compensation value 30B can be used to supply the Mth pixel row. As described above, when the level of the recovery data voltage VREC is adjusted based on the length of the recovery time period, the brightness deviation between the sensed pixel rows (N, M) can be reduced.

[0070] The above concept can be applied only to fixed frame frequency modes and not to variable frame frequency modes such as VRR technology. This is because in variable frame frequency modes, the length of the recovery period based on the pixel row at the same position varies with the frame frequency, but how the length of the recovery period can vary at the time when the recovery data voltage VREC is being supplied may not be known or determined by the timing controller.

[0071] Figure 5 and Figure 6 This is a diagram used to describe VRR technology, which changes the frame rate based on the input image.

[0072] like Figure 5 As shown, the host system can change the frame rate by altering the length of the vertical blank period (i.e., the length of the non-transition period of the data enable signal DE) based on the data rendering time of the input image. Variations in the frame rate can address issues such as screen dropouts, screen jitter, or input lag caused by sudden changes in the image. The host system can adjust the frame rate within a frequency range of 40Hz to 240Hz based on the data rendering time of the input image. Specifically, for still images, the host system can adjust the frame rate within a frequency range of 1Hz to 10Hz, but this disclosure is not limited to this. The range of the variable frame rate can be set differently based on model and device specifications.

[0073] like Figure 5 As shown, the example host system can fix the length of the vertical effective time period and can adjust the length of the vertical blank time period based on the data rendering time of the input image, thus changing the frame rate. For example, as Figure 6 As shown, in 144Hz mode, the host system can set the length of the vertical blank period to "Vblank1" and adjust the length of the non-transition period of the data enable signal DE corresponding to "Vblank1". In 100Hz mode, the host system can set the length of the vertical blank period to "Vblank2", which is "X" larger than "Vblank1", and adjust the length of the non-transition period of the data enable signal DE corresponding to "Vblank2". In 80Hz mode, the host system can set the length of the vertical blank period to "Vblank3", which is "Y" larger than "Vblank1", and adjust the length of the non-transition period of the data enable signal DE corresponding to "Vblank3". In 60Hz mode, the host system can set the length of the vertical blank period to "Vblank4", which is "Z" larger than "Vblank1", and adjust the length of the non-transition period of the data enable signal corresponding to "Vblank4".

[0074] Figure 7 This is a diagram used to illustrate an example of brightness distortion occurring in the sensing pixel due to differences in the length of the vertical blank period in a variable frame rate mode.

[0075] like Figure 7 As shown, when the length of the vertical blank period varies in the variable frame rate mode, the corresponding lengths of the recovery periods Prec1 and Prec2 can also vary. For example, the length of the recovery period Prec2 corresponding to a frame rate of 75Hz can be longer than the length of the recovery period Prec1 corresponding to a frame rate of 120Hz.

[0076] During the recovery period, the recovery data voltage VREC can be supplied to the gate electrode of the driving transistor DT included in the sensing pixel, and the reference voltage Vref can be supplied to the source electrode of the driving transistor DT. The pixel current flowing in the driving transistor DT can be proportional to the difference between the gate voltage VG and the source voltage VS (i.e., the gate-source voltage Vgs). The source voltage VS can be increased by the pixel current, and when the recovery period is short, the display drive of the next frame can start when the source voltage VS has not increased sufficiently and is relatively low. For example, in a comparison between a 75Hz frame frequency and a 120Hz frame frequency, the gate-source voltage Vgs1 may be relatively high at a 120Hz frame frequency with a relatively short recovery period Prec1, while the gate-source voltage Vgs2 may be relatively low at a 75Hz frame frequency with a relatively long recovery period Prec2. Therefore, luminance distortion may be more likely to occur at a 120Hz frame frequency where the recovered brightness of the sensing pixel is higher than at a 75Hz frame frequency.

[0077] Figure 8 and Figure 9 This is a diagram illustrating an example implementation for reducing luminance distortion in sensing pixels under variable frame rate mode. Figure 10 This is a diagram showing a lookup table where data offset values ​​of different sizes are mapped to each other based on the length of the vertical blank period or the length of the recovery period.

[0078] Figure 8 The driving waveform in AHz (where A is 120) mode is shown, and Figure 9 The driving waveform in the B Hz (where B is 75) mode is shown.

[0079] like Figure 8 As shown, in 120Hz mode, the data voltage supply circuit can supply the sensing data voltage SVDATA20 to the target pixel of the sensing pixel row during the sensing period in the vertical blank period of the first frame, supply the recovery data voltage VREC 30 to the target pixel during the first recovery period Prec1 after the sensing period, and supply the first display data voltage IVDATA2 40A to the target pixel during the vertical active period of the second frame after the first frame.

[0080] like Figure 9As shown, in the 75 Hz mode, the data voltage supply circuit supplies the sensed data voltage SVDATA20 to the target pixel of the sensing pixel during the sensing period in the vertical blanking period of the first frame, supplies the restored data voltage VREC 30 to the target pixel during the second restoration period Prec2 after the sensing period, and supplies the second display data voltage IVDATA2 40 to the target pixel during the vertical active period of the second frame after the first frame.

[0081] As Figures 8 to 10 shown, in order to reduce the occurrence of luminance distortion in the sensing pixel in a variable frame frequency environment, the level of the display data voltage IVDATA2 supplied to the target pixel during the vertical active period of the second frame can be set to increase in proportion to the length of the vertical blanking period.

[0082] For this purpose, the timing controller can count the number of horizontal synchronization signals Hsync arranged between the falling edge FE of the last data enable signal DE of the first frame and the rising edge RE of the first data enable signal DE of the second frame to calculate the length of the vertical blanking period. The timing controller can calculate the respective lengths of the restoration periods Prec1 and Prec2, and the restoration periods Prec1 and Prec2 can start from the vertical blanking period of the first frame and continue until before the display data voltage IVDATA2 is supplied to the target pixel during the vertical active period of the second frame. The respective lengths of the restoration periods Prec1 and Prec2 can be proportional to the lengths of the respective vertical blanking periods.

[0083] In Figure 10 this case, the count value Hsync_CNT of the horizontal synchronization signal Hsync can represent the length of the vertical blanking period. In order to increase the level of the display data voltage IVDATA2 in proportion to the length of the vertical blanking period, the timing controller can read the data offset value corresponding to the count value Hsync_CNT of the horizontal synchronization signal Hsync from the look-up table (for example, as Figure 10 shown, the data offset value corresponding to Hsync_CNT = X1 is -10 LSB, the data offset value corresponding to Hsync_CNT = X2 is -5 LSB, the data offset value corresponding to Hsync_CNT = X3 is -1 LSB, the data offset value corresponding to Hsync_CNT = X4 is 0 LSB, where X1 < X2 < X3 < X4), and can add the data offset value to the display data voltage IVDATA2. In Figure 10 the look-up table, the magnitude of the data offset value can increase as the length of the vertical blanking period (or the length of the corresponding restoration period) increases or the frame frequency decreases.

[0084] For example, in 120Hz mode, a first display data voltage IVDATA2 40A can be obtained by adding a first data offset value (e.g., -10LSB) to the display data voltage IVDATA2, and in 75Hz mode, a second display data voltage IVDATA2 40A can be obtained by adding a second data offset value (e.g., 0LSB) to the display data voltage IVDATA2.

[0085] Because the first display data voltage IVDATA2 40A corresponding to the 120Hz mode is less than the second display data voltage IVDATA2 40A corresponding to the 75Hz mode, brightness distortion caused by the perceived pixels appearing too bright can be prevented in the 120Hz mode, where the recovery period is relatively short. This is because display brightness is proportional to the level of the display data voltage.

[0086] Furthermore, regardless of changes in frame frequency and / or target pixel position, the level of the recovery data voltage VREC30 can be set to be equal to the level of the display data voltage IVDATA110 supplied to the target pixel during the vertical effective blanking of the first frame. In this example embodiment, the level of the recovery data voltage can be adjusted without considering the target pixel position. Adjusting the level of the recovery data voltage based on the target pixel position requires the timing controller to have advance information on the position-based length of the recovery period. For example, Figure 4 The concept of adjusting the recovery data voltage level shown can be applied to a fixed frame frequency environment, but not to a variable frame frequency environment. This is because in a variable frame frequency environment, the length of the vertical blank period is calculated based on the rising edge RE of the first data enable signal DE of the second frame, and therefore, the length of the recovery period is unknown before the rising edge RE of the first data enable signal ED of the second frame. That is, because the recovery period begins before the rising edge RE of the first data enable signal DE of the second frame, which is the vertical blank period of the first frame, the timing controller may not calculate the length of the vertical blank period at the beginning of the recovery period. Therefore, the length of the vertical blank period (or the length of the recovery period) may be unknown at the beginning of the recovery period.

[0087] Figure 11 This is a diagram illustrating a panel driving method for reducing luminance distortion in sensed pixels in a variable frame rate mode.

[0088] like Figure 11As shown, the panel driving method according to the example embodiment of this disclosure can supply sensing data voltage to the pixels of the display panel during the sensing period in the vertical blank period, and can sense the electrical characteristics of the pixels based on the sensing data voltage. Furthermore, during the recovery period following the sensing period, the panel driving method can supply recovery data voltage to the pixels to restore the display state of the pixels to the display state immediately preceding the sensing (S10 and S20).

[0089] According to an example embodiment of this disclosure, the panel driving method can count the number of horizontal synchronization signals Hsync arranged during the vertical blank period to calculate the length of the vertical blank period (S30) and determine the count value. Furthermore, the panel driving method can read a data offset value from a lookup table based on the count value and apply the data offset value to the display data voltage to be input to the pixel in the next frame (S40 and S50). Therefore, possible luminance distortion in the pixel can be reduced in a variable frame rate environment.

[0090] In this embodiment, the display data voltage to be supplied in the next frame can be adjusted based on the change in the recovery period caused by the change in frame frequency in the variable frame frequency mode. Therefore, in this embodiment, brightness distortion caused by differences in the length of the recovery period can be prevented, thereby improving display quality.

[0091] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0092] While this disclosure has been specifically shown and described with reference to its exemplary embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the following claims.

Claims

1. An electroluminescent display device, comprising: A display panel configured to display an image and including pixels; A data voltage supply circuit is configured to supply a sensing data voltage to the pixel during a sensing period in the vertical blank period of a first frame, to supply a recovery data voltage to the pixel during a recovery period after the sensing period, and to supply a display data voltage to the pixel during the vertical active period of a second frame after the first frame. A sensing circuit configured to sense the electrical characteristics of the pixel based on the sensing data voltage during the sensing period in the vertical blank period of the first frame; as well as A timing controller is configured to determine the display data voltage based on the length of the vertical blank period, such that the display data voltage increases as the length of the vertical blank period increases. The level of the display data voltage to be supplied to the pixel during the vertical active period of the second frame is determined based on the length of the vertical blank period of the first frame.

2. The electroluminescent display device according to claim 1, wherein, The timing controller is also configured to determine the length of the vertical blank period based on the number of horizontal synchronization signals in the vertical blank period.

3. The electroluminescent display device according to claim 1, wherein, The timing controller is also configured to determine the length of the vertical blank period, determine a data offset value based on the length of the vertical blank period, and determine the display data voltage by adding the data offset value to a data voltage corresponding to the input image data.

4. The electroluminescent display device according to claim 1, wherein, The recovery period begins during the vertical blank period of the first frame and continues into the second frame until the display data voltage is supplied to the pixel during the vertical active period of the second frame. The length of the recovery period is proportional to the length of the vertical blank period.

5. The electroluminescent display device according to claim 1, wherein, The display panel is configured to be driven at a variable frame rate, and The length of the recovery period is configured to increase as the frame frequency decreases.

6. The electroluminescent display device according to claim 5, in, The timing controller is also configured to determine the length of the recovery period, determine a data offset value based on the length of the recovery period, and determine the display data voltage by adding the data offset value to a data voltage corresponding to the input image data.

7. The electroluminescent display device according to claim 6, wherein, The data offset value increases as the length of the recovery period increases or the frame frequency decreases.

8. The electroluminescent display device according to claim 6, wherein, The timing controller is also configured to: Add the first data offset value to the data voltage provided at the first frame frequency; and The second data offset value is added to the data voltage provided at a second frame frequency lower than the first frame frequency. The second data offset value is larger than the first data offset value.

9. The electroluminescent display device according to claim 1, wherein, The data voltage supply circuit is further configured to supply a first display data voltage to the pixel during the vertical active period of the first frame, prior to the vertical blank period of the first frame, and The level of the restored data voltage is equal to the level of the first displayed data voltage.

10. A panel driving device for use with a display panel configured to display an image and including pixels, the panel driving device comprising: A data voltage supply circuit is configured to supply a sensing data voltage to the pixel during a sensing period in the vertical blank period of a first frame, to supply a recovery data voltage to the pixel during a recovery period after the sensing period, and to supply a display data voltage to the pixel during the vertical active period of a second frame after the first frame. as well as A sensing circuit configured to sense the electrical characteristics of the pixel based on the sensing data voltage during a sensing period in the vertical blank period of the first frame. The level of the display data voltage to be supplied to the pixel during the vertical effective period of the second frame is determined based on the length of the vertical blank period. The voltage of the displayed data increases as the length of the vertical blank period increases.

11. The panel driving device according to claim 10, wherein: The recovery period begins during the vertical blank period of the first frame and continues into the second frame until the display data voltage is supplied to the pixel during the vertical active period of the second frame. The length of the recovery period is proportional to the length of the vertical blank period.

12. The panel driving device according to claim 10, wherein, The panel driving device is configured to drive the pixels at a variable frame rate. The length of the recovery period is configured to increase as the frame frequency decreases, and The display data voltage is determined by adding a data offset value to a data voltage corresponding to the input image data, the data offset value being determined based on the length of the recovery period.

13. The panel driving device according to claim 12, wherein, The data offset value is configured to increase as the length of the recovery period increases or the frame frequency decreases.

14. The panel driving device according to claim 12, wherein, The first data offset value is configured to be added to the data voltage provided at the first frame frequency. The second data offset value is configured to be added to the data voltage provided at a second frame frequency lower than the first frame frequency, and The second data offset value is greater than the first data offset value.

15. The panel driving device according to claim 10, wherein, The data voltage supply circuit is further configured to supply a first display data voltage to the pixel during the vertical active period of the first frame, prior to the vertical blank period of the first frame, and The level of the restored data voltage is equal to the level of the first displayed data voltage.

16. A panel driving method for a display panel, the display panel being configured to display an image and including pixels, the method comprising: During the sensing period in the vertical blank period of the first frame, a sensing data voltage is supplied to the pixel, and the electrical characteristics of the pixel are sensed based on the sensing data voltage; During the recovery period following the sensing period, a recovery data voltage is supplied to the pixel; The display data voltage is determined based on the length of the vertical blank period in the first frame; as well as During the vertical effective period of the second frame following the first frame, the display data voltage is supplied to the pixel. Determining the display data voltage includes setting the display data voltage such that it increases as the length of the vertical blank period increases.

17. The method according to claim 16, wherein, Determining the voltage of the displayed data includes: The length of the vertical blank period is determined by counting the number of horizontal synchronization signals in the vertical blank period. Determine the data offset value corresponding to the count of the horizontal synchronization signal; and The data offset value is added to the data voltage corresponding to the input image data to determine the display data voltage.

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