Gate drive circuit and display device including the same

Abstract

The present disclosure relates to a gate driving circuit and a display apparatus including the same, and more particularly, to a gate driving circuit having a reduced size and a display apparatus including the same. The gate driving circuit includes a plurality of dummy stage circuits and a stage circuit which provide a gate signal for each gate line and include a Q node, a QH node, and a QB node. A gate signal output circuit included in each stage circuit can output first to jth gate signals based on a first to jth scan clock signal or a first low voltage according to a voltage level of the Q node or a voltage level of the QB node.

Description

Technical Field

[0001] The present disclosure relates to a gate driving circuit and an electronic device including the same, and more particularly, to a gate driving circuit and a display device including the same. Background Art

[0002] Recently, display devices using flat display panels, such as liquid crystal display devices, organic light emitting diode display devices, light emitting diode display devices, and electrophoretic display devices, have been widely used.

[0003] The display device may include a light-emitting element and a pixel having a pixel circuit for driving the light-emitting element. For example, the pixel circuit includes a driving transistor for controlling a driving current provided to the light-emitting element, and at least one switching transistor for controlling (or programming) a gate-source voltage of the driving transistor according to a gating signal. The switching transistor of the pixel circuit can be switched by a gating signal provided by a gating driving circuit provided on a substrate of the display panel.

[0004] The display device includes a display area that displays an image and a non-display area that does not display an image. As the size of the non-display area decreases, the size of the edge or frame area of ​​the display device decreases, and the size of the display area increases. Summary of the Invention

[0005] In the display device, since the gate driving circuit is disposed in the non-display area, the size of the display area can be increased as the size of the gate driving circuit is reduced.

[0006] The gate driver circuit may include multiple stage circuits. Each stage circuit may include multiple transistors for generating a gate signal. As the number of transistors included in each stage circuit increases, the size of the stage circuit and the size of the gate driver circuit increase. Therefore, in order to reduce the size of the gate driver circuit and increase the size of the display area, it is desirable to reduce the number of transistors included in each stage circuit.

[0007] As the number of times the transistor included in each stage circuit is driven increases, the characteristics of the transistor (e.g., the value of the threshold voltage) will change. When the voltage at the control node decreases as the value of the threshold voltage of the transistor changes, the transistor cannot be completely cut off. As a result, in the process of driving the gate drive circuit, leakage current may be generated in each stage circuit. If the gate signal cannot be output normally due to this leakage current, the image quality of the display device may deteriorate.

[0008] Furthermore, as the number of times a transistor included in each stage circuit is driven increases, the transistor may rapidly deteriorate, and the life of the display device may be shortened.

[0009] The present disclosure provides implementations that address one or more of these issues.

[0010] According to an embodiment of the present disclosure, a gate driving circuit having a reduced size and a display device having an increased display area size are provided by reducing the number of transistors included in a stage circuit and the number of lines connected to the transistors.

[0011] According to an embodiment of the present disclosure, a gate driving circuit and a display device having improved durability and reliability are provided by reducing voltage stress of transistors included in a stage circuit and thereby enabling the life of the transistors to be extended.

[0012] According to an embodiment of the present disclosure, by changing the connection structure of the carry signal line of the stage circuit, display artifacts such as horizontal lines caused in VRR driving can be reduced or eliminated.

[0013] The problems or issues to be solved herein are not limited to the above description, and other problems or issues to be solved will become apparent to those skilled in the art from the following description.

[0014] According to one aspect of the present disclosure, a gate drive circuit is provided, which includes multiple stage circuits and multiple virtual stage circuits, the multiple stage circuits are capable of providing a gate signal to each of a plurality of gate lines and include an M node, a Q node, a QH node and a QB node, and the multiple virtual stage circuits are configured in a previous stage of a first stage circuit in the multiple stage circuits so as to stably output the gate signal.

[0015] In one embodiment, each of the plurality of stage circuits may include a line selector, a Q-node controller, Q-node and QH-node stabilization circuits, an inverter, a QB-node stabilization circuit, a carry signal output circuit, and a strobe signal output circuit.

[0016] The line selector may charge the M node based on the previous stage carry signal in response to an input of a line sensing ready signal, and charge the Q node to a first high voltage level in response to an input of a reset signal or discharge the Q node to a third low voltage level in response to an input of a panel on signal.

[0017] The Q node controller may charge the Q node to a first high voltage level in response to input of a start signal or a previous stage carry signal, and discharge the Q node to a third low voltage level in response to input of a subsequent stage carry signal.

[0018] The Q-node and QH-node stabilization circuit may discharge the Q-node and the QH-node to a third low voltage level when the QB-node is charged to the second high voltage level.

[0019] The inverter may change the voltage level of the QB node according to the voltage level of the Q node.

[0020] The QB node stabilization circuit may discharge the QB node to a third low voltage level in response to an input of a previous stage carry signal, an input of a reset signal, and a charged voltage of the M node.

[0021] The carry signal output circuit may output the carry signal C(k) based on the voltage level of the carry clock signal CRCLK(k) according to the voltage level of the Q node or based on the third low voltage (GVSS3) level according to the voltage level of the QB node.

[0022] The gate signal output circuit may output first to j-th gate signals based on the first to j-th scan clock signals or the first low voltage according to a voltage level of the Q node or a voltage level of the QB node.

[0023] In one embodiment, the dummy stage circuits may be set almost simultaneously in response to a start signal and output carry signals whose phases are sequentially delayed in synchronization with the gated shift clock.

[0024] Each dummy stage circuit may include a Q-node controller, a Q-node and QH-node stabilization circuit, an inverter, and a carry signal output circuit, and further include an FB TFT circuit.

[0025] The FB TFT circuit is designed to have the same circuit structure as the T3 TFT, with the same gate-source voltage Vgs applied as the T3 TFT. In this case, when the T3 TFT deteriorates due to positive bias temperature stress (PBTS), the threshold voltage Vth of the FB TFT circuit shifts positively, and the corresponding flowing current decreases. The PGVDD voltage generation block (not shown) can sense this reduced current in the FB TFT circuit and increase the corresponding PGVDD voltage by the threshold voltage Vth.

[0026] In another aspect of the present disclosure, a display device is provided, comprising: a display panel including sub-pixels formed in an intersection area of ​​a gate line and a data line; a gate driving circuit for providing a scan signal to each gate line; a data driving circuit for providing a data voltage to each data line; and a timing controller for controlling driving of the gate driving circuit and the data driving circuit.

[0027] In one embodiment, the gate drive circuit may include multiple stage circuits and multiple dummy stage circuits, the multiple stage circuits being capable of providing a gate signal to each of the multiple gate lines and including an M node, a Q node, a QH node, and a QB node, and the multiple dummy stage circuits being configured in a previous stage of a first stage circuit in the multiple stage circuits so as to stably output the gate signal.

[0028] In one embodiment, each of the plurality of stage circuits may include a line selector, a Q-node controller, Q-node and QH-node stabilization circuits, an inverter, a QB-node stabilization circuit, a carry signal output circuit, and a strobe signal output circuit.

[0029] The line selector may charge the M node based on the previous stage carry signal in response to an input of a line sensing ready signal, and charge the Q node to a first high voltage level in response to an input of a reset signal or discharge the Q node to a third low voltage level in response to an input of a panel on signal.

[0030] The Q node controller may charge the Q node to a first high voltage level in response to input of a start signal or a previous stage carry signal, and discharge the Q node to a third low voltage level in response to input of a subsequent stage carry signal.

[0031] The Q-node and QH-node stabilization circuit may discharge the Q-node and the QH-node to a third low voltage level when the QB-node is charged to the second high voltage level.

[0032] The inverter may change the voltage level of the QB node according to the voltage level of the Q node.

[0033] The QB node stabilization circuit may discharge the QB node to a third low voltage level in response to an input of a previous stage carry signal, an input of a reset signal, and a charged voltage of the M node.

[0034] The carry signal output circuit may output the carry signal C(k) based on the voltage level of the carry clock signal CRCLK(k) according to the voltage level of the Q node or based on the third low voltage (GVSS3) level according to the voltage level of the QB node.

[0035] The gate signal output circuit may output first to j-th gate signals based on the first to j-th scan clock signals or the first low voltage according to a voltage level of the Q node or a voltage level of the QB node.

[0036] In one embodiment, the dummy stage circuits may be set almost simultaneously in response to a start signal and output carry signals whose phases are sequentially delayed in synchronization with the gated shift clock.

[0037] Each dummy stage circuit may include a Q-node controller, a Q-node and QH-node stabilization circuit, an inverter, and a carry signal output circuit, and further include an FB TFT circuit.

[0038] The FB TFT circuit is designed to have the same circuit structure as the T3 TFT, with the same gate-source voltage Vgs applied as the T3 TFT. In this case, when the T3 TFT deteriorates due to positive bias temperature stress (PBTS), the threshold voltage Vth of the FB TFT circuit shifts positively, and the flowing current decreases. The PGVDD voltage generation block (not shown) can sense this reduced current in the FB TFT circuit and increase the corresponding PGVDD voltage by the threshold voltage Vth.

[0039] According to an embodiment of the present disclosure, the number of transistors included in the stage circuit of the gate driver circuit and the number of lines connected to the transistors can be reduced, and the gate driver circuit can be stably driven. If the number of transistors included in each stage circuit is reduced, the size of the gate driver circuit can be reduced, and the reduction in the size of the stage circuit can increase the size of the display area of ​​the display device. In addition, the reduction in the number of transistors included in the stage circuit can provide the advantage of making the stage circuit more simple to configure and design.

[0040] Furthermore, according to embodiments of the present disclosure, the voltage level input to the transistors included in the stage circuit can be adjusted according to the driving time of the display device. This can reduce the voltage stress of the transistors and extend the life of the transistors. Furthermore, the durability and driving reliability of the gate drive circuit and the display device can be improved.

[0041] Furthermore, according to the embodiments of the present disclosure, by changing the connection structure of the carry signal line of the stage circuit to solve the horizontal line artifact caused during VRR driving, the image display quality of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this disclosure, illustrate various aspects of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0043] Figure 1 Schematically illustrating a display device according to aspects of the present disclosure;

[0044] Figure 2 An example sub-pixel array included in a display panel of a display device according to aspects of the present disclosure is illustrated;

[0045] Figure 3 Illustrated are example circuit configurations of sub-pixels in a display device according to aspects of the present disclosure and example connection structures between a timing controller, a data driving circuit, and the sub-pixels;

[0046] Figure 4 illustrates an example configuration of a plurality of stage circuits included in a gate driving circuit according to aspects of the present disclosure;

[0047] Figure 5 is an example circuit diagram of a stage circuit included in a gate driving circuit according to aspects of the present disclosure;

[0048] Figure 6 is an example circuit diagram of a dummy stage circuit included in a gate driving circuit according to aspects of the present disclosure;

[0049] Figure 7 is a circuit diagram of another dummy stage circuit included in the gate driving circuit according to aspects of the present disclosure;

[0050] Figure 8 is a first carry signal line connection diagram of a stage circuit included in a gate drive circuit according to various aspects of the present disclosure;

[0051] Figure 9 is a second carry signal line connection diagram of a stage circuit included in a gate drive circuit according to various aspects of the present disclosure;

[0052] Figure 10 yes Figure 8 a driving timing diagram of the stage circuit in the first connection configuration;

[0053] Figure 11 yes Figure 9 a driving timing diagram of the stage circuit in the second connection configuration;

[0054] Figure 12 The gate drive circuit according to various aspects of the present disclosure is Figure 5 Waveform diagram of input signal and output signal when the stage circuit outputs the strobe signal for image display;

[0055] Figure 13 is a graph showing a change in the magnitude of the second high voltage according to a driving time of a gate driving circuit in a display device according to aspects of the present disclosure; and

[0056] Figure 14 is a graph showing changes in threshold voltage magnitudes of transistors according to driving time of a gate driving circuit in a display device according to aspects of the present disclosure. DETAILED DESCRIPTION

[0057] By referring to the embodiments of the present disclosure described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and their implementation methods will be apparent. The embodiments set forth below are described in the context of specific embodiments and are provided only to fully disclose the present disclosure and inform those skilled in the art according to the embodiments of the present disclosure. However, it will be understood that these embodiments can be implemented in various different forms, and further, many changes, modifications, additions and improvements are possible. Therefore, the scope of the present disclosure is not limited to the embodiments described below, but should be defined by the scope of the appended claims.

[0058] In addition, the shapes, sizes, proportions, angles, quantities, etc. used to describe the exemplary embodiments of the present disclosure illustrated in the accompanying drawings are merely examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally designate similar elements. In addition, in the following description of the present disclosure, when it is determined that the detailed description of the well-known functions and configurations incorporated herein may make the subject matter in some embodiments of the present disclosure unclear, these descriptions will be omitted. Terms such as "including," "having," "comprising," "comprising," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Unless the context clearly indicates otherwise, the singular form used herein is intended to include the plural form.

[0059] When explaining any element or feature in the embodiments of the present disclosure, it should be interpreted that any dimensions and relative sizes of layers, regions, and areas include tolerances or error ranges even if no specific description is given.

[0060] Spatially relative terms such as “on,” “over,” “above,” “below,” “below,” “under,” “down,” “up,” “near,” “close,” “adjacent,” etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures, and should be interpreted that one or more elements may also be “interposed” between these elements unless terms such as “directly,” “only,” etc. are used.

[0061] Time relative terms such as "after," "following," "next," "before," etc., used in this document to describe the temporal relationship between events, operations, etc., are generally intended to include events, situations, circumstances, operations, etc. that occur discontinuously, unless terms such as "directly," "immediately," etc. are used.

[0062] When discussing embodiments related to signal flow, for example, embodiments in which a signal is sent from node A to node B may include the signal being sent from node A to node B by way of another node unless "directly" or "directly" is used.

[0063] When terms such as "first," "second," etc. are used herein to describe various elements or components, it should be understood that these elements or components are not limited thereto. These terms are only used herein to distinguish one element from other elements. Therefore, in the technical concept of the present disclosure, the first element mentioned below may be the second element.

[0064] The elements or features of the various exemplary embodiments of the present disclosure may be partially or completely combined or combined with each other, and may be interlocked and operated in various technical manners that can be fully understood by those skilled in the art, and the various exemplary embodiments may be performed independently of each other or in relation to each other.

[0065] According to an embodiment of the present disclosure, the sub-pixel circuit and the gate drive circuit provided on the substrate of the display panel can be implemented using transistors having an n-type MOSFET structure. However, the embodiments of the present disclosure are not limited thereto; for example, the transistors used in the sub-pixel circuit and the gate drive circuit can be p-type MOSFETs. The transistor may include a gate, a source, and a drain. In a transistor, carriers can flow from the source to the drain. In the case of an n-type transistor, the source voltage is lower than the drain voltage, allowing electrons to move from the source to the drain because the carriers are electrons. In an n-type transistor, current can flow from the drain to the source due to the electrons moving from the source to the drain. In the case of a p-type transistor, the source voltage is higher than the drain voltage, allowing holes to move from the source to the drain because the carriers are holes. In a p-type transistor, current can flow from the source to the drain due to the holes flowing from the source to the drain. In a transistor having a MOSFET structure, the source and drain are not fixed and can therefore be interchanged depending on the applied voltage. Therefore, it should be noted that, herein, any one of the source and the drain is referred to as a first source / drain electrode, and the other of the source and the drain is referred to as a second source / drain electrode.

[0066] Hereinafter, exemplary examples of a gate drive circuit and a display device including the gate drive circuit according to various aspects of the present disclosure will be described in detail with reference to the accompanying drawings. Even when shown in different drawings, the same elements, substantially the same elements, or almost the same elements may have the same reference numerals. Since the elements in the drawings are illustrated for ease of description and may have different proportions in the gate drive circuit, display device, and electronic device, the drawings are to be regarded as illustrative in nature and not restrictive.

[0067] Figure 1 Display devices according to aspects of the present disclosure are schematically illustrated. Figure 2 An example sub-pixel array included in a display panel of a display device according to aspects of the present disclosure is illustrated.

[0068] Reference Figure 1 and Figure 2 , a display device 1 according to aspects of the present disclosure may include a display panel 10 , a data driving circuit 12 , a gate driving circuit 13 , and a timing controller 11 .

[0069] A plurality of data lines 14 and a plurality of gate lines 15 may be disposed to cross each other in the display panel 10. A plurality of sub-pixels SP may be arranged in a matrix at each intersection of the data lines 14 and the gate lines 15.

[0070] The data lines 14 may include m (m is a positive integer) data voltage supply lines (14A_1 to 14A_m) and m sensing voltage readout lines (14B_1 to 14B_m). The gate lines 15 may include n (n is a positive integer) first gate lines (15A_1 to 15A_n) and n second gate lines (15B_1 to 15B_n).

[0071] Each subpixel SP can be connected to any one of the data voltage supply lines (14A_1 to 14A_m), any one of the sensing voltage readout lines (14B_1 to 14B_m), and any one of the first gate lines (15A_1 to 15A_n) and any one of the second gate lines (15B_1 to 15B_n). Each subpixel SP can represent one of the predefined colors, and a predefined number of subpixels SP can be included in one pixel P.

[0072] Each subpixel SP may receive a data voltage through a data voltage supply line, receive a first gate signal through a first gate line, receive a second gate signal through a second gate line, and output a sensing voltage through a sensing voltage readout line.

[0073] That is to say, in Figure 2 In the subpixel array shown, the subpixels SP can operate sequentially on a horizontal line basis in response to a first selection signal provided on a horizontal line basis (L#1 to L#n) from the first selection lines (15A_1 to 15A_n) and a second selection signal provided on a horizontal line basis from the second selection lines (15B_1 to 15B_n). The subpixels SP on the same horizontal line driven for sensing operations can receive data voltages for threshold voltage sensing from the data voltage supply lines (14A_1 to 14A_m) and output the sensing voltages to the sensing voltage readout lines (14B_1 to 14B_m). Each of the first selection signal and the second selection signal can be a selection signal for sensing a threshold voltage or a selection signal for displaying an image. However, embodiments of the present disclosure are not limited thereto.

[0074] Each sub-pixel SP can receive at least one high voltage EVDD and at least one low voltage EVSS from the power management circuit 16. The sub-pixel SP may include an OLED, a driving transistor, first and second switching transistors, and a storage capacitor. In some embodiments, a light source other than the OLED may be included in the sub-pixel SP.

[0075] The transistor included in the sub-pixel SP may be a p-type or n-type transistor. The semiconductor layer of the transistor included in the sub-pixel SP may include amorphous silicon, polysilicon, or oxide.

[0076] During an image display operation, the data driving circuit 12 may convert the compensated image data MDATA input from the timing controller 11 into data voltages for image display according to the data control signal DDC and supply the converted data voltages to the data voltage supply lines ( 14A_1 to 14A_m).

[0077] During a sensing operation for sensing the threshold voltage of the driving transistor, the data driving circuit 12 may provide a data voltage for threshold voltage sensing to the sub-pixel SP according to a first selection signal for threshold voltage sensing provided on a horizontal line basis, convert the sensing voltage input from the display panel 10 through the sensing voltage readout lines (14B_1 to 14B_m) into a digital value, and provide the converted sensing value to the timing controller 11.

[0078] The gate driving circuit 13 may generate a gate signal based on the gate control signal GDC. The gate signal may include a first threshold voltage sensing gate signal, a second threshold voltage sensing gate signal, a first image display gate signal, and a second image display gate signal.

[0079] During a sensing operation, the gate drive circuit 13 may provide a first threshold voltage sensing gate signal to the first gate lines (15A_1 to 15A_n) on a horizontal line basis, and provide a second threshold voltage sensing gate signal to the second gate lines (15B_1 to 15B_n) on a horizontal line basis. During an image display operation, the gate drive circuit 13 may provide a first image display gate signal to the first gate lines (15A_1 to 15A_n) on a horizontal line basis, and provide a second image display gate signal to the second gate lines (15B_1 to 15B_n) on a horizontal line basis. In one embodiment, the gate drive circuit 13 may be provided in the display panel 10 as a gate driver within a panel (GIP) type.

[0080] The timing controller 11 can generate a data control signal DDC for controlling the operation timing of the data driving circuit 12 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE provided from the host system 2. The timing controller 11 can use the sensed value provided from the data driving circuit 12 to compensate for the image data DATA provided from the host system 2, thereby generating compensated image data MDATA for compensating for the difference in the threshold voltage of the driving transistor, and provide the compensated image data MDATA to the data driving circuit 12.

[0081] The power management circuit 16 can generate and provide several types of voltages required to drive the display device 1 based on the power supplied from the host system 2. In one embodiment, the power management circuit 16 can generate at least one driving voltage EVDD and at least one base voltage (EVSS) for driving each subpixel SP based on the input voltage Vin supplied from the host system 2, and supply the generated driving voltage EVDD and base voltage (EVSS) to the display panel 10. As another embodiment, the power management circuit 16 can generate at least one gate driving voltage GVDD and at least one gate base voltage GVSS for driving the gate driving circuit 13, and supply the generated gate driving voltage GVDD and gate base voltage GVSS to the gate driving circuit 13.

[0082] Figure 3 An example circuit configuration of a sub-pixel in a display device according to aspects of the present disclosure and an example connection structure between a timing controller, a data driving circuit, and the sub-pixel are illustrated.

[0083] Reference Figure 3 , the sub-pixel SP may include an OLED, a driving transistor DT, a storage capacitor Cst, a first switching transistor ST1 and a second switching transistor ST2.

[0084] The OLED may include an anode electrode connected to the second node N2, a cathode electrode connected to a low voltage supply line or a terminal for supplying a low power source of a low-level driving voltage EVSS, and an organic compound layer between the anode electrode and the cathode electrode.

[0085] The driving transistor DT can be turned on according to the gate-source voltage Vgs and control the amount of current Ioled flowing through the OLED. The driving transistor DT may include a gate electrode connected to a first node N1, a drain electrode connected to a high voltage supply line or a terminal of a high power source for providing a high-level driving voltage EVDD, and a source electrode connected to a second node N2.

[0086] The storage capacitor Cst may be connected between the first node N1 and the second node N2 .

[0087] During a sensing operation, the first switching transistor ST1 may apply the data voltage Vdata for threshold voltage sensing, which is loaded on the data voltage supply line 14A, to the first node N1 in response to a first threshold voltage sensing gate signal SCAN.

[0088] During an image display operation, the first switching transistor ST1 may apply a data voltage Vdata for image display, which is applied to the data voltage supply line 14A, to the first node N1 in response to a first image display gate signal SCAN. The first switching transistor ST1 may include a gate electrode connected to the first gate line 15A, a drain electrode connected to the data voltage supply line 14A, and a source electrode connected to the first node N1.

[0089] During the sensing operation, the second switching transistor ST2 can control the flow of current between the second node N2 and the sensing voltage readout line 14B in response to the second threshold voltage sensing selection signal SEN, thereby enabling the source voltage of the second node N2 to change by following the gate voltage at the first node N1 to be stored in the sensing capacitor Cx of the sensing voltage readout line 14B.

[0090] During an image display operation, the second switching transistor ST2 can control the flow of current between the second node N2 and the sensing voltage readout line 14B in response to the second image display selection signal SEN, thereby resetting the source voltage of the driving transistor DT to the initialization voltage Vpre. The gate electrode, drain electrode, and source electrode of the second switching transistor ST2 can be connected to the second gate line 15B, the second node N2, and the sensing voltage readout line 14B, respectively.

[0091] The data driving circuit 12 may be connected to the subpixel SP via a data voltage supply line 14A and a sensing voltage readout line 14B. A sensing capacitor Cx for storing the source voltage at the second node N2 as a sensing voltage Vsen may be connected to the sensing voltage readout line 14B. The data driving circuit 12 may include a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), an initialization switch SW1, and a sampling switch SW2.

[0092] In the first and second periods of the sensing period, the DAC may generate data voltages Vdata for threshold voltage sensing having the same level or different levels under the control of the timing controller 11, and output the generated threshold voltage sensing data voltage Vdata to the data voltage supply line 14A. During the image display period, the DAC may convert the compensated image data MDATA into a data voltage Vdata for image display, and output the converted data voltage to the data voltage supply line 14A.

[0093] The initialization switch SW1 can control the current flow between the initialization voltage supply line or the terminal of the initialization power supply for supplying the initialization voltage Vpre and the sensing voltage readout line 14B. The sampling switch SW2 can control the current flow between the sensing voltage readout line 14B and the ADC. The ADC can convert the analog sensing voltage Vsen stored in the sensing capacitor Cx into a digital sensing value and provide the converted sensing value to the timing controller 11.

[0094] The sensing operation performed by the control of the timing controller 11 is as follows. When the threshold voltage sensing first selection signal SCAN and the threshold voltage sensing second selection signal SEN having the on-level Lon are applied to the sub-pixel SP, the first switching transistor ST1 and the second switching transistor ST2 may be turned on. At this time, the initialization switch SW1 of the data driving circuit 12 may also be turned on.

[0095] When the first switching transistor ST1 is turned on, a data voltage Vdata for threshold voltage sensing can be provided to the first node N1. When the initialization switch SW1 and the second switching transistor ST2 are turned on, an initialization voltage Vpre can be provided to the second node N2. At this time, as the gate-source voltage Vgs of the driving transistor DT becomes greater than its threshold voltage Vth, a current Ioled can flow between the drain and source of the driving transistor DT. The source voltage VN2 of the driving transistor DT, which is charged at the second node N2 by this current Ioled, gradually increases. Therefore, the source voltage VN2 of the driving transistor DT follows the gate voltage VN1 of the driving transistor DT until the gate-source voltage Vgs of the driving transistor DT reaches the threshold voltage Vth.

[0096] The source voltage VN2 of the driving transistor DT increased at the second node N2 can be stored as the sensing voltage Vsen in the sensing capacitor Cx formed on the sensing voltage readout line 14B via the second switching transistor ST2. When the sampling switch SW2 in the data driving circuit 12 is turned on during the sensing period in which the second threshold voltage sensing selection signal SEN is maintained at the on-level, the sensing voltage Vsen can be detected and provided to the ADC.

[0097] The ADC may convert the analog sensing voltage Vsen stored in the sensing capacitor Cx into a digital sensing value and provide the converted sensing value to the timing controller 11 .

[0098] In one embodiment, the timing controller 11 can control the data driving circuit 12 and the selection driving circuit 13 so that a sensing operation for one horizontal line can be performed in a period between a period in which image data of one frame is displayed through an image display operation (i.e., an image display period) and a subsequent period in which a subsequent frame of image data is displayed (i.e., a blanking period).

[0099] The timing controller 11 may compensate the image data based on the sensed value obtained by the data driving circuit 12 and generate compensated image data MDATA obtained by the compensation. As the compensated image data MDATA is provided to the data driving circuit 12, an image based on the compensated image data MDATA may be displayed on the display panel 10.

[0100] Figure 4 Example configurations of a plurality of stage circuits included in a gate driving circuit according to aspects of the present disclosure are illustrated.

[0101] Reference Figure 4 , the gate drive circuit 13 according to various aspects of the present disclosure may include a first-stage circuit to a k-th stage circuit (ST(1) to ST(k)) (k is a positive integer), a gate drive voltage line 131, a clock signal line 132, a line sensing preparation signal line 133 and a reset signal line 134. In addition, the gate drive circuit 13 may include one or more previous dummy stage circuits (DST1, DST2) provided at one or more previous stages of the first-stage circuit ST(1) and at least one subsequent dummy stage circuit DST3 provided at at least one subsequent stage of the k-th stage circuit ST(k). However, the structure of the gate drive circuit is not limited thereto. For example, at least one subsequent dummy stage circuit DST3 may be omitted. For another example, the number of previous dummy stage circuits is not limited to Figure 4 Quantity shown.

[0102] The gate drive voltage line 131 can provide at least one high voltage GVDD and at least one low voltage GVSS provided from a power supply (not shown) to the first stage circuit to the kth stage circuit (ST(1) to ST(k)), the previous dummy stage circuit (DST1, DST2) and the subsequent dummy stage circuit DST3.

[0103] In one implementation, the gate driving voltage line 131 may include a plurality of high voltage lines providing respective high voltages different from one another, and a plurality of low voltage lines providing respective low voltages different from one another.

[0104] For example, the gate drive voltage line 131 may include three high voltage lines for providing a first high voltage GVDD1, a second high voltage GVDD2, and a third high voltage GVDD3, each having a voltage level different from each other, and three low voltage lines for providing a first low voltage GVSS1, a second low voltage GVSS2, and a third low voltage GVSS3, each having a voltage level different from each other. However, this is merely an example, and the number of lines included in the gate drive voltage line 131 may vary depending on the embodiment.

[0105] The clock signal line 132 can provide the clock signal CLK provided from the timing controller 11, for example, the carry clock signal CRCLK, the scan clock signal SCCLK, etc., to the first-level circuit to the k-th-level circuit (ST(1) to ST(k)), the previous virtual-level circuit (DST1, DST2) and the subsequent virtual-level circuit DST3.

[0106] The line sensing preparation signal line 133 may provide the line sensing preparation signal LSP provided from the timing controller 11 to the first to k-th stage circuits (ST(1) to ST(k)). Alternatively, the line sensing preparation signal line 133 may be connected to the previous dummy stage circuits (DST1, DST2).

[0107] The reset signal line 134 may provide the reset signal RESET provided from the timing controller 11 to the first to kth stage circuits (ST(1) to ST(k)), the previous dummy stage circuits (DST1, DST2), and the subsequent dummy stage circuit DST3.

[0108] The panel turn-on signal line 135 may provide the panel turn-on signal POS provided from the timing controller 11 to the first to kth stage circuits (ST(1) to ST(k)), the previous dummy stage circuits (DST1, DST2), and the subsequent dummy stage circuit DST3.

[0109] Although not shown, except Figure 4 Lines for supplying different signals other than the lines (131, 132, 133, and 134) shown may be further connected to the first to k-th stage circuits (ST(1) to ST(k)), the previous dummy stage circuits (DST1, DST2), and the subsequent dummy stage circuit DST3. For example, a line for supplying a start signal VST to the previous dummy stage circuits (DST1, DST2) may be additionally connected to the previous dummy stage circuits (DST1, DST2).

[0110] In response to the input of the start signal VST provided from the timing controller 124, the previous dummy stage circuit (DST1, DST2) can output a previous stage carry signal C. The previous stage carry signal C can be provided to any one of the first stage circuit to the k-th stage circuit (ST(1) to ST(k)). The previous stage carry signal C can be provided to the next stage dummy stage circuit (e.g., DST2) of the previous dummy stage circuit (DST1, DST2).

[0111] The subsequent dummy stage circuit DST3 may output a subsequent stage carry signal C. The subsequent stage carry signal C may be supplied to any one of the first to k-th stage circuits (ST(1) to ST(k)).

[0112] The first-stage circuit to the k-th-stage circuit (ST(1) to ST(k)) can be connected to each other in a ladder or cascade manner, and can also be connected to the dummy-stage circuit (DST1 to DST3) in a ladder or cascade manner.

[0113] In one embodiment, each of the first to k-th stage circuits (ST(1) to ST(k)) can output j (j is a positive integer) strobe signals SCOUT and one carry signal C. That is, any one of the first to k-th stage circuits (ST(1) to ST(k)) can output the first to j-th strobe signals and one carry signal C.

[0114] For example, in Figure 4 In the embodiment shown, each stage circuit can output four selection signals SCOUT and one carry signal C. For example, the first stage circuit ST(1) can output the first selection signal SCOUT(1), the second selection signal SCOUT(2), the third selection signal SCOUT(3), the fourth selection signal SCOUT(4) and the first carry signal C(1), and the second stage circuit ST(2) can output the fifth selection signal SCOUT(5), the sixth selection signal SCOUT(6), the seventh selection signal SCOUT(7), the eighth selection signal SCOUT(8) and the second carry signal C(2). Therefore, in Figure 4 In the embodiment of the present invention, j is equal to 4.

[0115] The number of gate signals output from the first to k-th stage circuits (ST(1) to ST(k)) may be equal to the number n of gate lines 15 provided in the display panel 10. As described above, each stage circuit may output j gate signals. Therefore, the relationship of j×k=n holds.

[0116] For example, due to Figure 4 In the embodiment shown, j=4, so the number of stage circuits k is equal to 1 / 4 of the number n of gate lines 15. That is, in Figure 4 In the embodiment of , k=n / 4.

[0117] However, the number of strobe signals output by each stage circuit according to an embodiment of the present disclosure is not limited thereto. That is, in some embodiments, each stage circuit may output one, two, or three strobe signals, or may output five or more strobe signals. The number of stage circuits may vary depending on the number of strobe signals output by each stage circuit.

[0118] In the following description, discussion is made based on an embodiment in which each stage circuit outputs four strobe signals SCOUT and one carry signal C; however, embodiments of the present disclosure are not limited thereto.

[0119] The selection signal SCOUT output from the first stage circuit to the k-th stage circuit (ST(1) to ST(k)) can be a selection signal for threshold voltage sensing or a selection signal for image display. The carry signal C output from the first stage circuit to the k-th stage circuit (ST(1) to ST(k)) can be provided to different stage circuits. In this document, the carry signal provided from the previous stage circuit to any stage circuit is referred to as the previous stage carry signal, and the carry signal provided from the subsequent stage circuit to the stage circuit is referred to as the subsequent stage carry signal.

[0120] Figure 5 is an example circuit diagram of a stage circuit included in a gate driving circuit according to aspects of the present disclosure.

[0121] Figure 5 The stage circuit shown is Figure 4 Any one of the first-stage to k-th-stage circuits (ST(1) to ST(k)) shown.

[0122] Reference Figure 5 In one embodiment, the stage circuit may include an M node, a Q node, a QB node, and a QH node. In one embodiment, the stage circuit may include a line selector 502, a Q node controller 504, a Q node and QH node stabilization circuit 506, an inverter 508, a QB node stabilization circuit 510, a carry signal output circuit 512, and a strobe signal output circuit 514.

[0123] The line selector 502 can charge the M node based on the previous stage carry signal C(k-2) in response to the input of the line sense preparation signal LSP. In response to the input of the reset signal RESET, the line selector 502 can charge the Q node to a first high voltage (GVDD1) level based on the charge voltage at the M node. The line selector 502 can discharge or reset the Q node to a third low voltage (GVSS3) level in response to the input of the panel start signal POS.

[0124] The line selector 502 may include first to seventh transistors T11 to T17 and a pre-charge capacitor CA.

[0125] The first transistor T11 and the second transistor T12 may be connected between the M node and a previous stage carry signal C(k-2) line for transmitting the previous stage carry signal C(k-2). The first transistor T11 and the second transistor T12 may be connected to each other in series.

[0126] In response to the input of the line sensing ready signal LSP, the first transistor T11 can output the previous stage carry signal C(k-2) to the first connection node NC1. The second transistor T12 can electrically connect the first connection node NC1 to the M node in response to the input of the line sensing ready signal LSP. For example, when the line sensing ready signal LSP having a high voltage is input to the first transistor T11 and the second transistor T12, the first transistor T11 and the second transistor T12 can be turned on at the same time, thereby allowing the M node to be charged to the first high voltage (GVDD1) level.

[0127] The third transistor T13 can be turned on when the voltage level of the M node is high and can supply the first high voltage GVDD1 to the first connection node NC1. When the first high voltage GVDD1 is supplied to the first connection node NC1, the voltage difference between the gate voltage of the first transistor T11 and the voltage of the first connection node NC1 increases. Thereafter, when the line sensing preparation signal LSP having a low level is input to the gate of the first transistor T11 and the first transistor T11 is turned off, the first transistor T11 can be completely kept in the off state due to the voltage difference between the gate voltage of the first transistor T11 and the voltage of the first connection node NC1. Therefore, current leakage of the first transistor T11 and the voltage drop of the M node caused by the current leakage of the first transistor T11 can be prevented, which enables the voltage of the M node to be stably maintained.

[0128] The precharge capacitor CA can be connected between the first high voltage line for transmitting the first high voltage GVDD1 and the M node, and stores the voltage difference between the first high voltage GVDD1 and the voltage charged in the M node. When the first transistor T11, the second transistor T12, and the third transistor T13 are turned on, the precharge capacitor CA can store the high voltage of the previous stage carry signal C(k-2). When the first transistor T11, the second transistor T12, and the third transistor T13 are turned off, the precharge capacitor CA can maintain the voltage of the M node at the stored voltage for a predetermined time.

[0129] The fourth transistor T14 and the fifth transistor T15 may be connected between a first high voltage line for transmitting the first high voltage GVDD1 and the Q node. The fourth transistor T14 and the fifth transistor T15 may be connected to each other in series.

[0130] The fourth transistor T14 and the fifth transistor T15 can charge the Q node to the first high voltage GVDD1 in response to the voltage of the M node and the input of the reset signal RESET. The fourth transistor T14 can be turned on when the voltage of the M node is at a high level and transmit the first high voltage GVDD1 to the shared node of the fourth transistor T14 and the fifth transistor T15. The fifth transistor T15 can be turned on by the reset signal RESET having a high level and provide the voltage of the shared node to the Q node. Therefore, when the fourth transistor T14 and the fifth transistor T15 are turned on at the same time, the Q node can be charged to the first high voltage GVDD1.

[0131] The sixth transistor T16 and the seventh transistor T17 may be connected between the Q node and a third low voltage line for transmitting the third low voltage GVSS3 . The sixth transistor T16 and the seventh transistor T17 may be connected to each other in series.

[0132] In response to the input of the panel start signal POS, the sixth transistor T16 and the seventh transistor T17 can discharge the Q node to the third low voltage GVSS3. The discharge of the Q node to the third low voltage GVSS3 can also be represented as resetting the Q node. The seventh transistor T17 can be turned on by the input of the panel start signal POS with a high level and provide the third low voltage GVSS3 to the QH node. The sixth transistor T16 can be turned on by the input of the panel start signal POS with a high level and electrically connect the Q node and the QH node. Therefore, when the sixth transistor T16 and the seventh transistor T17 are turned on at the same time, the Q node can be discharged or reset to the third low voltage GVSS3.

[0133] The Q node controller 504 may charge the Q node to a first high voltage (GVDD1) level in response to input of a previous stage carry signal C(k-2) and discharge the Q node to a third low voltage GVSS3 in response to input of a subsequent stage carry signal C(k+2).

[0134] The Q-node controller 504 may include first to eighth transistors T21 to T28 .

[0135] The first transistor T21 and the second transistor T22 may be connected between a first high voltage line for transmitting the first high voltage GVDD1 and the Q node. The first transistor T21 and the second transistor T22 may be connected to each other in series.

[0136] The first transistor T21 and the second transistor T22 can charge the Q node to the first high voltage (GVDD1) level in response to the input of the previous stage carry signal C(k-2). The first transistor T21 can be turned on by the input of the previous stage carry signal C(k-2) and provide the first high voltage GVDD1 to the second connection node NC2. The second transistor T22 can be turned on by the input of the previous stage carry signal C(k-2) and electrically connect the second connection node NC2 to the Q node. Therefore, when the first transistor T21 and the second transistor T22 are turned on at the same time, the first high voltage GVDD1 can be provided to the Q node.

[0137] The fifth transistor T25 and the sixth transistor T26 may be connected to a third high voltage line for transmitting the third high voltage GVDD3 . The fifth transistor T25 and the sixth transistor T26 may provide the third high voltage GVDD3 to the second connection node NC2 in response to the third high voltage GVDD3 .

[0138] Since the fifth transistor T25 and the sixth transistor T26 can be turned on at the same time by the third high voltage GVDD3, the voltage difference between the gate voltage of the first transistor T21 and the voltage of the second connection node NC2 can be increased by enabling the third high voltage GVDD3 to be constantly supplied to the second connection node NC2. Therefore, when the previous stage carry signal C(k-2) having a low level is input to the gate of the first transistor T21 and the first transistor T21 is turned off, the first transistor T21 can be completely maintained in the off state due to the voltage difference between the gate voltage of the first transistor T21 and the voltage of the second connection node NC2. Therefore, current leakage of the first transistor T21 and the voltage drop of the Q node caused by the current leakage of the first transistor T21 can be prevented, which makes it possible to stably maintain the voltage of the Q node.

[0139] For example, when the threshold voltage of the first transistor T21 is negative (-), the gate-source voltage Vgs of the first transistor T21 can be maintained at a negative (-) polarity by the third high voltage GVDD3 supplied to its drain electrode. Therefore, the previous stage carry signal C(k-2) having a low level is input to the gate of the first transistor T21, thereby turning off the first transistor T21, and the first transistor T21 can be completely maintained in the off state and can prevent the occurrence of corresponding leakage current.

[0140] In one embodiment, the third high voltage GVDD3 may be set to a voltage level lower than the first high voltage GVDD1 .

[0141] The third transistor T23 and the fourth transistor T24 may be connected between the Q node and a third low voltage line for transmitting the third low voltage GVSS3 . The third transistor T23 and the fourth transistor T24 may be connected to each other in series.

[0142] The third transistor T23 and the fourth transistor T24 can discharge the Q node and the QH node to the third low voltage GVSS3 in response to the input of the subsequent stage carry signal C(k+2). The fourth transistor T24 can be turned on by the input of the subsequent stage carry signal C(k+2) and discharge the QH node to the third low voltage GVSS3. The third transistor T23 can be turned on by the input of the subsequent stage carry signal C(k+2) and electrically connect the Q node and the QH node. Therefore, when the third transistor T23 and the fourth transistor T24 are turned on at the same time, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3.

[0143] The seventh transistor T27 and the eighth transistor T28 may be connected between the first high voltage line for transmitting the first high voltage GVDD1 and the Q node and between the first high voltage line for transmitting the first high voltage GVDD1 and the QH node. The seventh transistor T27 and the eighth transistor T28 may be connected to each other in series.

[0144] The seventh transistor T27 and the eighth transistor T28 can provide a first high voltage GVDD1 to the QH node in response to the voltage of the Q node. The seventh transistor T27 can be turned on when the voltage of the Q node is at a high level and provide the first high voltage GVDD1 to the shared node of the seventh transistor T27 and the eighth transistor T28. The eighth transistor T28 can be turned on when the voltage of the Q node is at a high level and electrically connect the shared node to the QH node. Therefore, when the voltage of the Q node is at a high level, the seventh transistor T27 and the eighth transistor T28 can be turned on at the same time and provide the first high voltage GVDD1 to the QH node.

[0145] When the first high voltage GVDD1 is supplied to the QH node, the voltage difference between the gate of the third transistor T23 and the QH node increases. Therefore, the subsequent stage carry signal C(k+2) having a low level is input to the gate of the third transistor T23, thereby turning off the third transistor T23. Due to the voltage difference between the gate voltage of the third transistor T23 and the voltage of the QH node, the third transistor T23 can be completely maintained in the off state. Therefore, current leakage of the third transistor T23 and the voltage drop of the Q node caused by the current leakage of the third transistor T23 can be prevented, which makes it possible to stably maintain the voltage of the Q node.

[0146] The Q-node and QH-node stabilization circuit 506 may discharge the Q-node and the QH-node to a third low voltage ( GVSS3 ) level in response to the voltage of the QB node.

[0147] The Q node and QH node stabilization circuit 506 may include a first transistor T31 and a second transistor T32. The first transistor T31 and the second transistor T32 may be connected between the Q node and a third low voltage line for transmitting a third low voltage GVSS3. The first transistor T31 and the second transistor T32 may be connected in series with each other.

[0148] The first transistor T31 and the second transistor T32 can discharge the Q node and the QH node to a third low voltage GVSS3 in response to the voltage of the QB node. The second transistor T32 can be turned on when the voltage of the QB node is at a high level and provide the third low voltage GVSS3 to a shared node of the first transistor T31 and the second transistor T32. The first transistor T31 can be turned on when the voltage of the QB node is at a high level and electrically connect the Q node and the QH node. Therefore, when the first transistor T31 and the second transistor T32 are simultaneously turned on by the voltage of the QB node, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3.

[0149] The inverter 508 may change the voltage level of the QB node according to the voltage level of the Q node.

[0150] The inverter 508 may include first to fifth transistors T41 to T45 .

[0151] The second transistor T42 and the third transistor T43 may be connected between a second high voltage line for transmitting the second high voltage GVDD2 and a third connection node NC3. The second transistor T42 and the third transistor T43 may be connected to each other in series.

[0152] The second transistor T42 and the third transistor T43 can provide the second high voltage GVDD2 to the third connection node NC3 in response to the second high voltage GVDD2. The second transistor T42 can be turned on by the second high voltage GVDD2 and provide the second high voltage GVDD2 to the shared node of the second transistor T42 and the third transistor T43. The third transistor T43 can be turned on by the second high voltage GVDD2 and electrically connects the shared node of the second transistor T42 and the third transistor T43 to the third connection node NC3. Therefore, when the second transistor T42 and the third transistor T43 are simultaneously turned on by the second high voltage GVDD2, the third connection node NC3 can be charged to the second high voltage (GVDD2) level.

[0153] The fourth transistor T44 may be connected between the third connection node NC3 and a second low voltage line for transmitting the second low voltage GVSS2 .

[0154] The fourth transistor T44 may provide the second low voltage GVSS2 to the third connection node NC3 in response to the voltage of the Q node. The fourth transistor T44 may be turned on when the voltage of the Q node is at a high level and discharge or reset the third connection node NC3 to the second low voltage GVSS2.

[0155] The first transistor T41 may be connected between a second high voltage line for transmitting the second high voltage GVDD2 and the QB node.

[0156] The first transistor T41 may provide the second high voltage GVDD2 to the QB node in response to the voltage of the third connection node NC3. When the voltage of the third connection node NC3 is at a high level, the first transistor T41 may be turned on and charge the QB node to the second high voltage (GVDD2).

[0157] The fifth transistor T45 may be connected between the QB node and a third low voltage line for transmitting a third low voltage GVSS3 .

[0158] The fifth transistor T45 may provide the third low voltage GVSS3 to the QB node in response to the voltage of the Q node. The fifth transistor T45 may be turned on when the Q node voltage is at a high level and discharge or reset the QB node to the third low voltage GVSS3 level.

[0159] The QB node stabilizing circuit 510 may discharge the QB node to the third low voltage GVSS3 in response to the input of the previous stage carry signal C(k−2), the input of the reset signal, and the charge voltage of the M node.

[0160] The QB node stabilization circuit 510 may include first to third transistors T51 to T53 .

[0161] The first transistor T51 may be connected between the QB node and a third low voltage line for transmitting a third low voltage GVSS3 .

[0162] The first transistor T51 can provide the third low voltage GVSS3 to the QB node in response to the input of the previous stage carry signal C(k-2). When the previous stage carry signal C(k-2) having a high level is input to the gate of the first transistor T51, the first transistor T51 can provide the third low voltage GVSS3 to the QB node.

[0163] The second transistor T52 and the third transistor T53 may be connected between the QB node and a third low voltage line for transmitting the third low voltage GVSS3 . The second transistor T52 and the third transistor T53 may be connected to each other in series.

[0164] The second transistor T52 and the third transistor T53 can discharge the QB node to a third low voltage GVSS3 level in response to the input of the reset signal and the charge voltage of the M node. The third transistor T53 can be turned on when the voltage of the M node is at a high level and provide the third low voltage GVSS3 to the shared node of the second transistor T52 and the third transistor T53. The second transistor T52 can be turned on by the input of the reset signal RESET and electrically connect the shared node of the second transistor T52 and the third transistor T53 to the QB node. Therefore, when the reset signal RESET is input as a high level of the voltage of the M node, the second transistor T52 and the third transistor T53 can be turned on at the same time and enable the QB node to be discharged or reset to the third low voltage GVSS3.

[0165] The carry signal output circuit 512 may output the carry signal C(k) based on the voltage level of the carry clock signal CRCLK(k) according to the voltage level of the Q node or based on the third low voltage ( GVSS3 ) level according to the voltage level of the QB node.

[0166] The carry signal output circuit 512 may include a first transistor T61 , a second transistor T62 , and a boosting capacitor CC.

[0167] The first transistor T61 may be connected between a clock signal line for transmitting the carry clock signal CRCLK(k) and the first output node NO1. The boosting capacitor CC may be connected between a gate and a source of the first transistor T61.

[0168] The first transistor T61 can output a carry signal C(k) having a high voltage through the first output node NO1 based on the carry clock signal CRCLK(k) in response to the voltage of the Q node. The first transistor T61 can be turned on when the voltage of the Q node is at a high level and provide the carry clock signal CRCLK(k) having a high voltage to the first output node NO1. Therefore, the carry signal C(k) having a high voltage can be output.

[0169] When the carry signal C(k) is output, the boost capacitor CC can bootstrap the voltage of the Q node in synchronization with the carry clock signal CRCLK(k) having a high voltage level until it reaches a boosted voltage level greater than the first high voltage GVDD1. When the voltage of the Q node is bootstrapped, the carry clock signal CRCLK(k) having a high voltage level can be output as the carry signal C(k) quickly and without distortion.

[0170] The second transistor T62 may be connected between the first output node NO1 and a third low voltage line for transmitting a third low voltage GVSS3 .

[0171] The second transistor T62 can output a carry signal C(k) having a low voltage based on the third low voltage GVSS3 through the first output node NO1 in response to the voltage of the QB node. The second transistor T62 can be turned on when the voltage of the QB node is at a high level and provide the third low voltage GVSS3 to the first output node NO1. Therefore, a carry signal C(k) having a low voltage can be output.

[0172] The selection signal output circuit 514 can output multiple selection signals (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) based on the voltage level of the Q node or the voltage level of QB based on multiple scan clock signals (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) or the voltage level of the first low voltage GVSS1, where i is a positive integer.

[0173] The strobe signal output circuit 514 may include first to eighth transistors T71 to T78 and boosting capacitors ( CS1 , CS2 , CS3 , CS4 ).

[0174] The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 can be connected to a clock signal line for transmitting a scan clock signal (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) and the second output node NO2 to the fifth output node NO5, respectively. Boosting capacitors (CS1, CS2, CS3, CS4) can be connected between the gate and source of the first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77, respectively.

[0175] The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 can respectively output the strobe signals (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) having a high voltage through the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5 in response to the voltage of the Q node based on the scan clock signal (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)). The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 can be turned on when the voltage of the Q node is at a high level and provide the scan clock signals (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) having a high voltage to the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5, respectively. Therefore, the strobe signals (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) having a high voltage can be output.

[0176] When the strobe signal (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) is output, the boost capacitors (CS1, CS2, CS3, CS4) can bootstrap or increase the voltage of the Q node in synchronization with the high-level scan clock signal (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) until it reaches a boosted voltage level higher than the first high voltage GVDD1. When the voltage of the Q node is bootstrapped, the scan clock signal ((SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) with a high voltage level can be output as the strobe signal (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) quickly and without distortion.

[0177] The second transistor T72, the fourth transistor T74, the sixth transistor T76, and the eighth transistor T78 can respectively output low-voltage strobe signals (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) through the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5 based on the first low voltage GVSS1 in response to the voltage of the QB node. The second transistor T72, the fourth transistor T74, the sixth transistor T76, and the eighth transistor T78 can be turned on when the voltage of the Q node is at a high level and provide the first low voltage GVSS1 to the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5, respectively. Therefore, the strobe signals (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) with low voltages can be output.

[0178] exist Figure 5 In the illustrated embodiment, three high voltages (GVDD1, GVDD2, GVDD3) having different levels from each other and three low voltages (GVSS1, GVSS2, GVSS3) having different levels from each other can be provided to each stage circuit. For example, the first high voltage GVDD1, the second high voltage GVDD2, and the third high voltage GVDD3 can be set to 20V, 16V, and 14V, respectively, and the first low voltage GVSS1, the second low voltage GVSS2, and the third low voltage GVSS3 can be set to -6V, -10V, and -12V, respectively. However, these numbers are only examples, and the levels of the high voltage and the low voltage can be set differently according to the embodiment.

[0179] Figure 6 is an example circuit diagram of a dummy stage circuit included in a gate driving circuit according to aspects of the present disclosure.

[0180] Figure 6 The virtual stage circuit shown is Figure 4 A circuit diagram of a previous dummy stage circuit DST1 is shown.

[0181] Reference Figure 6 In one embodiment, the previous dummy stage circuit DST1 may include a Q node, a QB node, and a QH node. In one embodiment, the previous dummy stage circuit DST1 may include a Q node controller 504, a Q node and a QH node stabilization circuit 506, an inverter 508, and a carry signal output circuit 512.

[0182] The Q node controller 504 may charge the Q node to a first high voltage (GVDD1) level in response to input of a start signal Vst for initialization of the RT sensing line, and discharge the Q node to a third low voltage GVSS3 in response to input of a subsequent stage carry signal C(k+2).

[0183] The Q-node controller 504 may include first to eighth transistors T21 to T28 .

[0184] The first transistor T21 and the second transistor T22 may be connected between a first high voltage line for transmitting the first high voltage GVDD1 and the Q node. The first transistor T21 and the second transistor T22 may be connected to each other in series.

[0185] The first transistor T21 and the second transistor T22 can charge the Q node to the first high voltage (GVDD1) level in response to the input of the previous stage carry signal C(k-2). The first transistor T21 can be turned on by the input of the previous stage carry signal C(k-2) and provide the first high voltage GVDD1 to the second connection node NC2. The second transistor T22 can be turned on by the input of the previous stage carry signal C(k-2) and electrically connect the second connection node NC2 to the Q node. Therefore, when the first transistor T21 and the second transistor T22 are turned on at the same time, the first high voltage GVDD1 can be provided to the Q node.

[0186] The fifth transistor T25 and the sixth transistor T26 may be connected to a third high voltage line for transmitting the third high voltage GVDD3 . The fifth transistor T25 and the sixth transistor T26 may provide the third high voltage GVDD3 to the second connection node NC2 in response to the third high voltage GVDD3 .

[0187] Since the fifth transistor T25 and the sixth transistor T26 can be turned on at the same time by the third high voltage GVDD3, the voltage difference between the gate voltage of the first transistor T21 and the voltage of the second connection node NC2 can be increased by enabling the third high voltage GVDD3 to be constantly supplied to the second connection node NC2. Therefore, when the previous stage carry signal C(k-2) having a low level is input to the gate of the first transistor T21 and the first transistor T21 is turned off, the first transistor T21 can be completely maintained in the off state due to the voltage difference between the gate voltage of the first transistor T21 and the voltage of the second connection node NC2. Therefore, current leakage of the first transistor T21 and the voltage drop of the Q node caused by the current leakage of the first transistor T21 can be prevented, which makes it possible to stably maintain the voltage of the Q node.

[0188] For example, when the threshold voltage of the first transistor T21 is negative (-), the gate-source voltage Vgs of the first transistor T21 can be maintained at a negative (-) polarity by the third high voltage GVDD3 supplied to its drain electrode. Therefore, the previous stage carry signal C(k-2) having a low level is input to the gate of the first transistor T21, thereby turning off the first transistor T21, and the first transistor T21 can be completely maintained in the off state and can prevent the occurrence of corresponding leakage current.

[0189] In one embodiment, the third high voltage GVDD3 may be set to a voltage level lower than the first high voltage GVDD1 .

[0190] The third transistor T23 and the fourth transistor T24 may be connected between the Q node and a third low voltage line for transmitting the third low voltage GVSS3 . The third transistor T23 and the fourth transistor T24 may be connected to each other in series.

[0191] The third transistor T23 and the fourth transistor T24 can discharge the Q node and the QH node to the third low voltage GVSS3 in response to the input of the subsequent stage carry signal C(k+2). The fourth transistor T24 can be turned on by the input of the subsequent stage carry signal C(k+2) and discharge the QH node to the third low voltage GVSS3. The third transistor T23 can be turned on by the input of the subsequent stage carry signal C(k+2) and electrically connect the Q node and the QH node. Therefore, when the third transistor T23 and the fourth transistor T24 are turned on at the same time, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3.

[0192] The seventh transistor T27 and the eighth transistor T28 may be connected between the first high voltage line for transmitting the first high voltage GVDD1 and the Q node and between the first high voltage line for transmitting the first high voltage GVDD1 and the QH node. The seventh transistor T27 and the eighth transistor T28 may be connected to each other in series.

[0193] The seventh transistor T27 and the eighth transistor T28 can provide a first high voltage GVDD1 to the QH node in response to the voltage of the Q node. The seventh transistor T27 can be turned on when the voltage of the Q node is at a high level and provide the first high voltage GVDD1 to the shared node of the seventh transistor T27 and the eighth transistor T28. The eighth transistor T28 can be turned on when the voltage of the Q node is at a high level and electrically connect the shared node to the QH node. Therefore, when the voltage of the Q node is at a high level, the seventh transistor T27 and the eighth transistor T28 can be turned on at the same time and provide the first high voltage GVDD1 to the QH node.

[0194] When the first high voltage GVDD1 is supplied to the QH node, the voltage difference between the gate of the third transistor T23 and the QH node increases. Therefore, the subsequent stage carry signal C(k+2) having a low level is input to the gate of the third transistor T23, thereby turning off the third transistor T23. Due to the voltage difference between the gate voltage of the third transistor T23 and the voltage of the QH node, the third transistor T23 can be completely maintained in the off state. Therefore, current leakage of the third transistor T23 and the voltage drop of the Q node caused by the current leakage of the third transistor T23 can be prevented, which makes it possible to stably maintain the voltage of the Q node.

[0195] The Q-node and QH-node stabilization circuit 506 may discharge the Q-node and the QH-node to a third low voltage ( GVSS3 ) level in response to the voltage of the QB node.

[0196] The Q node and QH node stabilization circuit 506 may include a first transistor T31 and a second transistor T32. The first transistor T31 and the second transistor T32 may be connected between the Q node and a third low voltage line for transmitting a third low voltage GVSS3. The first transistor T31 and the second transistor T32 may be connected in series with each other.

[0197] The first transistor T31 and the second transistor T32 can discharge the Q node and the QH node to a third low voltage GVSS3 in response to the voltage of the QB node. The second transistor T32 can be turned on when the voltage of the QB node is at a high level and provide the third low voltage GVSS3 to a shared node of the first transistor T31 and the second transistor T32. The first transistor T31 can be turned on when the voltage of the QB node is at a high level and electrically connect the Q node and the QH node. Therefore, when the first transistor T31 and the second transistor T32 are simultaneously turned on by the voltage of the QB node, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3.

[0198] The inverter 508 may change the voltage level of the QB node according to the voltage level of the Q node.

[0199] The inverter 508 may include first to fifth transistors T41 to T45 .

[0200] The second transistor T42 and the third transistor T43 may be connected between a second high voltage line for transmitting the second high voltage GVDD2 and a third connection node NC3. The second transistor T42 and the third transistor T43 may be connected to each other in series.

[0201] The second transistor T42 and the third transistor T43 can provide the second high voltage GVDD2 to the third connection node NC3 in response to the second high voltage GVDD2. The second transistor T42 can be turned on by the second high voltage GVDD2 and provide the second high voltage GVDD2 to the shared node of the second transistor T42 and the third transistor T43. The third transistor T43 can be turned on by the second high voltage GVDD2 and electrically connects the shared node of the second transistor T42 and the third transistor T43 to the third connection node NC3. Therefore, when the second transistor T42 and the third transistor T43 are simultaneously turned on by the second high voltage GVDD2, the third connection node NC3 can be charged to the second high voltage (GVDD2) level.

[0202] The fourth transistor T44 may be connected between the third connection node NC3 and a second low voltage line for transmitting the second low voltage GVSS2 .

[0203] The fourth transistor T44 may provide the second low voltage GVSS2 to the third connection node NC3 in response to the voltage of the Q node. The fourth transistor T44 may be turned on when the voltage of the Q node is at a high level and discharge or reset the third connection node NC3 to the second low voltage GVSS2.

[0204] The first transistor T41 may be connected between a second high voltage line for transmitting the second high voltage GVDD2 and the QB node.

[0205] The first transistor T41 may provide the second high voltage GVDD2 to the QB node in response to the voltage of the third connection node NC3. When the voltage of the third connection node NC3 is at a high level, the first transistor T41 may be turned on and charge the QB node to the second high voltage (GVDD2).

[0206] The fifth transistor T45 may be connected between the QB node and a third low voltage line for transmitting a third low voltage GVSS3 .

[0207] The fifth transistor T45 may provide the third low voltage GVSS3 to the QB node in response to the voltage of the Q node. The fifth transistor T45 may be turned on when the Q node voltage is at a high level and discharge or reset the QB node to the third low voltage GVSS3 level.

[0208] The carry signal output circuit 512 may output the carry signal C(k) based on the voltage level of the carry clock signal CRCLK(k) according to the voltage level of the Q node or based on the third low voltage ( GVSS3 ) level according to the voltage level of the QB node.

[0209] The carry signal output circuit 512 may include a first transistor T61 , a second transistor T62 , and a boosting capacitor CC.

[0210] The first transistor T61 may be connected between a clock signal line for transmitting the carry clock signal CRCLK(k) and the first output node NO1. The boosting capacitor CC may be connected between a gate and a source of the first transistor T61.

[0211] The first transistor T61 can output a carry signal C(k) having a high voltage through the first output node NO1 based on the carry clock signal CRCLK(k) in response to the voltage of the Q node. The first transistor T61 can be turned on when the voltage of the Q node is at a high level and provide the carry clock signal CRCLK(k) having a high voltage to the first output node NO1. Therefore, the carry signal C(k) having a high voltage can be output.

[0212] When the carry signal C(k) is output, the boost capacitor CC can bootstrap the voltage of the Q node in synchronization with the carry clock signal CRCLK(k) having a high voltage level until it reaches a boosted voltage level greater than the first high voltage GVDD1. When the voltage of the Q node is bootstrapped, the carry clock signal CRCLK(k) having a high voltage level can be output as the carry signal C(k) quickly and without distortion.

[0213] The second transistor T62 may be connected between the first output node NO1 and a third low voltage line for transmitting a third low voltage GVSS3 .

[0214] The second transistor T62 can output a carry signal C(k) having a low voltage based on the third low voltage GVSS3 through the first output node NO1 in response to the voltage of the QB node. The second transistor T62 can be turned on when the voltage of the QB node is at a high level and provide the third low voltage GVSS3 to the first output node NO1. Therefore, a carry signal C(k) having a low voltage can be output.

[0215] Figure 7 is a circuit diagram of another dummy stage circuit included in a gate driving circuit according to aspects of the present disclosure.

[0216] Figure 7 The virtual stage circuit shown is Figure 4 A circuit diagram of the previous dummy stage circuit DST2 is shown.

[0217] Reference Figure 7In one embodiment, the previous dummy stage circuit DST2 may include a Q node, a QB node, and a QH node. In one embodiment, the previous dummy stage circuit DST2 may include a Q node controller 504, a Q node and QH node stabilization circuit 506, an inverter 508, a carry signal output circuit 512, and an FB TFT circuit 516.

[0218] The Q node controller 504, the Q node and QH node stabilization circuit 506, the inverter 508 and the carry signal output circuit 512 are connected to the Figure 6 The Q node controller 504, the Q node and QH node stabilization circuit 506, the inverter 508 and the carry signal output circuit 512 in the circuit diagram of FIG are the same. In view of this, the discussion of these elements is omitted and the same Figure 6 The discussion related to the circuit diagram is cited in Figure 7 of this implementation method.

[0219] In one embodiment, the FB TFT circuit 516 of the previous dummy stage circuit DST2 is designed to have the same circuit structure as the T3 TFT (e.g., the first transistor T31 and the second transistor T32), wherein the same gate-source voltage Vgs as the T3 TFT is applied. In this case, when the PBTS (positive bias temperature stress, the threshold voltage Vth of the T3 TFT) degradation of the T3 TFT progresses, the threshold voltage Vth of the FB TFT circuit is also positively shifted, and the flowing current is reduced. The PGVDD voltage generation block (not shown) can sense this reduced current of the FB TFT circuit and increase the corresponding PGVDD voltage by the threshold voltage Vth.

[0220] The FB TFT circuit 516 may include first to sixth transistors T81 to T86. The first and second transistors T81 and T82 may be connected between a feedback voltage line for transmitting the feedback voltage GVDD_FB and a third low voltage line for transmitting the third low voltage GVSS3. The first and second transistors T81 and T82 may discharge the QH node to the third low voltage GVSS3 in response to the voltage at the QB node. The second transistor T82 may be turned on when the voltage at the QB node is at a high level and provide the third low voltage GVSS3 to a shared node between the first and second transistors T81 and T82. The first transistor T81 may be turned on when the voltage at the QB node is at a high level and provide the feedback voltage GVDD_FB to the QH node. Therefore, when the first and second transistors T31 and T32 are simultaneously turned on by the voltage at the QB node, the Q node and the QH node may be discharged or reset to the third low voltage GVSS3. The third transistor T83 and the fourth transistor T84 as well as the fifth transistor T85 and the sixth transistor T86 have the same functions and operations as the first transistor T81 and the second transistor T82, and thus the discussion of these elements will be omitted for ease of description. In addition, the number of transistors included in the FB TFT circuit 516 is not limited to Figure 7 For example, the FB TFT circuit 516 may include one or more pairs of two transistors connected in series between the feedback voltage line and a third low voltage line for transmitting the third low voltage, and the gate electrodes of each of the one or more pairs of two transistors may be commonly connected to the QB node, and the connection node between the first transistor and the second transistor may be commonly connected to the QH node.

[0221] Figure 8 is the first carry signal line connection diagram of the stage circuit described in this article, and Figure 9 This is the second carry signal line connection diagram of the stage circuit described in this article.

[0222] Reference Figure 8In one embodiment, the carry signal lines between the stage circuits may be connected such that the carry signal line is connected from the first previous dummy stage circuit DST1 among the previous dummy stage circuits (DST1, DST2) to the first stage circuit ST(1), and the carry signal line is connected from the second previous dummy stage circuit DST2 among the previous dummy stage circuits (DST1, DST2) to the second stage circuit ST(2). The stage circuits in the first carry signal line connection diagram may be implemented such that the start signal Vst is simultaneously input to the first previous dummy stage circuit DST1 and the second previous dummy stage circuit DST2 for RT sensing line initialization, thereby activating the first previous dummy stage circuit DST1 and the second previous dummy stage circuit DST2, generating a previous stage carry signal C, and outputting the generated previous stage carry signal C to the first stage circuit ST(1) and the second stage circuit ST(2), respectively.

[0223] However, when based on Figure 8 When the variable refresh rate (VRR) driving is performed in the first carry signal line connection diagram of the stage circuit, the first previous dummy stage circuit DST1 and the second previous dummy stage circuit DST2 may be activated, and the FB TFT circuit 156 of the second previous dummy stage circuit DST2 is turned off and the corresponding PGVDD voltage increases, which causes display artifacts such as horizontal lines due to the voltage difference.

[0224] To solve Figure 8 The first carry signal line connection diagram of the stage circuit occurs in the VRR drive of this horizontal line, developed Figure 9 The second carry signal line connection diagram of the stage circuit is shown.

[0225] In VRR driver, if Figure 9 The second carry signal line connection diagram shown in the figure is used to drive the stage circuit, which can solve the occurrence of display artifacts such as horizontal lines. Figure 6 、 Figure 7 and Figure 9 Give relevant discussion:

[0226] ⅰ. The start signal Vst is input to the first previous dummy stage circuit DST1 for RT sensing line initialization; ⅱ. Then, the first previous dummy stage circuit DST1 can be activated to generate a previous stage carry signal C, and output the generated previous stage carry signal C to the second previous dummy stage circuit DST2 and the first stage circuit ST(1); and ⅲ. Thereafter, when the previous stage carry signal C from the first previous dummy stage circuit DST1 is input, the second previous dummy stage circuit DST2 can be activated to generate a previous stage carry signal C, and output the generated previous stage carry signal C to the second stage circuit ST(2).

[0227] In this way, in the second carry signal line connection diagram, since the start signal Vst can be input only to the first previous dummy stage circuit DST1, and the previous stage carry signal C from the first previous dummy stage circuit DST1 is input to the second previous dummy stage circuit DST2, the Q node of the second previous dummy stage circuit DST2 is not activated, and therefore, the QB node can be maintained in the on state, and the FB TFT circuit 156 can operate normally.

[0228] When the FB TFT circuit 156 of the second previous dummy stage circuit DST2 operates normally, since the corresponding PGVDD voltage does not change, no voltage difference is caused, and the occurrence of a horizontal line caused by the first carry signal line connection pattern of the stage circuit can be prevented.

[0229] Figure 10 is based on Figure 8 The first connection diagram is a driving timing diagram of the VRR driving stage circuit. Figure 10 , it can be seen that the FB TFT circuit 156 of the second previous dummy stage circuit DST2 is turned off, and the corresponding increase in the PGVDD voltage is maintained until the next frame starts.

[0230] Figure 11 is based on Figure 9 The second connection diagram is a driving timing diagram of the VRR driving stage circuit. Figure 9 , it can be seen that the FB TFT circuit 156 of the second previous dummy stage circuit DST2 is turned on, and the corresponding PGVDD voltage is normally maintained until the next frame starts.

[0231] As mentioned above, refer to Figure 6 、 Figure 7 、 Figure 10 and Figure 11 , when performing VRR driving, since the stage circuit according to the embodiment of the present disclosure is driven according to the second connection diagram of the carry signal line, display artifacts such as horizontal lines can be resolved and image display quality can be improved.

[0232] Figure 12 The present invention illustrates a gate drive circuit according to various aspects of the present disclosure. Figure 5 The waveforms of the input and output signals when the stage circuit outputs the selection signal for image display.

[0233] In the period (from P1 to P2), when the previous stage carry signal C(k-2) having a high level is input, the first transistor T21 and the second transistor T22 of the Q node controller 504 may be turned on. Therefore, the Q node may be charged to the first high voltage (GVDD1) level. Since the first transistor T51 of the QB node stabilization circuit 510 is turned on by the previous stage carry signal C(k-2) having a high level, the QB node may be discharged to the third low voltage GVSS3.

[0234] During the period (from P2 to P3), when the scan clock signal SCCLK(i) having a high level is input, the voltage of the Q node is boosted by the boost capacitor CS1 to a first boost voltage (BL1) level higher than the first high voltage GVDD1. Therefore, during the period (from P2 to P3), the strobe signal SCOUT(i) can be output from the second output node NO2.

[0235] In the period (from P3 to P4), when the scan clock signal SCCLK(i+1) having a high level is input together with the scan clock signal SCCLK(i) having a high level, the voltage of the Q node can be bootstrapped by the boosting capacitors (CS1, CS2) to a second boosted voltage (BL2) level higher than the first boosted voltage (BL1) level. Therefore, in the period (from P3 to P4), the strobe signal SCOUT(i+1) can be output from the third output node NO3.

[0236] During the period (from P4 to P5), when the high-level scan clock signal SCCLK(i+2) is input together with the high-level scan clock signal SCCLK(i+1), the voltage of the Q node can be maintained at a second boosted voltage (BL2) level higher than the first boosted voltage (BL1) level through the boost capacitors (CS2, CS3). Therefore, during the period (from P4 to P5), the strobe signal SCOUT(i+2) can be output from the fourth output node NO4.

[0237] During the period (from P5 to P6), when the high-level scan clock signal SCCLK(i+3) is input together with the high-level scan clock signal SCCLK(i+2), the voltage of the Q node can be maintained at the second boosted voltage (BL2) level higher than the first boosted voltage (BL1) level through the boost capacitors (CS3, CS4). Therefore, during the period (from P5 to P6), the strobe signal SCOUT(i+3) can be output from the fifth output node NO5.

[0238] In the period (from P6 to P7 ), since only the scan clock signal SCCLK(i+3) having a high level is input, the voltage of the Q node may drop to the level of the first boosting voltage BL1 through the boosting capacitor CS4 .

[0239] Furthermore, in the period (from P6 to P7), when the carry clock signal CRCLK(k) having a high level is input, a carry signal C(k) may be output from the first output node NO1 through the first transistor T61 turned on by the voltage charged in the Q node.

[0240] In the period (from P7 to P8), since the scan clock signal is not input, the voltage of the Q node can be charged to the first high voltage (GVDD1) level again. In addition, in the period (from P7 to P8), when the subsequent stage carry signal C(k+2) with a high level is input, the third transistor T23 and the fourth transistor T24 of the Q node controller 504 can be turned on. Therefore, at the time point of P8, the Q node can be discharged to the third low voltage GVSS3. When the Q node is discharged to the third low voltage GVSS3, since the fourth transistor T44 included in the inverter 508 is turned off and the second high voltage GVDD2 is applied to the gate of the first transistor T41, the first transistor T41 can be turned on. When the first transistor T41 is turned on, the QB node can be charged to the second high voltage (GVDD2) level.

[0241] Figure 4 and Figure 5 The stage circuits of the gate drive circuit 13 shown do not share the QB node. Therefore, the QB node can be turned on or off per frame. Therefore, the transistors (T31, T32, T62, T72, T74, T76, T78) connected to the QB node can be turned on or off per frame.

[0242] In this way, if the transistors (T31, T32, T62, T72, T74, T76, T78) connected to the QB node are turned on or off every frame, the transistors (T31, T32, T62, T72, T74, T76, T78) may be rapidly degraded due to the voltage stress applied to the transistors (T31, T32, T62, T72, T74, T76, and T78). The degradation of the transistors due to the voltage stress applied to the transistors may cause the threshold voltage of the transistors to increase, thereby causing performance degradation and shortening the life of the display device 1.

[0243] Therefore, in order to reduce the degradation rate of the transistors (T31, T32, T62, T72, T74, T76, T78) connected to the QB node, the gate driving circuit 13 according to aspects of the present disclosure can adjust the amplitude of the voltage charged to the QB node, the second high voltage GVDD2.

[0244] Figure 13 : is a graph showing a change in the magnitude of the second high voltage according to the driving time of the gate driving circuit in the display device according to aspects of the present disclosure. Figure 13 In FIG. 1 , the horizontal axis represents the driving time of the gate driving circuit 13, and the vertical axis represents Figure 13 The magnitude of the second high voltage GVDD2 is shown.

[0245] In one embodiment, the Figure 13 The magnitude of the second high voltage GVDD2 of the QB node shown can be adjusted according to the driving time of the gate driving circuit 13 .

[0246] For example, Figure 13 As shown in FIG. 1 , as the driving time of the gate driving circuit 13 increases, the amplitude of the second high voltage GVDD2 may increase. Figure 13 As shown, whenever the driving time of the gate driver circuit 13 increases to AT1, AT2, AT3, AT4 or AT5, the amplitude of the second high voltage GVDD2 can be gradually increased to GV1, GV2, GV3, GV4 and GV5. At this time, the amplitude (GV1, GV2, GV3, GV4, GV5) of the second high voltage GVDD2 of each stage can be greater than or equal to the threshold voltage of the transistor (T31, T32, T62, T72, T74, T76, T78) connected to the QB node at each driving time (AT1, AT2, AT3, AT4, AT5), and can be determined through experiments.

[0247] Figure 13 The embodiment shows that the amplitude of the second high voltage GVDD2 gradually increases as the driving time of the gate driving circuit 13 increases. However, in another embodiment, the amplitude of the second high voltage GVDD2 may increase linearly or nonlinearly in proportion to the driving time of the gate driving circuit 13.

[0248] also, Figure 13 The illustrated AT1, AT2, AT3, AT4, AT5, GV1, GV2, GV3, GV4, and GV5 are values ​​that may be set differently depending on the implementation and may be determined through experiments.

[0249] in addition, Figure 13The intervals between AT1, AT2, AT3, AT4, and AT5 shown in FIG. 1 and GV1, GV2, GV3, GV4, and GV5 may be the same or different. For example, the difference between AT2 and AT1 may be the same as or different from the difference between AT5 and AT4. As another example, the difference between GV3 and GV2 may be the same as or different from the difference between GV5 and GV4.

[0250] like Figure 13 As shown, by increasing the magnitude of the second high voltage GVDD2 in proportion to the driving time of the gate driving circuit 13, the gate driving circuit 13 can be normally driven and the voltage stress applied to the transistors (T31, T32, T62, T72, T74, T76, and T78) connected to the QB node can be minimized. Therefore, the life of the display device 1 can be extended.

[0251] Figure 14 is a graph showing changes in threshold voltage magnitudes of transistors according to driving time of a gate driving circuit in a display device according to aspects of the present disclosure.

[0252] exist Figure 14 , data 1204 indicates that when the second high voltage GVDD2 of the same magnitude is always supplied to Figure 4 and Figure 5 When the QB node in the gate driving circuit 13 is turned on, the threshold voltage magnitude of the transistor connected to the QB node changes.

[0253] In addition, data 1206 indicates that when Figure 4 and Figure 5 In the gate driving circuit 13 shown, when the magnitude of the second high voltage GVDD2 increases according to the driving time of the gate driving circuit 13, the magnitude of the threshold voltage of the transistor connected to the QB node changes.

[0254] Figure 14 The data 1204 shows that when the second high voltage GVDD2 having the same amplitude is always supplied to Figure 4 and Figure 5 When the QB node in the driving circuit 13 is turned on, the threshold voltage of the transistor connected to the QB node increases sharply. Therefore, the transistor connected to the QB node deteriorates rapidly, and the life of the display device 1 is shortened.

[0255] However, from Figure 14 From the data 1206, it can be seen that when Figure 4 and Figure 5When the gate driving circuit 13 shown adjusts the amplitude of the second high voltage GVDD2 according to the driving time of the gate driving circuit 13, the rate of increase of the threshold voltage amplitude of the transistor connected to the QB node is significantly reduced compared to the case where the amplitude of the second high voltage GVDD2 always has the same amplitude. Therefore, the life of the display device 1 can be further extended.

[0256] The above description has been presented to enable any person skilled in the art to make and use the present disclosure, and has been provided in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Although exemplary embodiments have been described for illustrative purposes, those skilled in the art will recognize that various modifications and applications can be made without departing from the essential features of the present disclosure. For example, various modifications can be made to the specific components of the exemplary embodiments. The above description and accompanying drawings provide examples of the technical ideas of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown, but is to be consistent with the widest scope consistent with the claims. The scope of protection of the present disclosure should be interpreted according to the claims, and all technical ideas within the scope of the claims should be interpreted as being included within the scope of the present disclosure.

[0257] CROSS-REFERENCE TO RELATED APPLICATIONS

[0258] This application claims the benefit of priority from Korean Patent Application No. 10-2021-0194274 filed on December 31, 2021, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A gate drive circuit, comprising: a first dummy stage circuit and a second dummy stage circuit, each of the first dummy stage circuit and the second dummy stage circuit being capable of providing a carry signal and each including a Q node, a QH node, and a QB node; as well as a plurality of stage circuits, each of the plurality of stage circuits being capable of providing a gate signal to each gate line and each including the Q node, the QH node, and the QB node; Wherein, each stage circuit comprises: a line selector configured to charge the M node based on a previous stage carry signal in response to an input of a line sensing ready signal, and charge the Q node to a first high voltage level in response to an input of a reset signal or discharge the Q node to a third low voltage level in response to an input of a panel turn-on signal; a Q-node controller configured to charge the Q-node to the first high voltage level in response to an input of the previous stage carry signal and discharge the Q-node to the third low voltage level in response to an input of a subsequent stage carry signal; a Q-node and QH-node stabilization circuit configured to discharge the Q-node and the QH-node to the third low voltage level when the QB-node is charged to the second high voltage level; an inverter configured to change a voltage level of the QB node according to a voltage level of the Q node; a QB node stabilizing circuit configured to discharge the QB node to the third low voltage level in response to an input of the previous stage carry signal, an input of the reset signal, and a charge voltage of the M node; a carry signal output circuit configured to output a carry signal based on a voltage level of a carry clock signal according to a voltage level of the Q node or based on the third low voltage level according to a voltage level of the QB node; and a strobe signal output circuit configured to output first to j-th strobe signals based on the first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node, wherein the second dummy stage circuit includes an FB TFT circuit, wherein the FB TFT circuit includes one or more pairs of first transistors and second transistors connected in series between a feedback voltage line for sending a feedback voltage and a third low voltage line for sending the third low voltage level, and wherein the gate electrodes of each of the one or more pairs of first transistors and second transistors are commonly connected to the QB node of the second dummy stage circuit, and the connection node between the first transistor and the second transistor is commonly connected to the QH node of the second dummy stage circuit.

2. The gate drive circuit according to claim 1, wherein: Each of the first dummy stage circuit and the second dummy stage circuit includes: a Q-node controller configured to charge the Q-node to the first high voltage level in response to an input of a start signal, and discharge the Q-node to the third low voltage level in response to an input of a subsequent stage carry signal; a Q-node and QH-node stabilization circuit configured to discharge the Q-node and the QH-node to the third low voltage level when the QB-node is charged to the second high voltage level; an inverter configured to change a voltage level of the QB node according to a voltage level of the Q node; and A carry signal output circuit is configured to output a carry signal based on a voltage level of a carry clock signal according to a voltage level of the Q node or based on a voltage level of the QB node and the third low voltage level.

3. The gate drive circuit according to claim 1, wherein: The first high voltage level and the second high voltage level are different from each other.

4. The gate drive circuit according to claim 1, wherein: The line selector includes a first transistor and a second transistor connected between the M node and a previous stage carry signal line for providing the previous stage carry signal, and a third transistor connected between a connection node between the first transistor and the second transistor and a first high voltage line for providing the first high voltage level, and The first transistor and the second transistor are controlled by the line sensing ready signal, and the third transistor is controlled by the voltage of the M node.

5. The gate driving circuit according to claim 1, wherein: When the voltage level of the Q node is at a high voltage level, the strobe signal output circuit sequentially outputs the first to j-th strobe signals based on the first to j-th scan clock signals.

6. The gate driving circuit according to claim 1, wherein: The strobe signal output circuit comprises: a pull-up transistor that is turned on when the voltage level of the Q node is at a high voltage level and is capable of providing the first to j-th scan clock signals to an output node; a pull-down transistor that is turned on when the voltage level of the QB node is at a high voltage level and is capable of providing the first low voltage to the output node; and A boost capacitor is connected between the gate and source of the pull-up transistor.

7. The gate driving circuit according to claim 6, wherein: When the voltage level of the QB node is charged to the second high voltage level, the pull-down transistor is turned on.

8. The gate driving circuit according to claim 1, wherein: The Q-node and QH-node stabilization circuit includes a first transistor and a second transistor that are turned on when the QB node is charged to the second high voltage level.

9. The gate driving circuit according to claim 1, wherein: The magnitude of the second high voltage level is adjusted according to a driving time of the gate driving circuit.

10. The gate driving circuit according to claim 1, wherein: The magnitude of the second high voltage level increases as the driving time of the gate driving circuit increases.

11. The gate driving circuit according to claim 2, wherein: The second dummy stage circuit further includes the FBTFT circuit to prevent TFT degradation.

12. The gate driving circuit according to claim 11, wherein: A previous stage carry signal line of the first dummy stage circuit is connected to the second dummy stage circuit and a first stage circuit among the plurality of stage circuits, and a previous stage carry signal line of the second dummy stage circuit is connected to a second stage circuit among the plurality of stage circuits.

13. A display device, comprising: a display panel including sub-pixels formed in intersection areas of gate lines and data lines; The gate driving circuit according to any one of claims 1 to 12, wherein the gate driving circuit is configured to provide a scan signal to each of the gate lines; a data driving circuit, the data driving circuit being configured to provide a data voltage to each of the data lines; as well as A timing controller is used to control the driving of the gate driving circuit and the data driving circuit.

14. A gate drive circuit, comprising: a first dummy stage circuit and a second dummy stage circuit, each of the first dummy stage circuit and the second dummy stage circuit being capable of providing a carry signal and each including a Q node, a QH node, and a QB node; as well as a plurality of stage circuits, each of the plurality of stage circuits being capable of providing a gate signal to each gate line and each including the Q node, the QH node, and the QB node; Wherein, the second dummy stage circuit includes an FB TFT circuit to prevent TFT degradation, wherein the previous stage carry signal line of the first dummy stage circuit is connected to the second dummy stage circuit and the first stage circuit among the plurality of stage circuits, and the previous stage carry signal line of the second dummy stage circuit is connected to the second stage circuit among the plurality of stage circuits, and wherein the FB TFT circuit includes one or more pairs of first and second transistors connected in series between a feedback voltage line for transmitting a feedback voltage and a third low voltage line for transmitting a third low voltage, and wherein the gate electrodes of each of the one or more pairs of first and second transistors are commonly connected to the QB node of the second dummy stage circuit, and the connection node between the first transistor and the second transistor is commonly connected to the QH node of the second dummy stage circuit.

15. A display device, comprising: a display panel including sub-pixels formed in intersection areas of gate lines and data lines; The gate driving circuit according to claim 14, wherein the gate driving circuit is configured to provide a scan signal to each of the gate lines; a data driving circuit, the data driving circuit being configured to provide a data voltage to each of the data lines; as well as A timing controller is used to control the driving of the gate driving circuit and the data driving circuit.

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