Layout of data pads on a semiconductor die

Abstract

This application relates to the layout of data pads on semiconductor dies. Layouts of data pads and dummy data pads are disclosed. A die can include a number of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge. The die can further include a first number of data pads differentially electrically coupled to the number of circuits and arranged near the first edge, and a first number of dummy data pads not electrically coupled to the number of circuits, arranged alternatingly with the first number of data pads, and near the first edge. The die can further include a second number of data pads arranged near the third edge, and a second number of dummy data pads arranged alternatingly with the second number of data pads, and near the third edge. Associated devices, systems, and methods are also disclosed.

Description

[0001] Priority requirements

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 646,565, filed on December 30, 2021, entitled “Layouts of Data Pads on a Semiconductor Die,” the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to the layout of semiconductor dies, and more specifically, to the layout of data pads on semiconductor dies. More specifically, various embodiments relate to the layout of data pads, dummy data pads, and common data pads on dies to allow stacking of multiple dies. Additionally, embodiments include related methods, apparatus, and systems. Background Technology

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low-power double data rate memory (LPDDR), phase-change memory (PCM), and flash memory.

[0005] Some memory devices contain two or more dies stacked on top of each other. The memory device can provide independent communication with each die. Summary of the Invention

[0006] Various embodiments may include a die comprising: a plurality of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite to the first edge, and a fourth edge opposite to the second edge. The die may also include a first number of data pads electrically coupled to the plurality of circuits in different locations. The first number of data pads may be disposed near the first edge. The die may also include a first number of dummy data pads not electrically coupled to the plurality of circuits, arranged alternately with the first number of data pads near the first edge, wherein a first data pad of the first number of data pads is disposed near the fourth edge, and a first dummy data pad of the first number of dummy data pads is disposed near the second edge. The die may also include a second number of data pads electrically coupled to the plurality of circuits in different locations. The second number of data pads may be disposed near the third edge. The die may further include a second number of dummy data pads, which are not electrically coupled to the plurality of circuits, and are arranged alternately with the second number of data pads near the third edge, wherein a second data pad of the second number of data pads is near the fourth edge, and a second dummy data pad of the second number of dummy data pads is near the second edge.

[0007] Various embodiments may include an apparatus comprising a die including a bottom die and a plurality of dies disposed above the bottom die. Each of the dies may be substantially identical to each of the other dies. Each of the plurality of dies may be rotated approximately 180° relative to a corresponding die directly below the bottom die about an axis orthogonal to the bottom die. Each of the dies may include a plurality of circuits, a plurality of data pads electrically coupled to the plurality of circuits at different grounds, and a plurality of dummy data pads not electrically coupled to the plurality of circuits. The plurality of dummy data pads may be arranged relative to the plurality of data pads such that each of the plurality of dummy data pads of each of the plurality of dies is aligned with a corresponding data pad of the plurality of data pads.

[0008] Various embodiments may include an apparatus comprising a die comprising a bottom die and a plurality of dies disposed above the bottom die. Each of the dies may be substantially identical to each of the other dies. Each of the plurality of dies may be rotated approximately 90° relative to a corresponding die directly below the bottom die about an axis orthogonal to the bottom die. Each of the dies may include a plurality of circuits, a plurality of data pads electrically coupled to the plurality of circuits at different grounds, and a plurality of dummy data pads not electrically coupled to the plurality of circuits. The plurality of dummy data pads may be arranged relative to the plurality of data pads such that each of the plurality of dummy data pads of each of the plurality of dies is aligned with a corresponding data pad of the plurality of data pads.

[0009] Various embodiments may include a die comprising: a plurality of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite to the first edge, and a fourth edge opposite to the second edge. The die may also include a plurality of data pads electrically coupled to the plurality of circuits. The plurality of data pads may be disposed near the first edge. The die may further include: a first plurality of dummy data pads not electrically coupled to the plurality of circuits, disposed near the second edge; a second plurality of dummy data pads not electrically coupled to the plurality of circuits, disposed near the third edge; and a third plurality of dummy data pads not electrically coupled to the plurality of circuits, disposed near the fourth edge. In such embodiments, the plurality of data pads may include a first data pad spaced a first distance from the first edge and a second distance from the fourth edge; the first plurality of dummy data pads may include a first dummy data pad that is substantially spaced a first distance from the second edge and substantially spaced a second distance from the first edge; the second plurality of dummy data pads may include a second dummy data pad that is substantially spaced a first distance from the third edge and substantially spaced a second distance from the second edge; and the third plurality of dummy data pads may include a third dummy data pad that is substantially spaced a first distance from the fourth edge and substantially spaced a second distance from the third edge.

[0010] Various embodiments may include a method comprising: stacking a plurality of dies such that a data pad of one of the dies is aligned with dummy data pads of dies above and below that one of the dies. Each of the dies may be substantially identical to each of the other dies. The method may further include: electrically coupling some of the data pads of the dies to the dummy data pads of the others. Such embodiments may also include rotating all dies except the bottom die substantially 90° or 180° relative to the die below them before stacking the dies. Attached Figure Description

[0011] Although this disclosure is summarized by means of claims that precisely point out and clearly assert particular embodiments, various features and advantages of embodiments within the scope of this disclosure may be more readily apparent from the following description when read in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a functional block diagram of an example memory device according to at least one embodiment of the present disclosure.

[0013] Figure 2A This is a functional block diagram illustrating an instance layout of a bare die according to at least one embodiment of the present disclosure.

[0014] Figure 2B This is an illustration based on at least one embodiment of the present disclosure. Figure 2A Functional block diagram of the instance layout of the padding instance of the bare die's DW area.

[0015] Figure 2C This is a functional block diagram illustrating an instance layout of an instance data pad, a dummy data pad, and a common data pad according to at least one embodiment of the present disclosure.

[0016] Figure 3 This is a functional block diagram illustrating an example of die stacking according to at least one embodiment of the present disclosure.

[0017] Figure 4 This is a functional block diagram illustrating another instance layout of an example data pad, a dummy data pad, and a common data pad according to at least one embodiment of the present disclosure.

[0018] Figure 5 This is a functional block diagram illustrating another instance of die stacking according to at least one embodiment of the present disclosure.

[0019] Figure 6 Example methods according to at least one embodiment of the present disclosure are shown.

[0020] Figure 7This is a simplified block diagram illustrating an example memory system according to at least one embodiment of the present disclosure.

[0021] Figure 8 This is a simplified block diagram illustrating an example electronic system according to at least one embodiment of the present disclosure. Detailed Implementation

[0022] Some devices and / or systems, such as memory devices and / or memory systems, may include two or more stacked dies (also commonly referred to as "dies"). The device may provide one or more independent communication channels for each die. For example, a memory device may include two or more dies, each having one or more memory arrays. To enable independent use of each memory array (e.g., to enable each memory array to store and retrieve data independently of other memory arrays), the memory device may include one or more independent data channels for each memory array. Data channels allow data to be written to and read from the memory arrays. Data channels may traverse interlayer connections, data pads, and dummy data pads, etc. In this disclosure, the terms "data pad" and "dummy data pad" each refer to electrical connection nodes present on both the front and back sides of the die. Data pads and dummy data pads may include upper metal layer pads, silicon body side pads, and through-silicon vias.

[0023] Some embodiments of this disclosure include a layout (e.g., arrangement) of data pads and dummy data pads on a die that allows stacking substantially identical copies of the dies while providing independent data channels for memory arrays on the die. For example, a first die may include a first data pad located at its upper left corner and a first dummy data pad located at its lower right corner. The first data pad may be electrically coupled to a first circuitry of the first die, while the first dummy data pad may not be electrically coupled to the first circuitry (in some embodiments, the first dummy data pad may be electrically isolated). A second die, being a substantially identical copy of the first die, may include a second data pad located at its upper left corner and a second dummy data pad located at its lower right corner. The second data pad may be electrically coupled to a second circuitry of the second die, while the second dummy data pad may not be electrically coupled to the second circuitry (in some embodiments, the second dummy data pad may be electrically isolated). The second die can be rotated approximately 180° about an axis orthogonal to the first die and stacked on top of the first die, such that the second dummy data pad of the second die is above the first data pad of the first die, and the second data pad of the second die is above the first dummy data pad of the first die. A first interlayer connection electrically couples a first input / output of the die stack to the second dummy data pad of the second die and the first data pad of the first die. A second interlayer connection electrically couples a second input / output of the die stack to the first dummy data pad of the first die and the second data pad of the second die. Because the second dummy data pad is not electrically coupled to the second circuitry (and / or electrically isolated relative to the second die), the first input / output can provide a first independent data channel for a first circuitry of the first die (e.g., a first memory array). Furthermore, because the first dummy data pad is not electrically coupled to the first circuitry (and / or electrically isolated relative to the first die), the second input / output can provide a second independent data channel for a second circuitry of the second die (e.g., a second memory array).

[0024] The example layout described above can be extended to include several data pads and several corresponding dummy data pads, thereby allowing several dies to be stacked and providing an independent data channel for each memory array of each of the several dies. In some embodiments, interlayer connections can be electrically coupled to several data pads of the multiple dies. In such cases, addressing can be applied to access the circuitry (e.g., circuitry of the memory array) of the multiple dies individually. For example, four dies can be stacked in two different orientations (e.g., one orientation is rotated approximately 180° relative to the other). Each of the four dies may include two data pads and two dummy data pads. Four interlayer connections can be electrically coupled to the data pads of the four dies. For example, at the first die (e.g., the bottom die), interlayer connections can be electrically coupled to each of the two data pads and the two dummy data pads. At the second die above the first die, the interlayer connection of the data pads electrically coupled to the first die can be electrically coupled to the dummy data pads of the second die, and the interlayer connection of the dummy data pads electrically coupled to the first die can be electrically coupled to the data pads of the second die. At the third die above the second die, the interlayer connection of the data pads electrically coupled to the second die can be electrically coupled to the dummy data pads of the third die, and the interlayer connection of the dummy data pads electrically coupled to the second die can be electrically coupled to the data pads of the third die. At the fourth die above the third die, the interlayer connection of the data pads electrically coupled to the third die can be electrically coupled to the dummy data pads of the fourth die, and the interlayer connection of the dummy data pads electrically coupled to the third die can be electrically coupled to the data pads of the fourth die. For example, a controller and / or host device (e.g., an "access device") may be configured to provide input to and / or receive output from one or more memory arrays of one or more of the four dies via unique interlayer connections that are part of the data channel for each die. For instance, the access device may use a first interlayer connection electrically coupled to a data pad of the first die, a dummy data pad of the second die, a data pad of the third die, and a dummy data pad of the fourth die to provide input to and / or receive output from the memory array of the first die. Alternatively, the access device may use a second interlayer connection, also electrically coupled to a data pad of the first die, a dummy data pad of the second die, a data pad of the third die, and a dummy data pad of the fourth die, to provide input to and / or receive output from the memory array of the third die.

[0025] As another example, the first die may include a first data pad at its upper left corner, a first dummy data pad at its upper right corner, a second dummy data pad at its lower right corner, and a third dummy data pad at its lower left corner. In this example, three additional dies, each identical to the first die, may be stacked on top of the first die, each rotated approximately 90° relative to the die below. This allows for the stacking of four identical dies while providing four independent data channels via four interlayer connections. The instance layout suitable for the approximately 90° rotation can be extended to use more than one data pad and more than three dummy data pads per die, thereby allowing for the stacking of more than four dies while providing separate data channels in a manner similar to that described in the previous example.

[0026] Alternatively or alternatively, the device may use additional data channels to provide data to all dies in the die stack. In this disclosure, the data channel used to provide data to all dies in the stack is referred to as a "common data channel." Examples of common data channels include data channels for transmitting test mode signals and reset signals. Alternatively or alternatively, power and ground may be provided through the common data channel. Similarly, interlayer connections configured to transmit common data channels may be referred to herein as "common interlayer connections," and data pads intended to be electrically coupled to common interlayer connections may be referred to as "common data pads." The device may use several different categories of common data channels (e.g., for carrying different categories of signals), and the device die may include several corresponding categories of common data pads, for example, a first category of common data pads configured for a first category of common data channels, and a second common data pad configured for a second category of common data channels.

[0027] Some embodiments of this disclosure may include a layout of public data pads of various categories of the die, which allows substantially identical copies of the die to be rotated and stacked relative to each other. For example, the die may include a first public data pad of a first category located near the upper left corner of the die and a second public data pad of a second category located near the first public data pad. The die may further include a third public data pad of a first category located near the lower right corner of the die and a fourth public data pad of a second category located near the third public data pad. The position of the first public data pad relative to the upper left corner may be opposite to the position of the third public data pad relative to the lower right corner, and the position of the second public data pad relative to the upper left corner may be opposite to the position of the fourth public data pad relative to the lower right corner. The relative positions of the dies may be such that when substantially identical copies of the die are placed on top of each other, the first public data pad of the die will be aligned with the third public data pad of the die copy, and the second public data pad of the die will be aligned with the fourth public data pad of the die copy.

[0028] This type of layout (i.e., a layout that allows alignment of data pads and dummy data pads and / or common data pad alignment for each category) allows interlayer connections to be straight (e.g., vertically through the stack) and without any lateral connection portions. Straight interlayer connections without lateral connections can reduce parasitic capacitance compared to other die stacks that include lateral connections. Furthermore, reducing the number of lateral connections or eliminating lateral connections altogether can offer other advantages when compared to layouts that include them, including reduced complexity and / or manufacturing time and / or cost reduction.

[0029] Furthermore, this type of layout (i.e., a layout that allows for alignment of data pads and dummy data pads and / or common data pad alignment for each category) allows for the stacking of multiple instances of similar or identical dies. This can make the fabrication of die stacks simpler and / or more economical.

[0030] Data pads can be configured for specific data channels or common data channels, and are electrically coupled to the circuitry on the die accordingly. For example, a data pad electrically coupled to the input / output circuitry of a memory array can be a data pad for a data channel. Another data pad electrically coupled to the address input circuitry of the memory array can be a data pad for receiving address information.

[0031] On the other hand, a dummy data pad can be defined as a circuit that is not electrically coupled to the die. For example, in some embodiments, the dummy data pad of the die can be electrically isolated from everything on the die. Thus, interlayer connections can be electrically coupled to the dummy data pad of the first die and the data pad of the second die, while electrical communication on the first die will not interfere with signals carried to or from the data pad of the second die.

[0032] Although various embodiments are described herein with reference to memory devices, this disclosure is not limited thereto, and these embodiments are generally applicable to microelectronic systems and / or semiconductor devices that may or may not include memory devices. Embodiments of this disclosure will now be explained with reference to the accompanying drawings.

[0033] Figure 1 This is a functional block diagram illustrating an example memory device 100 according to at least one embodiment of the present disclosure. The memory device 100 may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM, such as DDR4 SDRAM, etc.), synchronous graphics random access memory (SGRAM), or three-dimensional (3D) DRAM. The memory device 100, which can be integrated on a semiconductor chip, may include a memory array 102.

[0034] exist Figure 1 In one embodiment, memory array 102 is shown as comprising eight memory groups BANK0-7. Memory array 102 in other embodiments may comprise more or fewer groups. Each memory group comprises several access lines (word lines WL), several data lines (bit lines BL and / or BL), and several memory cells MC arranged at the intersections of the word lines WL and the bit lines BL and / or BL. The selection of word lines WL may be performed by row decoder 104, and the selection of bit lines BL and / or BL may be performed by column decoder 106. Figure 1 In one embodiment, row decoder 104 may include a corresponding row decoder for each memory group BANK0-7, and column decoder 106 may include a corresponding column decoder for each memory group BANK0-7.

[0035] Bit lines BL and / BL are coupled to their respective sense amplifiers SAMP. Read data from bit line BL or / BL is amplified by the sense amplifier SAMP and transferred to the read / write amplifier 160 via the complementary local data line (LIOT / B), the transfer gate (TG), and the complementary main data line (MIOT / B). Conversely, write data output from the read / write amplifier 160 is transferred to the sense amplifier SAMP via the complementary main data line MIOT / B, the transfer gate TG, and the complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0036] The memory device 100 may typically be configured to receive various inputs (e.g., from an external controller or host) via various terminals, such as address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118. The memory device 100 may include additional terminals, such as power terminals 120 and 122.

[0037] During expected operation, one or more command signals COM received via command terminal 112 can be transmitted to command decoder 150 via command input circuitry 152. Command decoder 150 may include circuitry configured to generate various internal commands by decoding the one or more command signals COM. Examples of internal commands include the action command ACT and the read / write signal R / W.

[0038] Furthermore, one or more address signals ADD received via address terminal 110 can be transmitted to address decoder 130 via address input circuit 132. Address decoder 130 can be configured to supply row address XADD to row decoder 104 and column address YADD to column decoder 106. Although command input circuit 152 and address input circuit 132 are shown as separate circuits, in some embodiments, address signals and command signals can be received via a common circuit.

[0039] The action command ACT may include a pulse signal activated in response to a command signal COM (e.g., an action command) indicating row access. In response to the action signal ACT, the row decoder 104 specifying the group address can be activated. Therefore, the word line WL specified by the row address XADD can be selected and activated.

[0040] The read / write signal R / W may include a pulse signal activated in response to a command signal COM (e.g., a read command or a write command) indicating column access. In response to the read / write signal R / W, the column decoder 106 can be activated, and the bit line BL specified by the column address YADD can be selected.

[0041] In response to the action command ACT, the read signal, the row address XADD, and the column address YADD, data can be read from the memory cell MC specified by the row address XADD and the column address YADD. The read data can be output via the sense amplifier SAMP, the transfer gate TG, the read / write amplifier 160, the input / output circuit 162, and the data terminal 116. Furthermore, in response to the action command ACT, the write signal, the row address XADD, and the column address YADD, write data can be supplied to the memory array 102 via the data terminal 116, the input / output circuit 162, the read / write amplifier 160, the transfer gate TG, and the sense amplifier SAMP. The write data can be written to the memory cell MC specified by the row address XADD and the column address YADD.

[0042] Clock signals CK and / or CK can be received via clock terminal 114. CLK input circuit 170 can generate an internal clock signal ICLK based on clock signals CK and / or CK. The internal clock signal ICLK can be transmitted to various components of memory device 100, such as command decoder 150 and internal clock generator 172. Internal clock generator 172 can generate an internal clock signal LCLK, which can be transmitted to input / output circuit 162 (e.g., for controlling the operating timing of input / output circuit 162). Furthermore, data mask terminal 118 can receive one or more data mask signals DM. When a data mask signal DM is activated, overwriting the corresponding data can be disabled.

[0043] Figure 2A This is a functional block diagram illustrating an example layout 200a of a die 274 according to at least one embodiment of the present disclosure. Layout 200a includes array regions 264a and 264b, and through-silicon vias (TSVs) and peripheral circuitry regions 266 adjacent to the centerline 276 of the die 274.

[0044] Additionally, layout 200a includes markings for specific channel regions (“channel regions”) on the die, such as channel A (“ChA”), channel B (“ChB”), channel C (“ChC”), channel D (“ChD”), channel I (“ChI”), channel J (“ChJ”), channel K (“ChK”), and channel L (“ChL”). Including multiple channels on the die can increase the granularity of memory cell accessibility, etc. Including multiple channels improves random access operations. Each channel region may include a portion of array region 264a or array region 264b and a portion of TSV and peripheral circuitry region 266. As an example, in Figure 2A The diagram shows ChA region 278. The TSV and peripheral circuitry region 266 of the channel region can be used for memory in the memory array region serving the channel region. For example, each channel region may include: an "AW" region (or "AWord" region) which may contain data pads for receiving address / command data (or "command blocks"); and two "DW" regions (or "DWord" regions) which may contain data pads for providing and / or receiving data (or "data I / O blocks").

[0045] Figure 2B This is an illustration based on at least one embodiment of the present disclosure. Figure 2A A functional block diagram of an example layout 200b for the pads in an example DW region of a die. Specifically, layout 200b shows the arrangement of a power / ground pad 268 (which can be used to deliver power to the die), a data pad 270 (which can be used to provide data to and / or receive data from the die, and more specifically to and from the die's memory array), and a clock / command pad 272 (which can be used to provide clock signals and / or command signals to the die). Each pad in the die can be electrically coupled to an interlayer connection that can couple the pad to other dies and / or die inputs / outputs. For example, in some embodiments, each pad may be or may contain a TSV.

[0046] Figure 2C This is a functional block diagram illustrating an instance layout 200c of data pads, dummy data pads, and common data pads on an instance die 202 according to at least one embodiment of the present disclosure. Layout 200c allows multiple instances of die 202 to be rotated and stacked relative to each other. The stacking of instances of die 202 (e.g., where alternating dies are rotated substantially 180° relative to each other) allows alignment of data pads and dummy data pads, as well as alignment of various categories of common data pads, which enables linear interlayer connections, such as without lateral connection portions.

[0047] For descriptive purposes, Figure 2 shows a die 202 without a memory array but with eight data pads and sixteen common data pads. Specifically, the description of die 202 and its layout 200c is intended to describe the principles and patterns of data pads, dummy data pads, and common data pads applicable to any die containing any number of data pads, dummy data pads, and common data pads arranged at any location on the die. For example, Figure 2A The TSV and peripheral circuit area 266 as a whole can be arranged according to layout 200c. Furthermore, since the pattern and principle described with respect to layout 200c are applicable to the TSV and peripheral circuit area 266 as a whole, the pattern and principle described with respect to layout 200c can be applied in each DW area and / or AW area of ​​the TSV and peripheral circuit area 266.

[0048] Die 202 may include components arranged in one or more memory array regions (e.g., Figure 2A Array region 264a and Figure 2A The array region 264b; in Figure 2C One or more memory arrays (e.g., not shown in the image) in the memory array (e.g., Figure 1 The memory array 102; in Figure 2C (Not shown in the diagram). The data pads, dummy data pads, and common data pads of layout 200c can be arranged close to the centerline of the bare die 202, for example, close to... Figure 2A The center line is 276, with the array area on both sides, as shown. Figure 2A As shown, or in layout 200c, the data pads, dummy data pads, and common data pads may be arranged close to the edge of the die 202, with one or more memory array regions between them.

[0049] The data pads of die 202 can provide data channels for the memory array. For example, the individual data pads of die 202 can be electrically coupled to various circuits of die 202 (e.g., input / output circuits). For example, data pads can be used to electrically couple to circuits such as address input circuit 132, command input circuit 152, input / output circuit 162, and / or CLK input circuit 170. Alternatively, data pads can be used to electrically couple to terminals, such as… Figure 1 The address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118 are included. In some embodiments, the data channel containing the data pads can be serialized and / or serial-to-parallel converted, thereby reducing the number of data pads per die and / or relaxing the data rate.

[0050] The die 202 includes a first edge 228, a second edge 230, a third edge 232, and a fourth edge 234. For illustrative purposes, axes 244 and 246 are shown on the die 202. Axis 244 may be located between the first edge 228 and the third edge 232, for example, axis 244 may be spaced approximately the same distance from the first edge 228 and the third edge 232. Axis 246 may be located between the second edge 230 and the fourth edge 234, for example, axis 246 may be spaced approximately the same distance from the second edge 230 and the fourth edge 234.

[0051] The die 202 includes data pads 204a, 204b, 204c, and 204d (collectively referred to as "data pads 204") disposed near a first edge 228. In this disclosure, the term "near" can mean that something (e.g., a data pad, a dummy data pad, or a common data pad) is closer to a location than to the opposite side of said location. For example, data pad 204 being near the first edge 228 means that data pad 204 is closer to the first edge 228 than to the third edge 232. In other words, data pad 204 being near the first edge 228 can mean that data pad 204 is on the first edge 228 side of axis 244. As an example, data pads near the die centerline (e.g., near...) Figure 2A The data pad 204 (centerline 276) may also be near the first edge, because the data pad is closer to the first edge than to the third edge opposite the first edge. For descriptive purposes, the data pad 204 is... Figure 2C The diagram shows four data pads; in other embodiments, any number of data pads 204 may be included. The data pads 204 may be electrically coupled to one or more corresponding circuits of the die 202 in different ways. For example, each data pad 204 may be electrically coupled to a corresponding circuit to allow access devices to be electrically coupled (e.g., via interlayer connections) to the one or more corresponding circuits of the memory array.

[0052] The die 202 includes dummy data pads 208a, 208b, 208c, and 208d (collectively, “dummy data pads 208”) disposed near a first edge 228. The dummy data pads 208 may be electrically coupled to one or more circuits of the die 202. In some embodiments, the dummy data pads 208 may be electrically isolated from all circuits of the die 202. For purposes of description, the dummy data pads 208 are... Figure 2CThe diagram shows four dummy data pads; in other embodiments, any number of dummy data pads 208 may be included. Dummy data pads 208 may be arranged alternately with data pads 204. For example, from left to right, data pads 204 and dummy data pads 208 include data pad 204a, dummy data pad 208a, data pad 204b, dummy data pad 208b, data pad 204c, dummy data pad 208c, data pad 204d, and dummy data pad 208d. As another example (not shown), groups of data pads 204 may be arranged alternately with groups of dummy data pads 208. For example, from left to right, data pads 204 and dummy data pads 208 may include data pads 204a, 204b, dummy data pads 208a, 208b, 204c, 204d, 208c, and 208d. Because data pads 204 and dummy data pads 208 are arranged alternately, one of the data pads 204 (e.g., data pad 204a) may be near an edge (e.g., fourth edge 234), and one of the dummy data pads 208 (e.g., dummy data pad 208d) may be near an opposite edge (e.g., second edge 230).

[0053] The bare die 202 includes data pads 206a, 206b, 206c, and 206d (collectively referred to as "data pads 206") disposed near the third edge 232; for purposes of description, the data pads 206 are... Figure 2C The diagram shows four data pads; in other embodiments, any number of data pads 206 may be included. The data pads 206 may be electrically coupled to corresponding circuitry to allow access devices to be electrically coupled (e.g., via interlayer connections) to one or more corresponding circuitry of the memory array.

[0054] Die 202 includes dummy data pads 210a, 210b, 210c, and 210d (collectively, “dummy data pads 210”) disposed near the third edge 232. The dummy data pads 210 may be electrically coupled to one or more circuits of die 202. In some embodiments, the dummy data pads 210 may be electrically isolated from all circuits of die 202. For purposes of description, the dummy data pads 210 are... Figure 2CThe diagram shows four dummy data pads; in other embodiments, any number of dummy data pads 210 may be included. Dummy data pads 210 may be arranged alternately with data pads 206. For example, from left to right, data pads 206 and dummy data pads 210 include data pad 206d, dummy data pad 210d, data pad 206c, dummy data pad 210c, data pad 206b, dummy data pad 210b, data pad 206a, and dummy data pad 210a. As another example (not shown), groups of data pads 206 may be arranged alternately with groups of dummy data pads 210, for example, from left to right: data pad 206d, data pad 206c, dummy data pad 210d, dummy data pad 210c, data pad 206b, data pad 206a, dummy data pad 210b, and dummy data pad 210a. Because data pads 206 and dummy data pads 210 are arranged alternately, one of the data pads 206 (e.g., data pad 206d) may be near an edge (e.g., fourth edge 234), and one of the dummy data pads 210 (e.g., dummy data pad 210a) may be near an opposite edge (e.g., second edge 230).

[0055] In some embodiments, the arrangement of data pads 204 and dummy data pads 208 may be symmetrical about axis 244 to the arrangement of data pads 206 and dummy data pads 210. For example, the distance between each data pad 204 and the first edge 228 may be substantially the same as the distance between a corresponding data pad 206 and the third edge 232. Similarly, the distance between each dummy data pad 208 and the first edge 228 may be substantially the same as the distance between a corresponding dummy data pad 210 and the third edge 232. In some embodiments, all data pads 204 may be spaced substantially the same distance from the first edge 228, and all data pads 206 may be spaced substantially the same distance from the third edge 232. In other embodiments, one or more of the data pads 204 may be spaced from the first edge 228 by a first distance, and the others of the data pads 204 may be spaced from the first edge 228 by a second distance. In such embodiments, one or more corresponding data pads 206 may be spaced approximately a first distance from the third edge 232, and the other corresponding data pads 206 may be spaced approximately a second distance from the third edge 232. Additionally, the distance between each data pad 204 and the fourth edge 234 may be approximately the same as the distance between a corresponding data pad 206 and the fourth edge 234. For example, the distance between data pad 204a and the fourth edge 234 may be approximately the same as the distance between data pad 206d and the fourth edge 234. Similarly, the distance between each dummy data pad 208 and the fourth edge 234 may be approximately the same as the distance between a corresponding dummy data pad 210. For example, the distance between dummy data pad 208a and the fourth edge 234 may be approximately the same as the distance between dummy data pad 210d and the fourth edge 234.

[0056] Alternatively, in some embodiments, the arrangement of the data pad 204 relative to the upper left corner (e.g., where the first edge 228 is adjacent to the fourth edge 234) may be opposite to the arrangement of the dummy data pad 210 relative to the lower right corner (e.g., where the second edge 230 is adjacent to the third edge 232). For example, the data pad 204a may be spaced 236 from the first edge 228 and 240 from the fourth edge 234, and the dummy data pad 210a may be spaced 238 from the third edge 232 (which may be substantially the same as distance 236) and 242 from the second edge 230 (which may be substantially the same as distance 240).

[0057] Similarly, the arrangement of the dummy data pad 208 relative to the upper left corner can be the opposite of the arrangement of the data pad 206 relative to the lower right corner. For example, the distance between the dummy data pad 208a and the first edge 228 can be approximately the same as the distance between the data pad 206a and the third edge 232, and the distance between the dummy data pad 208a and the fourth edge 234 can be approximately the same as the distance between the data pad 206a and the second edge 230.

[0058] In some embodiments, all data pads 204 may be spaced substantially the same distance from the first edge 228. In such embodiments, all dummy data pads 208 may be spaced substantially the same distance from the third edge 232. In other embodiments, one or more of the data pads 204 may be spaced from the first edge 228 at a first distance, and the others of the data pads 204 may be spaced from the first edge 228 at a second distance. In such embodiments, corresponding one or more of the dummy data pads 208 may be spaced from the third edge 232 at a first distance, and corresponding others of the dummy data pads 208 may be spaced from the third edge 232 at a second distance.

[0059] Such an arrangement of data pads 204, 206, dummy data pads 208, and dummy data pads 210 allows the data pads of the first die to align with the dummy data pads of the second die when substantially identical copies of the die 202 are rotated and stacked. For example, data pads 204, dummy data pads 208, 206, and 210 can be arranged such that when the die 202 is rotated substantially 180° about an axis between the first edge 228, the second edge 230, the third edge 232, and the fourth edge 234, data pad 204 will be in the position previously occupied by dummy data pad 210, dummy data pad 208 will be in the position previously occupied by data pad 206, data pad 206 will be in the position previously occupied by dummy data pad 208, and dummy data pad 210 will be in the position previously occupied by data pad 204.

[0060] The bare die 202 includes data pads 212-218, comprising: data pads 212a and 212b, which may be first-class common data pads; data pads 214a and 214b, which may be second-class common data pads; data pads 216a and 216b, which may be third-class common data pads; and data pads 218a and 218b, which may be fourth-class common data pads. For purposes of description, data pads 212-218 comprise four categories of common data pads. In other embodiments, any number of common data pads and any number of categories of common data pads may be included. Data pads 212a, 214a, 216a, and 218a may be near a first edge 228, and data pads 212b, 214b, 216b, and 218b may be near a third edge 232. Compared to data pads 204 and 206, data pads 212-218 can be common data pads used for common data channels.

[0061] The bare die 202 includes data pads 220-226, comprising: data pads 220a and 220b, which may be common data pads of a first category; data pads 222a and 222b, which may be common data pads of a second category; data pads 224a and 224b, which may be common data pads of a third category; and data pads 226a and 226b, which may be common data pads of a fourth category. For purposes of description, data pads 220-226 comprise four categories of common data pads. In other embodiments, any number of common data pads and any number of categories of common data pads may be included. Data pads 220a, 222a, 224a, and 226a may be near a first edge 228, and data pads 220b, 222b, 224b, and 226b may be near a third edge 232. Compared to data pads 204 and 206, data pads 220-226 can be common data pads used for common data channels.

[0062] In some embodiments, the arrangement of data pads 212a, 214a, 216a, and 218a may be symmetrical about axis 244 to the arrangement of data pads 220b, 222b, 224b, and 226b. For example, the distance between each of data pads 212a, 214a, 216a, and 218a and the first edge 228 may be substantially the same as the distance between a corresponding data pad 220b, 222b, 224b, and 226b and the third edge 232. In some embodiments, all data pads 212a, 214a, 216a, and 218a may be substantially the same distance from the first edge 228, and all data pads 220b, 222b, 224b, and 226b may be substantially the same distance from the third edge 232. In other embodiments, one or more of data pads 212a, 214a, 216a, and 218a may be spaced from the first edge 228 by a first distance, and the others of data pads 212a, 214a, 216a, and 218a may be spaced from the first edge 228 by a second distance. In such embodiments, corresponding one or more of data pads 220b, 222b, 224b, and 226b may be spaced from the third edge 232 by a substantially first distance, and corresponding others of data pads 220b, 222b, 224b, and 226b may be spaced from the third edge 232 by a substantially second distance. Additionally, the distance between each of data pads 212a, 214a, 216a, and 218a and the fourth edge 234 may be substantially the same as the distance between a corresponding one of data pads 220b, 222b, 224b, and 226b and the fourth edge 234. For example, the distance between data pad 212a and the fourth edge 234 can be substantially the same as the distance between data pad 220b and the fourth edge 234. Furthermore, the distance between each of data pads 212a, 214a, 216a, and 218a and the axis 246 can be substantially the same as the distance between the corresponding data pads 220b, 222b, 224b, and 226b and the axis 246. For example, the distance between data pad 218a and the axis 246 can be substantially the same as the distance between data pad 226b and the axis 246.

[0063] In some embodiments, according to layout 200c, the arrangement of data pads 212a, 214a, 216a, and 218a may be symmetrical about axis 246 with respect to the arrangement of data pads 220a, 222a, 224a, and 226a. For example, the distance between each of data pads 212a, 214a, 216a, and 218a and the first edge 228 may be substantially the same as the distance between the corresponding data pads 220a, 222a, 224a, and 226a and the first edge 228. In some embodiments, all data pads 212a, 214a, 216a, and 218a and data pads 220a, 222a, 224a, and 226a may be spaced substantially the same distance from the first edge 228. In other embodiments, one or more of data pads 212a, 214a, 216a, and 218a may be spaced from the first edge 228 by a first distance, and the others of data pads 212a, 214a, 216a, and 218a may be spaced from the first edge 228 by a second distance. In such embodiments, corresponding one or more of data pads 220a, 222a, 224a, and 226a may be spaced from the first edge 228 by a substantially first distance, and corresponding others of data pads 220a, 222a, 224a, and 226a may be spaced from the first edge 228 by a substantially second distance. Additionally, the distance between each of data pads 212a, 214a, 216a, and 218a and the fourth edge 234 may be substantially the same as the distance between a corresponding one of data pads 220a, 222a, 224a, and 226a and the second edge 230. For example, the distance between data pad 212a and the fourth edge 234 can be substantially the same as the distance between data pad 220a and the second edge 230. Furthermore, the distance between each of data pads 212a, 214a, 216a, and 218a and the axis 246 can be substantially the same as the distance between the corresponding data pads 220a, 222a, 224a, and 226a and the axis 246. For example, the distance between data pad 218a and the axis 246 can be substantially the same as the distance between data pad 226a and the axis 246.

[0064] In some embodiments, the arrangement of the data pads 212a, 214a, 216a, and 218a of each category relative to the upper left corner may be the opposite of the arrangement of the data pads 212b, 214b, 216b, and 218b of each category relative to the lower right corner. For example, data pad 212a (of the first category) may be spaced 248 from the first edge 228, data pad 212b (of the first category) may be spaced 250 from the third edge 232 (which may be substantially the same as the distance 248), data pad 212a may be spaced 252 from the fourth edge 234, and data pad 212b may be spaced 254 from the third edge 232 (which may be substantially the same as the distance 252). Similarly, the distance between the (second category) data pad 214a and the first edge 228 can be substantially the same as the distance between the (second category) data pad 214b and the third edge 232, and the distance between the data pad 214a and the fourth edge 234 can be substantially the same as the distance between the data pad 214b and the second edge 230. Furthermore, the (fourth category) data pad 218a can be 256 meters away from the first edge 228, the data pad 218b can be 258 meters away from the third edge 232 (which can be substantially the same as distance 256), the data pad 218a can be 260 meters away from the axis 246, and the data pad 218b can be 262 meters away from the axis 246 (which can be substantially the same as distance 260).

[0065] In some embodiments, all data pads 212a, 214a, 216a, and 218a may be spaced approximately the same distance from the first edge 228. In such embodiments, all data pads 212b, 214b, 216b, and 218b may be spaced approximately the same distance from the third edge 232. In other embodiments, one or more of the data pads 212a, 214a, 216a, and 218a may be spaced a first distance from the first edge 228, and the others of the data pads 212a, 214a, 216a, and 218a may be spaced a second distance from the first edge 228. In such embodiments, one or more of the corresponding data pads 212b, 214b, 216b and 218b may be spaced from the third edge 232 by a substantially first distance, and the other corresponding data pads 212b, 214b, 216b and 218b may be spaced from the third edge 232 by a substantially second distance.

[0066] Such an arrangement of data pads 212-218 allows for alignment of common data pads of the same class when substantially identical copies of the bare die 202 are rotated and stacked.

[0067] Will Figure 2A and Figure 2C Relatedly, based on the principles and patterns of layout 200c, Figure 2AThe data pad of the DW0 region of ChA relative to Figure 2A The layout of the upper left corner of die 274 is the opposite of the layout of the dummy data pads of the DW1 area of ​​ChL relative to the lower right corner of die 274. This layout of the data pads and dummy data pads ensures that when a copy of die 274 is rotated and stacked on top of die 274, the data pads of the DW0 area of ​​ChA of die 274 are aligned with the dummy data pads of the DW1 area of ​​the DW1 area of ​​the DW1 area of ​​ChL of the copy of die 274. Furthermore, according to the principle and pattern of layout 200c, the dummy data pads of the DW0 area of ​​ChA of die 274 will be aligned with the data pads of the DW1 area of ​​ChL of the DW1 area of ​​the copy of die 274. The same applies to the DW1 areas of ChA and ChL, the DW0 areas of ChB and ChK, and so on.

[0068] In some embodiments, the layout of the data pads and dummy data pads in each DW0 may correspond to the layout of the dummy data pads in each DW1, and the layout of the dummy data pads in each DW0 may correspond to the layout of the data pads in each DW1. Therefore, the layout of the data pads and dummy data pads within each DW may follow the principles and patterns of layout 200c for the DW. For example, each DW may be considered as a bare die 202 and may follow the principles and patterns of layout 200c. Similarly, the layout of the data pads and dummy data pads within each AW may follow the principles and patterns of layout 200c for the AW.

[0069] Similarly, based on the principles and patterns of layout 200c, Figure 2A The public data pads for each category of the DW0 area of ​​ChA relative to Figure 2A The layout of the upper left corner of die 274 can be the same as the layout of the common data pads of each category in the DW1 area of ​​ChL relative to the lower right corner of die 274. This layout of the common data pads of each category ensures that when a copy of die 274 is rotated and stacked on top of die 274, the common data pads of each category in the DW0 of ChA of die 274 are aligned with the common data pads of the same category in the DW1 of the copy of die 274 in ChL. The same applies to the DW1 of ChA and the DW0 of ChL, the DW0 of ChB and the DW1 of ChK, and so on.

[0070] In some embodiments, the layout of the common data pads of each category in each DW0 may correspond to the layout of the common data pads of each category in each DW1. Therefore, the layout of the common data pads of each category within each DW may follow the principles and patterns of layout 200c for the DW. For example, each DW may be considered as a bare die 202 and may follow the principles and patterns of layout 200c. Similarly, the layout of the common data pads of each category within each AW may follow the principles and patterns of layout 200c for the AW.

[0071] Figure 3 This is a functional block diagram illustrating an example die stack 300 according to at least one embodiment of the present disclosure. For example, the die stack 300 may be referred to as a "memory device" or a "memory system". Each die in the die stack 300 may be... Figure 2C An example of die 202. Die stack 300 includes three instances of die 202 rotated and stacked relative to each other. Three dies are shown for illustrative purposes. In other embodiments, any number of dies may be included. Die stack 300 (where alternating dies are rotated 180° relative to each other) allows the data pads of a particular die to be aligned with the dummy data pads of the alternating dies and / or allows the alignment of common data pads of various categories, which enables linear interlayer connections, such as without lateral connection portions.

[0072] The die stack 300 includes die 302 (e.g., the bottom die), die 304 above die 302, and die 306 above die 304. Each die in the die stack 300 may be substantially identical to each of the others in the die stack 300. Each die in the die stack 300 may be rotated substantially 180° relative to the corresponding die directly below it about an axis orthogonal to the bottom die. For example, die 304 may be rotated substantially 180° relative to die 302, and die 306 may be rotated substantially 180° relative to die 304.

[0073] Each die in the die stack 300 may contain several data pads 308, each data pad being electrically coupled to a corresponding circuit (not shown) on the corresponding die where the data pad 308 is located. The data pads 308 may be... Figure 2C Examples of data pads 204 and 206.

[0074] Each die in the die stack 300 may further include a plurality of dummy data pads 310, each dummy data pad not electrically coupled to the circuitry of the corresponding die on which the dummy data pad 310 is located. In some embodiments, the dummy data pads 310 may be electrically isolated relative to the die on which the dummy data pad is located. For example, the dummy data pads 310 on die 302 may be electrically isolated relative to die 302. The plurality of dummy data pads 310 may be arranged relative to the plurality of data pads 308 such that each of the plurality of dummy data pads 310 of each die in the die stack 300 may be aligned with a corresponding data pad in the plurality of data pads 308. The dummy data pads 310 may be Figure 2C Examples of dummy data pads 208 and dummy data pads 210.

[0075] For example, die 302 may include one or more first data pads located near the upper left corner of the die, one or more first dummy data pads located near the upper left corner, one or more second data pads located near the lower right corner of the die, and one or more second dummy data pads located near the lower right corner. A first position of the first data pad relative to the upper left corner may correspond to a second position of the second dummy data pad relative to the lower right corner, and a third position of the first dummy data pad relative to the upper left corner may correspond to a fourth position of the second data pad relative to the lower right corner.

[0076] Because the data pads 308 of the dies in the die stack 300 are aligned with the dummy data pads 310 of adjacent dies in the die stack 300, a linear interlayer connection can electrically couple the dummy data pads 310 and data pads 308 of adjacent dies in the die stack 300. For example, interlayer connection 316 can electrically couple the dummy data pad 310 of die 302 to the data pads 308 of die 304 and the dummy data pads 310 of die 306.

[0077] Data pads and interlayer connections can be implemented such that each die in the die stack 300 is associated with one or more interlayer connections to provide one or more independent data channels for each die in the die stack 300. For example, an interlayer connection may electrically couple all data pads 308 of die 302 to all data pads 308 of die 306. Access means can be configured to access die 302 through a specific interlayer connection and access die 306 through other interlayer connections.

[0078] Alternatively, each die in the die stack 300 may include a data pad 312. The data pad 312 may be a common data pad of various categories. The data pads 312 may be arranged such that each data pad 312 of each die in the die stack 300 is aligned with a corresponding data pad 312 of a corresponding die directly beneath the die. For example, each data pad 312 of die 302 is aligned with each data pad 312 of die 304, and each data pad 312 of die 304 is also aligned with each data pad 312 of die 306.

[0079] The arrangement of the data pads 312 of each category allows each data pad 312 of the first category for each die in the die stack 300 to be aligned with its counterpart in the first category of the data pads 312 of the corresponding die directly beneath the die. Furthermore, each data pad 312 of the second category for each die in the die stack 300 is aligned with its counterpart in several second category data pads 312 of the corresponding die directly beneath the die. For example, the top left data pad in each die stack 300 may have a first category. Additionally, the second leftmost data pad in each die stack 300 may have a second category. Therefore, an interlayer connection 318 can be electrically coupled to the first category of data pads 312 of all dies in the die stack 300, and another interlayer connection (not shown) can be electrically coupled to all the second category data pads 312.

[0080] Figure 4 This is a functional block diagram illustrating an example layout 400 of data pads and dummy data pads on die 402 according to at least one embodiment of the present disclosure. Layout 400 allows multiple instances of die 402 to be rotated and stacked relative to each other. The stacking of instances of die 402 (where alternating dies are rotated 90° relative to each other) allows data pad dummy data pad alignment and / or common data pad alignment of various categories, which enables linear interlayer connections, such as without lateral connection portions.

[0081] Die 402 may contain one or more memory arrays (e.g., Figure 1 Memory array 102; Figure 4 (Not shown in the image). The data pads of die 402 can provide data channels for the memory array. For example, the data pads can be electrically coupled to individual inputs and / or outputs of the memory array.

[0082] The bare film 402 includes a first edge 410, a second edge 412, a third edge 414, and a fourth edge 416.

[0083] Die 402 includes a plurality of data pads 404, each data pad being electrically coupled to a corresponding circuit of die 402. The data pads 404 may be disposed near the first edge 410. Figure 4 In this illustration, seven data pads 404 are shown for illustrative purposes. In other embodiments, other numbers of data pads 404 may be included.

[0084] The die 402 includes dummy data pads 406 that are not electrically coupled to circuitry. In some embodiments, the dummy data pads 406 may be electrically isolated. The dummy data pads 406 include a first number of dummy data pads 406 disposed near a second edge 412, a second number of dummy data pads 406 disposed near a third edge 414, and a third number of dummy data pads 406 disposed near a fourth edge 416. Figure 4 For illustrative purposes, twenty-one dummy data pads 406 are shown. In other embodiments, other numbers of dummy data pads 406 may be included.

[0085] The arrangement of the dummy data pad 406 relative to each of the second edge 412, the third edge 414, and the fourth edge 416 can be symmetrical to the arrangement of the data pad 404 relative to the first edge 410. For example, the first data pad can be spaced a first distance from the first edge 410 and a second distance from the fourth edge 416. A corresponding dummy data pad can be spaced approximately a first distance from the second edge 412 and approximately a second distance from the first edge 410. Another corresponding dummy data pad can be spaced approximately a first distance from the third edge 414 and approximately a second distance from the second edge 412. Furthermore, another corresponding dummy data pad can be spaced approximately a first distance from the fourth edge 416 and approximately a second distance from the third edge 414.

[0086] This arrangement of data pad 404 and dummy data pad 406 allows the data pad of the first die to be aligned with the dummy data pads of the second, third, and fourth dies when substantially identical copies of the die 402 are rotated and stacked.

[0087] The bare die 402 further includes a data pad 408. The data pad 408 can be a common data pad, such as different categories of common data pads. For example, in the data pad 408 near the first edge 410, the left data pad may have a first category, and the right data pad may have a second category. Furthermore, in the data pad 408 near the second edge 412, the top data pad may have a first category, and the bottom data pad may have a second category. Furthermore, in the data pad 408 near the third edge 414, the right data pad may have a first category, and the left data pad may have a second category. Furthermore, in the data pad 408 near the fourth edge 416, the bottom data pad may have a first category, and the top data pad may have a second category.

[0088] This arrangement of data pads 408 allows for alignment of data pads 408 of the same type when substantially identical copies of the bare die 402 are rotated and stacked.

[0089] Figure 5This is a functional block diagram illustrating an example die stack 500 according to at least one embodiment of the present disclosure. For example, the die stack 500 may be referred to as a "memory device" or a "memory system". Each die in the die stack 500 may be... Figure 4 An example of die 402. Die stack 500 includes five instances of die 402 rotated and stacked relative to each other. Five dies are shown for illustrative purposes. In other embodiments, any number of dies may be included. Die stack 500 (where alternating dies are rotated 90° relative to each other) allows data pads of a particular die to be aligned with dummy data pads of other dies and / or common data pads of various categories, enabling linear interlayer connections, such as without lateral connection portions.

[0090] Die stack 500 includes die 502, die 504, die 506, die 508, and die 510. Each die in die stack 500 may be substantially identical to each of the other dies in die stack 500. Each die in die stack 500 may be rotated approximately 90° relative to the corresponding die directly below it about an axis orthogonal to the bottom die. For example, die 504 may be rotated approximately 90° relative to die 502, and die 506 may be rotated approximately 90° relative to die 504.

[0091] Each die in the die stack 500 may contain several data pads 512, wherein each data pad is electrically coupled to a corresponding circuit on the corresponding die where the data pad 512 is located. The data pads 512 may be... Figure 4 An example of data pad 404.

[0092] Each die in the die stack 500 may also include a plurality of dummy data pads 514 that are not electrically coupled to circuitry on the die where the dummy data pad 514 is located. The plurality of dummy data pads 514 may be arranged relative to the plurality of data pads 512 such that each of the plurality of dummy data pads 514 on each die in the die stack 500 may be aligned with a corresponding data pad in the plurality of data pads 512. The dummy data pads 514 may be... Figure 4 An example of dummy data pad 406.

[0093] For example, die 502 may include one or more first data pads located near a first edge, one or more first dummy data pads located near a second edge, one or more second dummy data pads located near a third edge, and one or more third dummy data pads located near a fourth edge. A first position of the first data pad relative to the first edge may correspond to: a second position of the first dummy data pad relative to the second edge, a third position of the second dummy data pad relative to the third edge, and a fourth position of the third dummy data pad relative to the fourth edge.

[0094] Because the data pads 512 of the dies in the die stack 500 are aligned with the dummy data pads 514 of at least some of the other dies in the die stack 500, a linear interlayer connection can electrically couple the dummy data pads 514 and the data pads 512. For example, interlayer connection 528 can electrically couple the dummy data pads of die 510, the data pads of die 508, the dummy data pads of die 506, the dummy data pads of die 504, and the dummy data pads of die 502.

[0095] Data pads and interlayer connections can be implemented such that each die in the die stack 500 is associated with one or more interlayer connections to provide one or more independent data channels for each die in the die stack 500. For example, an interlayer connection may electrically couple all data pads 512 of die 502 to all data pads 512 of die 510. Access means can be configured to access die 502 through a specific interlayer connection and access die 510 through other interlayer connections. For example, all interlayer connections 518, 520, and 526 may be electrically coupled to the data pads of die 502 and die 510. Access means may determine that the memory array of die 502 is accessed through interlayer connection 518 and the memory array of die 510 is accessed through interlayer connection 520.

[0096] Alternatively, each die in the die stack 500 may include a data pad 516. The data pad 516 may be a common data pad of various categories. The data pads 516 may be arranged such that each data pad 516 of each die in the die stack 500 is aligned with a corresponding data pad 516 of a corresponding die directly beneath the die. For example, each data pad 516 of die 502 is aligned with each data pad 516 of die 504, each data pad 516 of die 504 is also aligned with each data pad 516 of die 506, each data pad 516 of die 506 is also aligned with each data pad 516 of die 508, and each data pad 516 of die 508 is also aligned with each data pad 516 of die 510.

[0097] The arrangement of the data pads 516 of each category allows each of the first category of data pads 516 for each die in the die stack 500 to be aligned with its counterpart in the first category of data pads 516 for the corresponding die directly beneath the die. Furthermore, each of the second category of data pads 516 for each die in the die stack 500 is aligned with its counterpart in several second category data pads 516 for the corresponding die directly beneath the die. For example, in the data pads 516 of each die in the die stack 500: in the data pads 516 near the first edge, the left data pad may have a first category and the right data pad may have a second category; in the data pads near the second edge, the top data pad may have a first category and the bottom data pad may have a second category; in the data pads 408 near the third edge, the right data pad may have a first category and the left data pad may have a second category; and in the data pads 408 near the fourth edge, the bottom data pad may have a first category and the top data pad may have a second category. Therefore, interlayer connection 522 can be electrically coupled to the first category of data pads 516 of all dies in the die stack 500, and interlayer connection 524 can be electrically coupled to all the second category of data pads 516.

[0098] Figure 6 This is a flowchart illustrating an example method 600 according to at least one embodiment of the present disclosure. Method 600 may be arranged according to at least one embodiment described in the present disclosure. In some embodiments, method 600 may be arranged in a... Figure 1 Memory device 100 Figure 3 300 bare dies stacked Figure 5 500 bare dies stacked Figure 7 Memory system 700, Figure 8 The electronic system 800 or at least a portion of another device or system is executed. Although shown as discrete blocks, the individual blocks can be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0099] At frame 602, several dies are available. Each of the several dies may be substantially identical to each of the other dies. Each die may include several data pads electrically coupled to the corresponding circuitry of the die and several dummy data pads for circuitry not electrically coupled to the die. Figure 2C The bare die 202 (including data pad 204, data pad 206, dummy data pad 208 and dummy data pad 210) may be the first instance of the bare die among the plurality of bare dies obtained at box 602. Figure 4The bare die 402 (including data pad 404 and dummy data pad 406) may be a second instance of the bare die among the plurality of bare dies obtained at frame 602.

[0100] At frame 604, the plurality of dies can be rotated and stacked on top of each other such that the data pad of one of the dies is aligned with the dummy data pads of the dies above and below that one of the dies. Figure 3 The die stack 300 can be a first instance of how the dies are rotated and stacked at frame 604. For example, rotating and stacking each of the plurality of dies may involve rotating each of the die stacks (except the bottom die) approximately 180° relative to the die below it. Figure 5 The die stack 500 can be a second instance of how the dies are rotated and stacked at frame 604. For example, rotating and stacking each of the plurality of dies may involve rotating each of the die stacks (except the bottom die) approximately 90° relative to the die below it.

[0101] At block 606, some of the data pads of the plurality of dies can be electrically coupled to dummy data pads of the others of the plurality of dies. Furthermore, the dummy data pads of the others of the plurality of dies can be electrically coupled to the data pads of some of the plurality of dies. Figure 3 Interlayer connections 314, 316, and 318 may be first instances of interlayer connections that electrically couple some of the data pads of the plurality of dies to dummy data pads of the others at frame 606. Figure 5 Interlayer connections 518, 520, 522, 524, 526, and 528 may be a second instance of interlayer connections that electrically couple some of the data pads of the plurality of dies to dummy data pads of the others of the plurality of dies at frame 606.

[0102] Modifications, additions, or omissions may be made to method 600 without departing from the scope of this disclosure. For example, the operations of method 600 may be performed in a different order. Furthermore, the operations and actions outlined are provided by way of example only, and some of these operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without departing from the essence of the disclosed embodiments.

[0103] Figure 7This is a simplified block diagram illustrating an example memory system 700 implemented according to at least one embodiment of the present disclosure. The memory system 700, which may include, for example, semiconductor devices, includes a plurality of memory devices 702 and a controller 704. The controller 704 may be operatively coupled to the memory devices 702 to transmit command / address signals (e.g., by...) to the memory devices 702. Figure 1 (Command / address signals received by command terminal 112 and / or address terminal 110).

[0104] According to one or more embodiments disclosed herein, the memory device 702 of the memory system 700 (e.g., Figure 1 At least one of the memory device 100 and / or controller 704 may include according to Figure 2C Layout 200c or Figure 4 A layout of 400 for one or more bare wafers.

[0105] An electronic system is also disclosed. According to various embodiments, the electronic system may include a memory device having a plurality of memory dies, each memory die having an array of memory cells. Each memory cell may include an access transistor and a memory element operatively coupled to the access transistor.

[0106] Figure 8 This is a simplified block diagram illustrating an electronic system 800 implemented according to at least one embodiment of the present disclosure. The electronic system 800 includes at least one input device 802, which may include, for example, a keyboard, mouse, or touchscreen. The electronic system 800 further includes at least one output device 804, such as a monitor, touchscreen, or speaker. The input device 802 and the output device 804 are not necessarily separate from each other. The electronic system 800 further includes a storage device 806. The input device 802, output device 804, and storage device 806 may be coupled to a processor 808. The electronic system 800 further includes a memory device 810 coupled to the processor 808. The memory device 810 may include… Figure 7 The electronic system 800 may include at least a portion of the memory system 700. The electronic system 800 may include, for example, computing, processing, industrial, or consumer products. For example, but not limitingly, the electronic system 800 may include a personal computer or computer hardware component, a server or other networking hardware component, a database engine, an intrusion prevention system, a handheld device, a tablet computer, a notebook computer, a camera, a mobile phone, a music player, a wireless device, a display, a chipset, a game, a vehicle, or other known systems.

[0107] Various embodiments may include a die comprising: a plurality of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite to the first edge, and a fourth edge opposite to the second edge. The die may also include a first number of data pads electrically coupled to the plurality of circuits in different locations. The first number of data pads may be disposed near the first edge. The die may also include a first number of dummy data pads not electrically coupled to the plurality of circuits, arranged alternately with the first number of data pads near the first edge, wherein a first data pad of the first number of data pads is disposed near the fourth edge, and a first dummy data pad of the first number of dummy data pads is disposed near the second edge. The die may also include a second number of data pads electrically coupled to the plurality of circuits in different locations. The second number of data pads may be disposed near the third edge. The die may further include a second number of dummy data pads, which are not electrically coupled to the plurality of circuits, and are arranged alternately with the second number of data pads near the third edge, wherein a second data pad of the second number of data pads is near the fourth edge, and a second dummy data pad of the second number of dummy data pads is near the second edge.

[0108] Various embodiments may include an apparatus comprising a die including a bottom die and a plurality of dies disposed above the bottom die. Each of the dies may be substantially identical to each of the other dies. Each of the plurality of dies may be rotated approximately 180° relative to a corresponding die directly below the bottom die about an axis orthogonal to the bottom die. Each of the dies may include a plurality of circuits, a plurality of data pads electrically coupled to the plurality of circuits at different grounds, and a plurality of dummy data pads not electrically coupled to the plurality of circuits. The plurality of dummy data pads may be arranged relative to the plurality of data pads such that each of the plurality of dummy data pads of each of the plurality of dies is aligned with a corresponding data pad of the plurality of data pads.

[0109] Various embodiments may include an apparatus comprising a die comprising a bottom die and a plurality of dies disposed above the bottom die. Each of the dies may be substantially identical to each of the other dies. Each of the plurality of dies may be rotated approximately 90° relative to a corresponding die directly below the bottom die about an axis orthogonal to the bottom die. Each of the dies may include a plurality of circuits, a plurality of data pads electrically coupled to the plurality of circuits at different grounds, and a plurality of dummy data pads not electrically coupled to the plurality of circuits. The plurality of dummy data pads may be arranged relative to the plurality of data pads such that each of the plurality of dummy data pads of each of the plurality of dies is aligned with a corresponding data pad of the plurality of data pads.

[0110] Various embodiments may include a die comprising: a plurality of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite to the first edge, and a fourth edge opposite to the second edge. The die may also include a plurality of data pads electrically coupled to the plurality of circuits. The plurality of data pads may be disposed near the first edge. The die may further include: a first plurality of dummy data pads not electrically coupled to the plurality of circuits, disposed near the second edge; a second plurality of dummy data pads not electrically coupled to the plurality of circuits, disposed near the third edge; and a third plurality of dummy data pads not electrically coupled to the plurality of circuits, disposed near the fourth edge. In such embodiments, the plurality of data pads may include a first data pad spaced a first distance from the first edge and a second distance from the fourth edge; the first plurality of dummy data pads may include a first dummy data pad that is substantially spaced a first distance from the second edge and substantially spaced a second distance from the first edge; the second plurality of dummy data pads may include a second dummy data pad that is substantially spaced a first distance from the third edge and substantially spaced a second distance from the second edge; and the third plurality of dummy data pads may include a third dummy data pad that is substantially spaced a first distance from the fourth edge and substantially spaced a second distance from the third edge.

[0111] Various embodiments may include a method comprising: stacking a plurality of dies such that a data pad of one of the dies is aligned with dummy data pads of dies above and below that one of the dies. Each of the dies may be substantially identical to each of the other dies. The method may further include: electrically coupling some of the data pads of the dies to the dummy data pads of the others. Such embodiments may also include rotating all dies except the bottom die substantially 90° or 180° relative to the die below them before stacking the dies.

[0112] As is customary, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations for describing various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Additionally, some aspects of the drawings may be simplified for clarity. Consequently, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0113] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For example, an apparatus or memory device may include a system-on-a-chip (SoC).

[0114] As used herein, unless otherwise specified, the term “semiconductor” should be broadly interpreted to include microelectronic and MEMS devices that may or may not employ semiconductor functionality for operation (e.g., magnetic storage, optical devices, etc.).

[0115] The terms used herein, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0116] Furthermore, if the intention is to use a specific number of introduced claim statements, then this intention will be explicitly stated in the claims, and without such a statement, this intention does not exist. For example, to aid understanding, the appended claims may contain the introductory phrases “at least one” and “one or more” to introduce the claim statements. However, the use of such phrases should not be construed as implying that introducing the claim statements with the indefinite article “a / an” limits any particular claim containing such introduced claim statements to embodiments containing only one such statement, even if the same claim contains the introductory phrases “one or more” or “at least one” and an indefinite article such as “a” (e.g., “a” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles to introduce claim statements. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0117] Furthermore, even when a specific number of the introduced claims are explicitly stated, it should be understood that such a statement should generally be interpreted as referring to at least the number of statements (e.g., a simple statement of "two statements" without other modifiers means at least two statements, or two or more statements). Moreover, in cases where conventions such as "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, such structures are generally intended to include only A, only B, only C, A and B, A and C, B and C, or A, B, and C, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0118] Furthermore, it should be understood that any transitional word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, is intended to include the possibility of including one, any, or both of the stated terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0119] Furthermore, the use of the terms "first," "second," "third," etc., in this document does not necessarily imply a specific order or number of elements. Generally, the terms "first," "second," "third," etc., are used as general identifiers to distinguish different elements. Where the terms "first," "second," "third," etc., do not imply a specific order, they should not be construed as implying a specific order. Similarly, where the terms "first," "second," "third," etc., do not imply a specific number of elements, they should not be construed as implying a specific number of elements.

[0120] Additional non-limiting embodiments of this disclosure include:

[0121] Example 1: A die comprising: a plurality of circuits; a first edge; a second edge perpendicular to the first edge; a third edge opposite to the first edge; a fourth edge opposite to the second edge; a first plurality of data pads electrically coupled to the plurality of circuits, the first plurality of data pads being disposed near the first edge; and a first plurality of dummy data pads not electrically coupled to the plurality of circuits, alternating with the first plurality of data pads, disposed near the first edge, wherein a first data pad among the first plurality of data pads is disposed near the fourth edge. The first dummy data pad of the first plurality of dummy data pads is located near the second edge; the second plurality of data pads, which are electrically coupled to the plurality of circuits respectively, are arranged near the third edge; and the second plurality of dummy data pads, which are not electrically coupled to the plurality of circuits, are arranged alternately with the second plurality of data pads near the third edge, wherein the second data pad of the second plurality of data pads is located near the fourth edge, and the second dummy data pad of the second plurality of dummy data pads is located near the second edge.

[0122] Example 2: The bare die according to Example 1, wherein the first data pad is separated from the first edge by a first distance and from the fourth edge by a second distance, and wherein the second dummy data pad is separated from the third edge by approximately the first distance and from the second edge by approximately the second distance.

[0123] Example 3: A bare die according to any one of Examples 1 and 2, wherein the first number of data pads are all separated from the first edge by a first distance, and the second number of dummy data pads are all separated from the third edge by approximately the first distance.

[0124] Example 4: A bare die according to any one of Examples 1 to 3, wherein the arrangement of the first number of data pads and the first number of dummy data pads is symmetrical with respect to the arrangement of the second number of data pads and the second number of data pads about an axis of symmetry parallel to the first edge and between the first edge and the third edge.

[0125] Example 5: A die according to any one of Examples 1 to 4, wherein the first number of data pads, the first number of dummy data pads, the second number of data pads, and the second number of dummy data pads are arranged such that when the die is rotated 180° approximately around an axis between the first edge, the second edge, the third edge, and the fourth edge, the first number of data pads will be in a first position previously occupied by the second number of dummy data pads, the first number of dummy data pads will be in a second position previously occupied by the second number of data pads, the second number of data pads will be in a third position previously occupied by the first number of dummy data pads, and the second number of dummy data pads will be in a fourth position previously occupied by the first number of data pads.

[0126] Example 6: A die according to any one of Examples 1 to 5, further comprising: a third number of data pads electrically coupled to the plurality of circuits at different grounds, the third number of data pads being disposed near the first edge, the third number of data pads including data pads of a first category and data pads of a second category, the third number of data pads including third data pads of the first category near the fourth edge and fourth data pads of the second category near the third data pads; and a fourth number of data pads electrically coupled to the plurality of circuits at different grounds, the fourth number of data pads being disposed near the third edge, the fourth number of data pads including data pads of the first category and data pads of the second category, the fourth number of data pads including fifth data pads of the first category near the second edge and sixth data pads of the second category near the fifth data pads.

[0127] Example 7: A bare die according to any one of Examples 1 to 6, wherein the third data pad is spaced a first distance from the first edge and a second distance from the fourth edge, and the fifth data pad is spaced substantially the first distance from the third edge and substantially the second distance from the second edge.

[0128] Example 8: A bare die according to any one of Examples 1 to 7, wherein all of the third number of data pads are separated from the first edge by a first distance, and all of the fourth number of data pads are separated from the third edge by substantially the first distance.

[0129] Example 9: A bare die according to any one of Examples 1 to 8, wherein: the third number of data pads further includes: a seventh data pad of the second category, which is near the center line between the fourth edge and the second edge and is closer to the fourth edge than to the second edge; and an eighth data pad of the first category, which is near the seventh data pad; and the fourth number of data pads further includes: a ninth data pad of the second category, which is near the center line and is closer to the second edge than to the second edge; and a tenth data pad of the first category, which is near the ninth data pad.

[0130] Example 10: A bare die according to any one of Examples 1 to 9, wherein the seventh data pad is spaced a first distance from the first edge and a second distance from the center line, and the ninth data pad is spaced substantially the first distance from the third edge and substantially the second distance from the center line.

[0131] Example 11: A bare die according to any one of Examples 1 to 10, wherein the seventh data pad is spaced a first distance from the first edge and a second distance from the center line, and the ninth data pad is spaced substantially the first distance from the third edge and substantially the second distance from the center line.

[0132] Example 12: A bare die according to any one of Examples 1 to 11, wherein the first type of data pad is used to transmit a first type of signal, and the second type of data pad is used to transmit a second type of signal.

[0133] Example 13: A bare die according to any one of Examples 1 to 12, wherein the third number of data pads are arranged in a third group of data pads, each third group of data pads including a first category of data pads and a second category of data pads, wherein the third group of data pads is arranged between the data pads including the first number of data pads and the first number of dummy data pads and the dummy data pad groups.

[0134] Example 14: An apparatus comprising: a die including a bottom die and a plurality of dies disposed above the bottom die, each of the dies being substantially identical to each of the other dies, each of the plurality of dies being rotated substantially 180° relative to a corresponding die directly below the bottom die about an axis orthogonal to the bottom die, each of the dies including: a plurality of circuits; a plurality of data pads electrically coupled to the plurality of circuits respectively; and a plurality of dummy data pads not electrically coupled to the plurality of circuits, the plurality of dummy data pads being disposed relative to the plurality of data pads such that each of the plurality of dummy data pads of each of the plurality of dies is aligned with a corresponding data pad of the plurality of data pads.

[0135] Example 15: The apparatus according to Example 14, wherein each of the dies includes: a first data pad among the plurality of data pads near the upper left corner of the die; a first dummy data pad among the plurality of dummy data pads near the upper left corner; a second data pad among the plurality of data pads near the lower right corner of the die; and a second dummy data pad among the plurality of dummy data pads near the lower right corner.

[0136] Example 16: The apparatus according to any one of Examples 14 and 15, wherein the first position of the first data pad relative to the upper left corner corresponds to the second position of the second dummy data pad relative to the lower right corner, and the third position of the first dummy data pad relative to the upper left corner corresponds to the fourth position of the second data pad relative to the lower right corner.

[0137] Example 17: The apparatus according to any one of Examples 14 to 16, wherein the plurality of data pads includes a first plurality of data pads, and wherein each of the dies includes a second plurality of data pads arranged such that each of the second plurality of data pads of each of the plurality of dies is aligned with a corresponding of the plurality of second data pads of the corresponding die directly beneath the die.

[0138] Example 18: An apparatus according to any of Examples 14 to 17, wherein each of the second plurality of data pads has a category according to a signal to be transmitted through the corresponding data pad, and wherein the second plurality of data pads are arranged such that each of the second plurality of first category data pads of each of the plurality of dies is aligned with a corresponding of the first category of the plurality of second data pads of the corresponding die directly beneath the die, and each of the second plurality of second category data pads of each of the plurality of dies is aligned with a corresponding of the second category of the plurality of second data pads of the corresponding die directly beneath the die.

[0139] Example 19: A method comprising: stacking a plurality of dies such that a data pad of one of the dies is aligned with dummy data pads of dies above and below the one of the dies, each of the dies being substantially identical to each of the other dies; and electrically coupling the data pads of some of the dies to the dummy data pads of the others of the dies.

[0140] Example 20: The method according to Example 19 further includes, before stacking the plurality of bare dies, rotating all of the bare dies except the bottom bare die by approximately 180° relative to the bare die below them.

[0141] Example 21: The method according to any of Examples 19 and 20 further includes, before stacking the plurality of bare dies, rotating all of the bare dies except the bottom bare die by approximately 90° relative to the bare die below them.

[0142] The embodiments of this disclosure described above and shown in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, various modifications to this disclosure will become apparent to those skilled in the art from the description, in addition to what is shown and described herein, such as alternative applicable combinations of the described elements. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. A die comprising: a number of circuits; a first edge; a second edge perpendicular to the first edge; a third edge opposite the first edge; a fourth edge opposite the second edge; a first number of data pads differentially electrically coupled to the number of circuits, the first number of data pads arranged near the first edge; a first number of dummy data pads not electrically coupled to the number of circuits, arranged near the first edge in alternation with the first number of data pads, wherein a first data pad of the first number of data pads is near the fourth edge and a first dummy data pad of the first number of dummy data pads is near the second edge; a second number of data pads differentially electrically coupled to the number of circuits, the second number of data pads arranged near the third edge; and a second number of dummy data pads not electrically coupled to the number of circuits, arranged near the third edge in alternation with the second number of data pads, wherein a second data pad of the second number of data pads is near the fourth edge and a second dummy data pad of the second number of dummy data pads is near the second edge, wherein the first number of data pads, the first number of dummy data pads, the second number of data pads, and the second number of dummy data pads are arranged such that when the die is rotated substantially 180° about an axis orthogonal to the die, the first number of data pads will be in a first position previously occupied by the second number of dummy data pads, the first number of dummy data pads will be in a second position previously occupied by the second number of data pads, the second number of data pads will be in a third position previously occupied by the first number of dummy data pads, and the second number of dummy data pads will be in a fourth position previously occupied by the first number of data pads.

2. The die of claim 1, wherein the first data pad is separated from the first edge by a first distance, separated from the fourth edge by a second distance, and wherein the second dummy data pad is separated from the third edge by substantially the first distance, separated from the second edge by substantially the second distance.

3. The die of claim 1, wherein all of the first number of data pads are separated from the first edge by a first distance and all of the second number of dummy data pads are separated from the third edge by substantially the first distance.

4. The die of claim 1, wherein the arrangement of the first number of data pads and the first number of dummy data pads is symmetric about a symmetry axis parallel to the first edge and between the first edge and the third edge, and the arrangement of the second number of data pads and the second number of dummy data pads is symmetric about the symmetry axis.

5. The die of claim 1, further comprising: ​ a third number of data pads differentially electrically coupled to the number of circuits, the third number of data pads arranged near the first edge, the third number of data pads including a first category of data pads and a second category of data pads, the third number of data pads including a third data pad of the first category near the fourth edge and a fourth data pad of the second category near the third data pad; and a fourth number of data pads differentially electrically coupled to the number of circuits, the fourth number of data pads arranged near the third edge, the fourth number of data pads including the first category of data pads and the second category of data pads, the fourth number of data pads including a fifth data pad of the first category near the second edge and a sixth data pad of the second category near the fifth data pad.

6. The die of claim 5, wherein the third data pad is separated from the first edge by a first distance, from the fourth edge by a second distance, and the fifth data pad is separated from the third edge by substantially the first distance and from the second edge by substantially the second distance.

7. The die of claim 5, wherein the third number of data pads are all separated from the first edge by a first distance, and the fourth number of data pads are all separated from the third edge by substantially the first distance.

8. The die of claim 5, wherein: the third number of data pads further includes a seventh data pad of the second category near a centerline between the fourth edge and the second edge and closer to the fourth edge than to the second edge, and an eighth data pad of the first category near the seventh data pad; and the fourth number of data pads further includes a ninth data pad of the second category near the centerline and closer to the second edge than to the second edge, and a tenth data pad of the first category of data pads near the ninth data pad.

9. The die of claim 8, wherein the seventh data pad is separated from the first edge by a first distance, from the centerline by a second distance, and the ninth data pad is separated from the third edge by substantially the first distance and from the centerline by substantially the second distance.

10. The die of claim 5, wherein the first category of data pads are for transmitting a first category of signals, and the second category of data pads are for transmitting a second category of signals.

11. The die of claim 5, wherein the third number of data pads are arranged in third data pad groups, each third data pad group including a first category data pad and a second category data pad, wherein the third data pad groups are arranged between data pad and dummy data pad groups including the first number of data pads and the first number of dummy data pads.

12. An apparatus comprising: A die including a bottom die and a number of dies arranged above the bottom die, each of the dies being substantially identical to each of the other dies, each of the number of dies being substantially rotated 180° about an axis orthogonal to the bottom die relative to a respective die directly below the die, each of the dies including: a number of circuits; a number of data pads electrically coupled differently to the number of circuits; and a number of dummy data pads not electrically coupled to the number of circuits, the number of dummy data pads being arranged relative to the number of data pads such that each of the number of dummy data pads of each of the number of dies is aligned with a respective data pad of the number of data pads of other dies disposed above and / or below the given die.

13. The apparatus of claim 12, wherein each of the dies includes: a first data pad of the number of data pads near a top left corner of the die; a first dummy data pad of the number of dummy data pads near the top left corner; a second data pad of the number of data pads near a bottom right corner of the die; and a second dummy data pad of the number of dummy data pads near the bottom right corner.

14. The apparatus of claim 13, wherein a first position of the first data pad relative to the top left corner corresponds to a second position of the second dummy data pad relative to the bottom right corner, and a third position of the first dummy data pad relative to the top left corner corresponds to a fourth position of the second data pad relative to the bottom right corner. a second number of data pads arranged such that each of the second number of data pads of each of the number of dies is aligned with a respective one of the second number of data pads of the respective die directly below the die.

15. The device of claim 12, wherein the number of data pads comprises a first number of data pads, and wherein each of the dies comprises:

16. The apparatus of claim 15, wherein each of the second number of data pads has a category according to a signal to be transmitted through the respective data pad, and wherein the second number of data pads are arranged such that each of the second number of data pads of a first category of each of the number of dies is aligned with a respective one of the second number of data pads of the first category of the respective die directly below the die, and each of the second number of data pads of a second category of each of the number of dies is aligned with a respective one of the second number of data pads of the second category of the respective die directly below the die. ​

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