Preparation Process of Thermoelectric Separation Circuit Board

Abstract

The present application relates to a preparation process of a thermoelectric separation circuit board, belonging to the technical field of circuit board preparation, and comprising the following steps: Pretreatment of the copper substrate: cutting the material, drilling holes, then performing inner layer pattern transfer, inner layer etching, after which convex copper blocks are formed on the copper substrate, stripping the film, inner layer etching inspection, inner layer oxidation; Pretreatment of the FR-4 core board: cutting the material, drilling holes, inner layer pattern transfer, etching away the areas of the bottom copper foil and the surface copper foil corresponding to the convex copper blocks, and not stripping the film after etching, inner layer etching inspection, and then routing out the areas corresponding to the convex copper blocks; Pretreatment of the PP board: cutting, drilling holes, routing out the areas corresponding to the convex copper blocks; Overlapping the FR4 substrate, the PP sheet, and the copper substrate from top to bottom in a rivet positioning manner, pressing, stripping the dry film on the surface of the FR-4 core board, drilling holes, and grinding away the resin overflowing onto the board surface. The present application has the effect of improving the heat conduction and heat dissipation efficiency and processing accuracy of the circuit board.

Description

Technical Field

[0001] This application relates to the technical field of printed circuit board manufacturing processes, and particularly to a preparation process for a thermoelectric separation printed circuit board. Background Art

[0002] As a new generation of solid-state light sources, light-emitting diodes (LEDs) have many advantages such as long lifespan, high energy efficiency, and environmental friendliness, and are widely used in lighting sources. During the light-emitting process, LEDs continuously generate heat. If effective heat dissipation cannot be achieved, the internal temperature of the LEDs will increase, resulting in a decrease in the luminous efficiency of the LEDs, shortening of the lifespan of the LEDs, and even failure of the LED wafers.

[0003] Currently, thermoelectric separation technology is often used to improve the heat dissipation efficiency of LEDs. Heat refers to the heat-conducting pads on the LED board, and electricity refers to the electrodes on the LED board. The function of the heat-conducting pads is to conduct heat, and the role of the electrodes is to conduct electricity. The two are isolated by insulating materials, achieving thermoelectric separation of the LEDs. Thermoelectric separation printed circuit boards usually have a copper substrate provided at the bottom of the printed circuit board, with convex copper provided on the copper substrate. The heat-conducting pads are connected to the convex copper, and the heat generated by the LEDs is transferred to the copper substrate through the convex copper, and heat dissipation is carried out through the copper substrate; the electrodes of the LEDs are electrically connected to the copper layer on which the outer layer circuit is etched on the printed circuit board.

[0004] The production process of thermoelectric separation printed circuit boards is relatively complex. The processing accuracy of the printed circuit boards will be affected by various process flows, and the common processing accuracy of printed circuit boards is limited, resulting in limited conductive or heat-conducting performance of the finished printed circuit boards, and even possibly reducing the luminous efficiency of the LEDs. Therefore, improvement is needed. Summary of the Invention

[0005] In order to improve the processing accuracy of thermoelectric separation printed circuit boards, this application provides a preparation process for a thermoelectric separation printed circuit board.

[0006] The preparation process for a thermoelectric separation printed circuit board provided by this application adopts the following technical solutions:

[0007] A preparation process for a thermoelectric separation printed circuit board includes the following steps:

[0008] Copper substrate pretreatment: cutting the material, drilling holes, then performing inner layer pattern transfer, inner layer etching. After etching, convex copper blocks are formed on the copper substrate, stripping the film, inner layer etching inspection, inner layer oxidation;

[0009] FR-4 core board pretreatment: cutting the material, drilling holes, inner layer pattern transfer, etching away the bottom copper foil and the area of the surface copper foil corresponding to the convex copper blocks, and not stripping the film after etching, inner layer etching inspection, and then routing out the area corresponding to the convex copper blocks;

[0010] PP board pretreatment: cutting, drilling holes, routing out the area corresponding to the convex copper blocks;

[0011] Adopt the rivet positioning method to overlap, laminate, and then strip the dry film on the surface layer of the FR-4 core board, drill holes, and grind the resin overflowing onto the board surface in sequence from top to bottom for the FR-4 core board, PP board, and copper substrate.

[0012] By adopting the above technical solution, the conductive electrode of the electronic component is electrically connected to the FR-4 core board, and the surface copper foil of the FR-4 core board conducts electricity, realizing the conductive function of the circuit board; the heat-conducting pad of the electronic component is connected to the convex copper block, and the convex copper block transfers heat to the copper substrate, and the high heat-conducting and heat-dissipating performance of the copper substrate realizes the heat-dissipating function of the circuit board; the electrical insulation performance and low heat-conducting performance of the PP board separate the conductive function of the FR-4 core board and the heat-conducting and heat-dissipating function of the copper substrate, thereby enabling the circuit board to achieve thermoelectric separation, improving the heat-dissipating efficiency of the electronic component, and reducing the possibility of affecting the working efficiency of the electronic component due to excessive heat.

[0013] In the pretreatment of the copper substrate, after the inner layer pattern transfer of the copper substrate, an image area covered by the anti-corrosion dry film is formed. After the inner layer etching, the area not covered by the dry film is etched away, and the area covered by the dry film protrudes from the surface of the copper substrate to form a convex copper block.

[0014] In the pretreatment of the FR-4 core board, first etch away the copper foil area corresponding to the convex copper block on the surface layer, and then perform grooving, which can effectively reduce the possibility of burrs generated by milling off the copper foil layer first during the grooving process, and further improve the grooving accuracy of the FR-4 core board; after the FR-4 core board is etched, the dry film is not stripped, and the remaining dry film plays a protective role for the FR-4 core board during the subsequent production and processing, effectively reducing the possibility of the board surface of the FR-4 core board being contaminated by impurities during the production and processing, and improving the processing accuracy of the FR-4 core board.

[0015] Preferably, the FR-4 core board is a double-sided copper core board, with copper foil layers on both the bottom layer and the surface layer, and the layer thickness of each layer is 2.0OZ; the intermediate layer is an insulating layer with a layer thickness of 0.05mm.

[0016] By adopting the above technical solution, the two copper foil layers provide double-sided protection for the insulating layer, while increasing the thickness of the FR-4 core board, reducing the possibility of the incoming FR-4 core board being in a rolled state, and also reducing the possibility of jamming the board during transportation.

[0017] Preferably, in the FR-4 pretreatment step, the grooving step includes: overlapping 8-12 FR-4 core boards into a group, placing a group of FR-4 core boards flat between two wood pulp boards, and then performing grooving, and the grooving size is 0.15mm larger than the single side of the convex copper block.

[0018] By adopting the above technical solution, the processing efficiency of the FR-4 core board is improved. The two-layer wood pulp board provides a protective effect for the FR-4 core board, reducing the possibility of the surface of the FR-4 core board being scratched during the grooving process.

[0019] In a specific feasible embodiment, in the pretreatment of the PP board, the step of drilling holes includes: overlapping 8-10 PP boards as a group, placing a group of PP boards flat between two wood pulp boards, and then performing board drilling, and the drilling hole size is 0.10 mm larger than the single side of the convex copper block.

[0020] By adopting the above technical solution, the processing efficiency of the PP board is improved. The two-layer wood pulp board provides a protective effect for the PP board, reducing the possibility of the surface of the PP board being scratched during the grooving process.

[0021] Preferably, the thickness of the convex copper block is 0.17-0.19 mm.

[0022] Preferably, each inner layer pattern transfer step includes film pasting, exposure, and development; the developer in the development step includes the following components in parts by mass:

[0023] Alkaline compound 0.1-5 parts, solvent 90-100 parts, polyether-modified polysiloxane 0.1-4 parts, sodium dodecylbenzenesulfonate 0.1-2 parts, betaine-type surfactant 0.1-2 parts.

[0024] By adopting the above technical solution, the dry film is attached to the surface of the copper substrate or the FR-4 core board. The dry film in the exposed area undergoes a polymerization reaction under the action of ultraviolet light to form an anti-corrosion layer; the alkaline compound in the developer reacts with the acidic active groups in the dry film in the unexposed area to generate soluble organic polymer salts, thereby removing the dry film in the unexposed area, while the dry film in the exposed area does not react with the developer. Therefore, an anti-corrosion pattern will be formed after development;

[0025] The betaine-type surfactant can effectively reduce the surface tension of the developer, enabling the developer to quickly spread onto the dry film layer, improving the uniformity of development, and being beneficial to improving the formation accuracy of the anti-corrosion pattern; there is an electrostatic attraction between the positive charge carried by the hydrophilic group of the betaine-type surfactant and the negative charge carried by the hydrophilic group of sodium dodecylbenzenesulfonate. The interaction between the two enhances the surface activity of the developer, further promoting the uniform spreading of the developer; under the electrostatic attraction of the hydrophilic groups of the two, the hydrophobic groups of the betaine surfactant and the hydrophobic groups of sodium dodecylbenzenesulfonate approach each other to form mixed micelles. When too much organic polymer salt is generated by the reaction of the alkaline compound with the dry film active groups, the organic polymer salt will precipitate, while the mixed micelles can encapsulate the organic polymer salt, improving the solubility of the organic polymer salt and reducing the possibility of the organic polymer salt precipitating on the surface of the copper substrate or the FR-4 core board and affecting the subsequent processing accuracy;

[0026] While the polyether-modified polysiloxane has better surface activity, it also has excellent foam stabilizing and defoaming properties, and can effectively reduce the foam generated when the betaine-type surfactant and sodium dodecylbenzenesulfonate act, which is beneficial to reducing the influence of foam on development, further improving the uniformity of development, being beneficial to improving the edge fineness of the anti-etching pattern, and then being beneficial to improving the accuracy of the etching edge during the subsequent inner layer etching step.

[0027] Preferably, the betaine-type surfactant is selected from one or a combination of more of lauramidopropyl betaine, oleic acid amide carboxy betaine, and dodecyl ethoxysulfobetaine.

[0028] Preferably, the alkaline compound is selected from one or a combination of more of sodium carbonate, potassium carbonate, sodium bicarbonate, potassium bicarbonate, sodium hydroxide, potassium hydroxide, triethylamine, diethylamine, and diethanolamine.

[0029] Preferably, the preparation method of the developer includes the following steps:

[0030] According to the ratio, dissolve the alkaline compound, polyether-modified polysiloxane, sodium dodecylbenzenesulfonate, and betaine-type surfactant in a solvent, and mix evenly to obtain a developer.

[0031] In a specific feasible embodiment, in the assembly and lamination step, after grinding and removing the resin overflowing onto the board surface, it further includes AOI, etching inspection, sandblasting, solder mask printing, solder mask pre-baking, solder mask exposure, solder mask development, solder mask post-baking, text, punching, testing, immersion gold plating, routing, FQA, and packaging.

[0032] By adopting the above technical solution, a finished thermoelectric separation circuit board is produced.

[0033] In summary, the present application has the following beneficial technical effects:

[0034] 1. In the pretreatment step of the FR-4 core board of the present application, first etch and remove the copper foil area corresponding to the protruding copper block on the surface layer, and then perform routing, which can effectively avoid the possibility of burrs generated by first milling off the copper foil layer during the routing process; after the FR-4 core board is etched, the dry film is not removed, and the remaining dry film plays a protective role for the FR-4 core board during the subsequent production and processing process, effectively reducing the possibility of impurities contaminating the board surface of the FR-4 core board during the production and processing process;

[0035] 2. In the inner layer image transfer step of this application, the betaine surfactant in the developer can effectively reduce the surface tension of the developer, enabling the developer to quickly spread onto the dry film layer and improving the uniformity of development; there is an electrostatic attraction between the positive charge carried by the hydrophilic group of the betaine surfactant and the negative charge carried by the hydrophilic group of sodium dodecylbenzenesulfonate, and the interaction between the two enhances the surface activity of the developer, further promoting the uniform spreading of the developer; while polyether-modified polysiloxane has good surface activity, it also has excellent foam stabilizing and defoaming properties, which can effectively reduce the foam generated when the betaine surfactant and sodium dodecylbenzenesulfonate act, facilitating the reduction of the impact of foam on development, further improving the uniformity of development, being conducive to improving the edge fineness of the anti-etching pattern, and thus being conducive to improving the precision of the etching edge during the subsequent inner layer etching step;

[0036] 3. For the circuit board prepared by using the preparation process of this application, the FR-4 core board is electrically connected to the conductive electrode of the electronic component, and the surface copper foil of the FR-4 core board conducts electricity, realizing the conductive function of the circuit board; the convex copper block contacts the heat dissipation part of the electronic component and transfers heat to the copper substrate, and the high thermal conductivity and heat dissipation performance of the copper substrate realize the heat dissipation function of the circuit board; the electrical insulation performance and low thermal conductivity of the PP board separate the conductive function of the FR-4 core board and the heat conduction and heat dissipation function of the copper substrate, thereby enabling the circuit board to achieve thermal and electrical separation, improving the heat dissipation efficiency of the electronic component, and reducing the possibility of affecting the working efficiency of the electronic component due to excessive heat. Brief Description of the Drawings

[0037] Figure 1 is a flowchart of the preparation process of a thermoelectric separation circuit board according to an embodiment of this application;

[0038] Figure 2 is a schematic cross-sectional view of the thermoelectric separation circuit board prepared in Embodiment 1 of this application.

[0039] Description of the Reference Numerals:

[0040] 1. Copper substrate; 11. Convex copper block; 2. FR-4 core board; 21. Insulating layer; 22. Surface copper layer; 3. PP board. Detailed Description of the Embodiment

[0041] The following further describes this application in detail with reference to the drawings and embodiments.

[0042] Embodiment

[0043] Embodiment 1

[0044] This embodiment discloses a preparation process of a thermoelectric separation circuit board.

[0045] Refer to Figure 1 and Figure 2, the preparation process of the thermoelectric separation circuit board includes the following steps:

[0046] The first step:

[0047] (1) Pretreatment of the copper substrate:

[0048] Cutting the copper substrate 1 into the required size by means of routing;

[0049] Drilling, respectively drilling rivet holes, second-drill positioning holes and other tool holes on the copper substrate 1;

[0050] Inner layer pattern transfer, dry film is attached to both sides of the copper substrate 1, and then subjected to film exposure. The dry film in the exposed area undergoes a polymerization reaction under ultraviolet irradiation and has corrosion resistance after polymerization; then developed with a commercially available developer. The dry film in the unexposed area reacts with the alkaline compounds in the developer to form soluble substances and is removed, while the dry film in the exposed area does not react with the developer and remains on the copper substrate 1 to form an anti-corrosion pattern; in this embodiment, the model of the developer is RS-666.

[0051] Inner layer etching, the area not covered by the anti-corrosion pattern is etched and thinned, while the area covered by the anti-corrosion pattern is not etched, forming a convex copper block 11. The thickness range of the convex copper block 11 is 0.17 - 0.19 mm. In this embodiment, the thickness of the convex copper block 11 is 0.18 mm; after etching, the dry film on the convex copper block 11 is removed;

[0052] Inner layer etching inspection, checking for etching defect points;

[0053] Inner layer oxidation, performing brown oxidation on the surface of the copper substrate 1 to increase the surface area of the copper substrate 1 and improve the adhesion.

[0054] (2) Pretreatment of the FR-4 core board:

[0055] Cutting, selecting a double-sided copper core board as the FR-4 core board 2, with the thickness of the middle insulating layer 21 being 0.05 mm, and the copper thickness of both the bottom copper layer and the surface copper layer 22 being 2.0 OZ, cutting the FR-4 core board 2 into the required size;

[0056] Drilling, drilling exposure alignment holes on the FR-4 core board 2;

[0057] Inner layer pattern transfer, attaching dry film to the surface of the FR-4 core board 2, then exposing, developing, and removing the dry film in the area corresponding to the convex copper block 11;

[0058] Inner layer etching, etching off the bottom copper layer and the area of the surface copper layer 22 corresponding to the convex copper block 11, and not removing the surface dry film after etching;

[0059] Inner layer etching inspection, checking for etching defect points;

[0060] Inner-grooving of the core board: Overlap 10 FR-4 core boards 2 as a group and place them flat between two wood pulp boards. Drill rivet holes corresponding to the copper substrate 1, and mill out the area corresponding to the second-drill positioning holes and the convex copper blocks 11 on the copper substrate 1. The size of the milled-out area is 0.15 mm larger than the size of the second-drill positioning holes or the convex copper blocks 11 on each side.

[0061] (3) Pretreatment of the PP board:

[0062] Cutting: Cut the PP board 3 into the required size. In this embodiment, pp1080 is selected for the PP board 3.

[0063] Drilling: Drill forming positioning holes in the PP board 3.

[0064] Inner-grooving of the PP board: Overlap 8 PP boards 3 as a group and place them flat between two wood pulp boards. Drill rivet holes corresponding to the copper substrate 1, and mill out the area corresponding to the second-drill positioning holes on the copper substrate 1. The size of the milled-out area is 0.15 mm larger than the size of the second-drill positioning holes on each side; mill out the area corresponding to the convex copper blocks 11, and the size of the milled-out area is 0.10 mm larger than the size of the second-drill positioning holes on each side.

[0065] The second step:

[0066] Refer to Figure 2 , and overlap, press, and laminate the FR-4 core board 2, the PP board 3, and the copper substrate 1 from top to bottom in the way of rivet positioning. Use acid etching to remove the dry film on the surface layer of the FR-4 core board 2.

[0067] Second drilling: Use the second-drill positioning holes for positioning and drill out each tool hole.

[0068] Board grinding: Grind and remove the resin that overflows from the PP board 3 onto the board surface.

[0069] Then, through measurement of expansion and contraction → outer layer circuit → board repair → acid etching → AOI → etching inspection → sandblasting → solder mask printing → solder mask pre-baking → solder mask exposure → solder mask development → solder mask post-baking → lettering → punching → testing → immersion gold → board milling → FQA → packaging, the thermoelectric separation circuit board is obtained.

[0070] Example 2

[0071] The difference between this embodiment and Example 1 is only that the developer used in the developing step includes the following components by mass: 20 g of alkaline compound, 950 g of solvent, 25 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate, and 15 g of betaine-type surfactant.

[0072] In this embodiment, sodium carbonate is selected as the alkaline compound, water is used as the solvent, and lauramidopropyl betaine is selected as the betaine-type surfactant.

[0073] The preparation method of the developer includes the following steps:

[0074] Dissolve the above-mentioned masses of sodium carbonate, polyether-modified polysiloxane, sodium dodecylbenzenesulfonate, and betaine-type surfactant in water, and stir evenly to obtain the developer.

[0075] Example 3

[0076] The difference between this example and Example 2 is only that the developer includes the following components in the following masses:

[0077] Alkaline compound 20 g, solvent 950 g, polyether-modified polysiloxane 30 g, betaine-type surfactant 15 g.

[0078] Example 4

[0079] The difference between this example and Example 2 is only that the developer includes the following components in the following masses:

[0080] Alkaline compound 20 g, solvent 950 g, polyether-modified polysiloxane 30 g, sodium dodecylbenzenesulfonate 0.1 g, betaine-type surfactant 15 g.

[0081] Example 5

[0082] The difference between this example and Example 2 is only that the developer includes the following components in the following masses:

[0083] Alkaline compound 20 g, solvent 950 g, polyether-modified polysiloxane 30 g, sodium dodecylbenzenesulfonate 10 g, betaine-type surfactant 15 g.

[0084] Example 6

[0085] The difference between this example and Example 2 is only that the developer includes the following components in the following masses:

[0086] Alkaline compound 20 g, solvent 950 g, polyether-modified polysiloxane 30 g, sodium dodecylbenzenesulfonate 20 g, betaine-type surfactant 15 g.

[0087] Example 7

[0088] The difference between this example and Example 2 is only that the developer includes the following components in the following masses:

[0089] Alkaline compound 20 g, solvent 950 g, polyether-modified polysiloxane 30 g, sodium dodecylbenzenesulfonate 25 g, betaine-type surfactant 15 g.

[0090] Example 8

[0091] The difference between this example and Example 2 is only that the developer includes the following components in the following masses:

[0092] 20 g of alkaline compound, 950 g of solvent, 30 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate.

[0093] Example 9

[0094] The difference between this example and Example 2 is only that the developer solution comprises the following components by mass:

[0095] 20 g of alkaline compound, 950 g of solvent, 30 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate, 0.1 g of betaine surfactant.

[0096] Example 10

[0097] The difference between this example and Example 2 is only that the developer solution comprises the following components by mass:

[0098] 20 g of alkaline compound, 950 g of solvent, 30 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate, 10 g of betaine surfactant.

[0099] Example 11

[0100] The difference between this example and Example 2 is only that the developer solution comprises the following components by mass:

[0101] 20 g of alkaline compound, 950 g of solvent, 30 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate, 20 g of betaine surfactant.

[0102] Example 12

[0103] The difference between this example and Example 2 is only that the developer solution comprises the following components by mass:

[0104] 20 g of alkaline compound, 950 g of solvent, 30 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate, 25 g of betaine surfactant.

[0105] Example 13

[0106] 20 g of alkaline compound, 950 g of solvent, 15 g of sodium dodecylbenzenesulfonate, 15 g of betaine surfactant.

[0107] Example 14

[0108] The difference between this example and Example 2 is only that the developer solution comprises the following components by mass:

[0109] 20 g of alkaline compound, 950 g of solvent, 0.1 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate, 15 g of betaine surfactant.

[0110] Example 15

[0111] The difference between this example and Example 2 is only that the developer includes the following components by mass:

[0112] 20 g of alkaline compound, 950 g of solvent, 40 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate, and 15 g of betaine-type surfactant.

[0113] Example 16

[0114] The difference between this example and Example 2 is only that the developer includes the following components by mass:

[0115] 20 g of alkaline compound, 950 g of solvent, 45 g of polyether-modified polysiloxane, 15 g of sodium dodecylbenzenesulfonate, and 15 g of betaine-type surfactant.

[0116] Performance detection test

[0117] Select the developers in Examples 2-13 and conduct the following tests:

[0118] Test 1: Perform film pressing on a transparent glass substrate (100 mm × 100 mm), conduct film exposure, take the developers of Examples 2-13, dilute them to 100 times respectively and then develop, clean the glass substrate after development, air dry it, observe the resist pattern through a microscope, confirm the integrity and missing degree of the resist pattern, and classify each example into levels 1-5, where level 1 indicates good pattern integrity and no missing, and level 5 indicates poor pattern integrity and excessive missing;

[0119] Test 2: After development, observe the amount of solid residue on the glass substrate in the area not covered with the resist pattern through a microscope, and classify each example into levels 1-5, where level 1 indicates no solid residue and level 5 indicates excessive solid residue;

[0120] Test 3: Take the developers of Examples 2-13, dilute them 100 times respectively, take 10 ml and add it to a volumetric flask, shake for 5 min, and classify each example into levels 1-5 according to the volume of the generated foam, where level 1 indicates less foam and level 5 indicates excessive foam.

[0121] The test results are summarized in Table 1.

[0122]

[0123]

[0124] Combined with Example 2, Example 3, Example 8, and Example 13, and in combination with Table 1, it is shown that preferably using the developer disclosed in the present application can ensure the integrity of the resist pattern, while having a small amount of solid residue, effectively avoiding the influence of solid residues on the copper substrate or FR-4 core board, and having a small amount of foam; the synergistic cooperation of sodium dodecylbenzenesulfonate and betaine-type surfactant can improve the surface activity of the developer, improve the integrity of the resist pattern, and reduce the residue of solids. Polyether-modified polysiloxane can effectively reduce the generation of foam, reduce the influence of foam on development, and ensure the integrity of the resist pattern.

[0125] Combined with Example 2, Examples 4-6, and in combination with Table 1, it can be seen that increasing the addition amount of sodium dodecylbenzenesulfonate within the scope disclosed in the present application can improve the integrity of the resist pattern and reduce the solid residue, while also increasing the amount of foam generated; combined with Example 7, when the addition amount of sodium dodecylbenzenesulfonate is too much, more foam is generated, reducing the development effect and the integrity of the resist pattern.

[0126] Combined with Example 2, Examples 9-12, and in combination with Table 1, it can be seen that increasing the addition amount of betaine-type surfactant within the scope disclosed in the present application can improve the integrity of the resist pattern and reduce the solid residue, and the amount of foam generated will increase accordingly. Combined with Example 13, when there is too much betaine-type surfactant, more foam is generated, reducing the integrity of the resist pattern.

[0127] Combined with Example 2, Examples 14-15, and in combination with Table 1, it can be seen that adding polyether-modified polysiloxane can effectively reduce the generation of foam. Combined with Example 16, when too much polyether-modified polysiloxane is added, the integrity of the resist pattern will be reduced, which may be because too much polyether-modified polysiloxane reduces the surface activity of the developer, thereby resulting in poor spreading of the developer and reducing the integrity of the resist pattern.

[0128] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereby. Therefore, all equivalent changes made according to the structure, shape, and principle of the present application should be covered within the protection scope of the present application.

Claims

1. A preparation process of a thermoelectric separation circuit board, characterized in that: It includes the following steps: Pretreatment of copper substrate: cutting the blank, drilling, then performing inner layer pattern transfer, inner layer etching, after which convex copper blocks are formed on the copper substrate, inner layer etching inspection, inner layer oxidation; Pretreatment of FR-4 core board: cutting the blank, drilling, inner layer pattern transfer, etching away the bottom copper foil and the area of the surface copper foil corresponding to the convex copper blocks, and not removing the film after etching, inner layer etching inspection, then routing out the area corresponding to the convex copper blocks; and the routing size is 0.15 mm larger than the single side of the convex copper block; Pretreatment of PP board: cutting, drilling, routing out the area corresponding to the convex copper blocks; and the routing size is 0.10 mm larger than the single side of the convex copper block; Adopting the rivet positioning method, overlapping the FR-4 core board, PP board, and copper substrate from top to bottom in sequence, pressing, removing the dry film on the surface layer of the FR-4 core board, drilling, and grinding to remove the resin overflowing onto the board surface; Each step of the inner layer pattern transfer step includes film pasting, exposure, and development; The developer in the development step is composed of the following components in parts by mass: 0.1 - 5 parts of alkaline compound, 90 - 100 parts of solvent, 0.1 - 4 parts of polyether modified polysiloxane, 0.1 - 2 parts of sodium dodecylbenzenesulfonate, 0.1 - 2 parts of betaine type surfactant.

2. The preparation process of the thermoelectric separation circuit board according to claim 1, wherein: The FR-4 core board is a double-sided copper core board, with copper foil layers on both the bottom and surface layers, and the layer thickness of each layer is 2.0 OZ; the intermediate layer is an insulating layer with a layer thickness of 0.05 mm.

3. The preparation process of the thermoelectric separation circuit board according to claim 1, characterized in that: In the FR-4 pretreatment step, the routing step includes: overlapping 8 - 12 FR-4 core boards into a group, placing a group of FR-4 core boards flat between two wood pulp boards, and then performing routing.

4. The preparation process of the thermoelectric separation circuit board according to claim 1, characterized in that: In the PP board pretreatment, the routing step includes: overlapping 8 - 10 PP boards into a group, placing a group of PP boards flat between two wood pulp boards, and then performing routing.

5. The preparation process of the thermoelectric separation circuit board according to claim 1, wherein: The thickness of the convex copper block is 0.17 - 0.19 mm.

6. The preparation process of the thermoelectric separation circuit board according to claim 1, characterized in that: The betaine type surfactant is selected from one or a combination of more than one of lauramidopropyl betaine, oleic acid amide carboxy betaine, and dodecyl ethoxysulfobetaine.

7. The preparation process of the thermoelectric separation circuit board according to claim 1, characterized in that: The alkaline compound is selected from one or a combination of more than one of sodium carbonate, potassium carbonate, sodium bicarbonate, potassium bicarbonate, sodium hydroxide, potassium hydroxide, triethylamine, diethylamine, and diethanolamine.

8. The preparation process of the thermoelectric separation circuit board according to claim 1, characterized in that: The preparation method of the developer includes the following steps: according to the ratio, dissolving the alkaline compound, polyether modified polysiloxane, sodium dodecylbenzenesulfonate, and betaine type surfactant in the solvent, and mixing evenly to obtain the developer.

9. The preparation process of the thermoelectric separation circuit board according to claim 1, characterized in that: In the assembly and pressing step, after grinding to remove the resin overflowing onto the board surface, it also includes AOI, etching inspection, sandblasting, solder mask printing, solder mask pre-baking, solder mask exposure, solder mask development, solder mask post-baking, lettering, punching, testing, immersion gold plating, routing, FQA, and packaging.

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