Memory device and method of manufacturing the same

Abstract

This application relates to a memory device and a method of manufacturing the same. A vertical 3D memory device may include: a plurality of contacts associated with a plurality of digital lines and extending through a substrate; a plurality of word line plates separated from each other by respective dielectric layers and including first and second pluralities of word line plates; a dielectric material positioned between the first plurality and the second plurality of word line plates, the dielectric material extending in a serpentine shape over the substrate; a plurality of pillars formed over the plurality of contacts and coupled to the plurality of contacts; and a plurality of memory elements, each including a chalcogenide material positioned in a recess having an arch shape between a respective word line plate and a respective pillar, wherein the chalcogenide material in the recess contacts the respective word line plate.

Description

[0001] Cross - Reference

[0002] This patent application is a national stage application of International Patent Application No. PCT / IB2020 / 020042, titled "MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME", filed by Fratin et al. on July 22, 2020, and assigned to its assignee, and the entire content of the application is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] This technical field relates to a memory device and a method for manufacturing the same. BACKGROUND ART

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like.

[0005] Information is stored by programming different states of the memory device. For example, binary devices most commonly store one of two states, which are typically represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program a state into the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), other chalcogenide-based memories, and other memory devices. Memory devices can be volatile or non-volatile.

[0007] Improving memory devices generally can include increasing memory cell density, increasing read / write speed, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing cost, among other metrics. Solutions may be needed to save space in a memory array, increase memory cell density, or reduce the total power usage of a memory array having a three-dimensional vertical architecture. SUMMARY OF THE INVENTION

[0008] Describe a vertical 3D memory device. The vertical 3D memory device may include: a plurality of contacts associated with a plurality of digital lines and extending through a substrate; a plurality of word line plates separated from each other by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a dielectric material positioned between the first plurality of word line plates and the second plurality of word line plates, the dielectric material extending over the substrate in a serpentine shape; a plurality of pillars formed over the plurality of contacts and coupled to the plurality of contacts; and a plurality of memory elements, each including a chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, wherein the recess has an arch shape, and the chalcogenide material in the recess contacts the respective word line plate at a middle portion of the recess and contacts the respective pillar at a bottom portion of the recess.

[0009] Describe a method of manufacturing a vertical 3D memory array. The method of manufacturing the vertical 3D memory array may include: forming a plurality of conductive contacts extending through a substrate, each associated with a respective one of a plurality of digital lines; forming a plurality of conductive layers separated from each other by respective ones of a plurality of dielectric layers, the plurality of conductive layers configured as word lines; forming a trench through the plurality of conductive layers and the plurality of dielectric layers, the trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines; depositing a dielectric material in the trench; forming a plurality of openings by etching a portion of the dielectric material, each opening over a respective contact and exposing the respective contact; forming a plurality of recesses in the plurality of openings in a plurality of planes in which the plurality of conductive layers are located; forming a chalcogenide material in the plurality of recesses; and forming a plurality of conductive pillars, each conductive pillar in a respective one of the plurality of openings and contacting the chalcogenide material formed in a respective one of the plurality of recesses, the plurality of conductive pillars configured as digital lines, wherein each of the plurality of recesses has an arch shape and is between a respective word line and a respective digital line, and the chalcogenide material in the recess contacts the respective word line at a middle portion of the recess and contacts the respective digital line at a bottom portion of the recess.

[0010] Describe a method of manufacturing a vertical 3D memory array. The method of manufacturing the vertical 3D memory array may include: forming a trench through a plurality of conductive layers and a plurality of dielectric layers of the 3D memory array, the trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines; depositing a dielectric material in the trench; forming a plurality of openings by etching a portion of the dielectric material, each opening exposing the substrate; forming a plurality of recesses in the plurality of openings in a plurality of planes in which the plurality of conductive layers are located; and forming a chalcogenide material in the plurality of recesses, wherein each of the plurality of recesses has an arch shape, and the chalcogenide material in the recess contacts a respective word line at a crown of the recess. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Illustrate an example of a vertical 3D memory array according to an example disclosed herein.

[0012] Figure 2A Illustrate a bottom view of an example 3D memory array according to an example disclosed herein.

[0013] Figure 2B Illustrate a side view of an example 3D memory array according to an example disclosed herein.

[0014] Figures 3A to 3D Illustrate various views of an example 3D memory array according to an example disclosed herein.

[0015] Figure 4 Illustrate various views of an example 3D memory array according to an example disclosed herein.

[0016] Figures 5A to 5C Illustrate various views of an example 3D memory array according to an example disclosed herein.

[0017] Figure 6 Illustrate various views of an example 3D memory array according to an example disclosed herein.

[0018] Figure 7A AND 7B Illustrate various views of an example 3D memory array according to an example disclosed herein.

[0019] Figure 8 Illustrate a side view of an example 3D memory array according to an example disclosed herein.

[0020] Figure 9 Show a flowchart illustrating a method of fabricating a 3D memory array according to an example disclosed herein.

[0021] Figure 10 Show a flowchart illustrating another method of fabricating a 3D memory array according to an example disclosed herein.

[0022] Figure 11 Is a block diagram of an apparatus in the form of a memory device according to an example disclosed herein. DETAILED DESCRIPTION

[0023] The present disclosure relates to a three-dimensional (3D) vertical self-selecting memory array having increased memory cell density and compressed memory cells and a method of manufacturing the same. The memory array may include a conductive contact and an arrangement of openings through alternating layers of conductive and insulating materials, which may reduce the spacing between memory cells while maintaining a dielectric thickness to sustain a voltage applied to the memory array. The contact area between the memory element material of the memory cell and the conductive material may be reduced because the memory element is formed in an arched recess, where an intermediate portion (e.g., the apex) contacts the conductive material.

[0024] In some examples, the 3D memory array may include a substrate having a plurality of contacts arranged in a pattern (e.g., a geometric pattern) and a first insulating material formed on the substrate. A plurality of planes of conductive material may be separated from each other by a second insulating material and formed on the substrate material. The planes of conductive material may be examples of word lines.

[0025] During manufacture of this memory array, trenches may be formed to separate odd and even WL line planes to produce a shape of a "comb" structure (e.g., a structure of a tool that appears to have fingers and spaces between the fingers). The trenches may have any geometric configuration and include groups of odd and even fingers of the comb facing each other at a fixed distance. In some examples, the trenches may be formed in a serpentine shape. The trenches may divide each plane of the conductive material into two sections or two plates. Each location of the conductive material may be an example of a word line plate. In some examples, inside the trenches, the planes of the conductive material may be etched in a way that multiple grooves are formed with an insulating material and the conductive material, where each groove may be configured to receive a memory element material (e.g., a chalcogenide material). A dielectric material may be deposited in the trenches, and in some cases, the dielectric material may fill the grooves. The dielectric material may form a serpentine shape. In some examples, other geometric configurations of the trenches are considered.

[0026] Portions of the dielectric material may be removed by an etching process (e.g., a dry etching process) to form openings. The openings may expose portions of the substrate, the plurality of conductive contacts, and portions of the conductive and insulating materials. In some examples, the openings may be formed in an oval shape. In some examples, other geometric configurations of the openings are considered. For example, rectangular openings may be formed. In some examples, the walls of the dielectric material may be exposed in the openings. Another etching process (e.g., an isotropic wet etching process) may be performed to enlarge the openings in each plane of the conductive material such that the enlarged openings are tangent to the conductive material (with a certain excess tolerance). A memory element material (e.g., a chalcogenide material) may be deposited in the enlarged openings. The memory element material may be removed from portions of the openings such that only the memory element material in the arched recesses is retained. In some examples, each of the arched recesses may be formed by the conductive material, the dielectric material, and the insulating material.

[0027] The conductive pillars can be formed in the openings containing the memory element material in the arched recesses. In some examples, the memory element material can contact the conductive material at the middle (e.g., the vault) of the arched recess and contact the conductive pillars at the bottom (e.g., the wider bottom) of the arched recess. In some examples, the memory element material can contact the dielectric material at the opposite sides of the arched recess between the middle and the bottom. The conductive pillars can be examples of digital lines. The conductive pillars can be arranged to extend into (e.g., generally perpendicular to) the plane of the conductive material and the substrate. Each conductive pillar can be coupled to a different conductive contact. The pillars can be formed of a barrier material and a conductive material.

[0028] Alternatively, in some examples, before depositing the dielectric material in the trenches, a sacrificial layer (e.g., a conformal material) can be deposited in the trenches and in some cases, the sacrificial layer fills the grooves. In other words, the conformal material can be formed between the conductive material and the dielectric material. The conformal material and the dielectric material can form a serpentine shape.

[0029] In an example of forming the conformal material, portions of the dielectric material can be removed by an etching process (e.g., a dry etching process) to form openings. The openings can expose portions of the substrate, a plurality of conductive contacts, and portions of the conformal material and the insulating material. In some examples, the openings can be formed in an oval shape. In some examples, other geometric configurations of the openings are considered. For example, rectangular openings can be formed. In some examples, the walls of the dielectric material can be exposed in the openings. Another etching process (e.g., an isotropic wet etching process) can be performed to expand the openings in each plane of the conductive material such that portions of the conformal material are etched away and arched recesses are formed in the conformal material and between the conductive material and the dielectric material. In some examples, the arched recesses are tangent to the conductive material (with a certain excess tolerance). A memory element material (e.g., a chalcogenide material) can be deposited in the expanded openings. Portions of the memory element material can be removed from the openings such that only the memory element material in the arched recesses is retained. In some examples, each of the arched recesses can be formed by the conductive material, the conformal material, and the insulating material.

[0030] The conductive pillars can be formed in the openings containing the memory element material in the recesses. In some examples, the memory element material can contact the conductive material at the middle (e.g., the vault) of the arched recess and contact the conductive pillars at the bottom (e.g., the wider bottom) of the arched recess. In some examples, the memory element material can contact the conformal material at the opposite sides of the arched recess between the middle and the bottom. The conductive pillars can be examples of digital lines. The conductive pillars can be arranged to extend into (e.g., generally perpendicular to) the plane of the conductive material and the substrate. Each conductive pillar can be coupled to a different conductive contact. The pillars can be formed of a barrier material and a conductive material.

[0031] In some instances, the contact area between the storage element material and the conductive material can be less than the contact area between the storage element material and the conductive pillar. In some instances, the contact area between the storage element material and the conductive material can be controlled by the alignment of the conductive pillar relative to the conductive material. For example, if the average intercept / contact is 17 nm, where the conductive pillar radius is equal to 20 nm, then a + / - 1 nm fluctuation in its center can result in a + / - 4 nm fluctuation in the contact size. Appropriate over-dishing can reduce this variability and allow for better dimensional control.

[0032] In some instances, the plurality of conductive pillars formed over the plurality of contacts can interrupt the continuity of the dielectric material extending over the substrate in a serpentine shape.

[0033] Such a configuration of the memory array and the manufacturing method can allow for a higher density of memory cells and compact memory cells relative to previous solutions. Each memory cell (e.g., the storage element material) can be recessed inside the opposite sides of the conductive pillar to ensure cell isolation. Relative to some previous solutions, this configuration can allow for more stringent control of the cell thickness and size. Each plane of the conductive material intersecting the conductive pillar can form two memory cells addressed by a first word line plane in the plane and a second word line plane in the plane. Each conductive pillar can be decoded by a transistor located at the bottom or top of the memory array. The transistor can be an example of a digital line selector formed as a regular matrix.

[0034] The features of the present disclosure are initially described in the context of the background of a memory array as described in reference Figure 1 The features of the present disclosure are described in the context of the background of different views of an exemplary 3D memory array during the manufacturing steps as described in reference Figures 2A to 8 The features of the present disclosure are further illustrated and described with reference to a flowchart related to the vertical 3D memory array architecture as described in reference Figure 9 and 10 These and other features of the present disclosure are further described in the context of the background of an exemplary 3D memory device as described in reference Figure 11

[0035] Figure 1 An example of a 3D memory array 100 in accordance with aspects of the present disclosure is illustrated. The memory array 100 can include a first array or stack 105 of memory cells located over a substrate 104 and a second array or stack 108 of memory cells on top of the first array or stack 105. In some instances, the memory array 100 can have a different orientation relative to the substrate 104, such as a 90° rotation from the orientation shown in Figure 1 where the first array or stack 105 of memory cells can be positioned adjacent to the second array or stack 108 of memory cells.

[0036] The memory array 100 may include word lines 110 and digit lines 115. The memory cells of the first stack 105 and the second stack 108 may each have one or more self-selective memory cells. Although some of the elements included are labeled with numerical indicators, other corresponding elements are not labeled, but they are the same or will be understood to be similar. Figure 1 in

[0037] The memory cell stack may include a first dielectric material 120, a memory element material 125 (e.g., a chalcogenide material), a second dielectric material 130, a memory element material 135 (e.g., a chalcogenide material), and a third dielectric material 140. In some examples, the self-selective memory cells of the first stack 105 and the second stack 108 may have a common conductive line such that the corresponding self-selective memory cells of each of the stacks 105 and 108 may share the digit line 115 or the word line 110.

[0038] In some examples, the cell may be programmed by providing an electrical pulse to the memory cell that may include a memory storage element. The pulse may be provided via a first access line (e.g., word line 110) or a second access line (e.g., digit line 115) or a combination thereof. In some cases, after the pulse is provided, ions may migrate within the memory storage element depending on the polarity of the memory cell. Thus, the concentration of ions relative to the first or second side of the memory storage element may be at least partially based on the polarity of the voltage between the first access line and the second access line. In some cases, an asymmetrically shaped memory storage element may cause ions to accumulate more at the portion of the element with the larger area. A particular portion of the memory storage element may have a higher resistivity and thus may produce a threshold voltage higher than other portions of the memory storage element. This description of ion migration represents an example of the mechanism of the self-selective memory cell for achieving the results described herein. This example of the mechanism should not be considered limiting. The present disclosure also includes other examples of the mechanism of the self-selective memory cell for achieving the results described herein.

[0039] The architecture of the memory array 100 may in some cases be referred to as a vertical 3D cross-point architecture, where the memory cells are formed at the topological cross-points between the word lines 110 and the digit lines 115. Compared to other memory architectures, this cross-point architecture can provide relatively high-density data storage at a lower production cost. For example, the cross-point architecture may have memory cells with reduced area and thus increased memory cell density compared to other architectures.

[0040] Although Figure 1An example shows two memory stacks 105 and 108, but other configurations are possible. In some examples, a single memory stack of self-selecting memory cells (which may be referred to as a two-dimensional memory) can be constructed above the substrate 104. In some examples, three or four memory stacks of memory cells can be configured in a manner similar to that in a three-dimensional cross-point architecture.

[0041] The memory array 100 can include a substrate 104 having a plurality of contacts arranged in a grid or staggered pattern. In some cases, the plurality of contacts can extend through the substrate and be coupled to the access lines of the memory array 100. The memory array 100 can include a plurality of planes of conductive material separated from each other by a second insulating material on a first insulating material formed on the substrate material. Each of the plurality of planes of conductive material can include a plurality of grooves formed therein. The plurality of planes (e.g., word line plates) can be obtained by an alternative process by etching using a sacrificial layer (e.g., a conformal layer) during a stack deposition processing step; removing the conformal layer after cell definition and replacing the conformal layer with a more conductive material.

[0042] A dielectric material can be formed in a serpentine shape through the second insulating material and the conductive material. A plurality of conductive pillars can be arranged in openings to extend generally perpendicular to the plurality of planes of conductive material and the substrate. Each corresponding one of the plurality of conductive pillars can be coupled to a different one of the conductive contacts.

[0043] In some examples, the memory stacks 105 and 108 can include chalcogenide materials configured to store logic states. For example, the memory cells of the memory stacks 105 and 108 can be examples of self-selecting memory cells. The chalcogenide materials can be formed in the plurality of grooves such that the chalcogenide materials in each corresponding one of the plurality of grooves are at least partially in contact with one of the plurality of conductive pillars.

[0044] Figure 2A A bottom view of an example 3D memory array 200-a according to an example as disclosed herein is illustrated. The memory array 200-a can include a plurality of conductive contacts 235 formed in the substrate 104 and extending through the substrate 104 and coupled to the access lines of the memory array 100. For example, the substrate 104 can be a dielectric material, such as a dielectric film.

[0045] A single conductive contact of the plurality of conductive contacts 235 can be configured to couple any single vertical column to a transistor (not shown). The plurality of conductive contacts 235 can be arranged in a grid pattern. In some instances, each of the plurality of conductive contacts 235 can be surrounded by up to eight other conductive contacts 235. In some instances, the plurality of conductive contacts 235 can be arranged in a staggered pattern or a hexagonal pattern. For example, each of the plurality of conductive contacts 235 can be surrounded by up to six other conductive contacts 235.

[0046] Figure 2B FIG. 4 illustrates a side view of an example 3D memory array 200-b according to an example as disclosed herein. The memory array 200-b can include a plurality of conductive contacts 235 that can be formed in a substrate 104. The memory array 200-b can also include a plurality of stacked planes of an insulating material 240 and a plurality of stacked planes of a conductive material 245 (e.g., word line planes or word line plates). The stacked planes of the conductive material 245 can be separated from each other in the z-direction (e.g., vertically separated) by the plurality of planes of the insulating material 240. For example, a first plane (e.g., bottom plane) of a second insulating material 240 can be formed (e.g., deposited) on a plane of the substrate 104, and then a plane of the conductive material 245 can be formed on the first plane of the second insulating material 240. In some instances, a layer of a first insulating material 240 can be deposited on the substrate 104. In some instances, the conductive material 245 can be a conductive carbon layer or other conductive layer compatible with an active material. In some instances, the conductive material 245 can include conductive layers separated by a protective barrier by an active material. The conductive material 245 can be configured to function as at least one word line plate. In some instances, the conductive material 245 and the insulating material 240 form a plurality of layers, such as alternating layers.

[0047] Additional planes of the second insulating material 240 can be formed on the conductive material 245 in an alternating manner as Figure 2B illustrated. The second insulating material 240 can be a dielectric material, such as a dielectric film or layer. In some instances, the second insulating material 240 and the substrate 104 can be the same type of insulating material. Examples of insulating materials disclosed herein include (but are not limited to) dielectric materials such as silicon oxide.

[0048] Each corresponding one of the plurality of planes of the conductive material 245 can be at (e.g., form) a different level of the 3D memory array 200-b. Individual planes of the material forming the memory cells can be referred to as a stack of the 3D memory array 200-b. The conductive material 245 can include a metal (or semi-metal) material or a semiconductor material (e.g., doped polysilicon material), etc. (e.g., formed therefrom). In some instances, the conductive material 245 can be a conductive carbon plane.

[0049] Figure 2B Six planes of the conductive material 245 and seven planes of the second insulating material 240 are shown. The seventh plane of the second insulating material 240 may be the topmost layer of the 3D memory array 200-b. The number of planes of the conductive material 245 and the second insulating material 240 is not limited to Figure 2B the number described therein. The conductive material 245 and the second insulating material 240 may be arranged in more than six stacks or fewer than six stacks.

[0050] Figure 3A Shows a top view of an exemplary 3D memory array 200-c, which may be an example of the memory array 200-b described in Figure 2B after forming the trench 350. Figure 3B Describes during a process step following Figure 3A a cross-sectional view of an exemplary 3D memory array 200-d along the section line A-A′. Figure 3C Describes during a process step following Figure 3B a cross-sectional view of an exemplary 3D memory array 200-e along the section line A-A′. Figure 3D Describes during a process step following Figure 3B a top view of an exemplary 3D memory array 200-e along the section line B-B′.

[0051] Figure 3A Describes forming a trench 350 that passes through alternating planes of the conductive material 245 ( Figure 3B shown in Figure 3B ) and the second insulating material 240 ( Figure 2A shown in 2B ). The trench 350 may expose the substrate 104 (previously shown in Figure 2A and 2B ) and the conductive contact 235 (previously shown in

[0052] at the bottom of the trench 350. The trench 350 may be etched from the top to the bottom and etched into a serpentine shape. For example, the trench 350 may cross rows of the conductive contacts 235 in a first direction (e.g., from left to right) and then cross adjacent rows of the conductive contacts 235 in a second direction opposite to the first direction (e.g., from right to left). Refer to Figure 3AIn an example, the trench 350 crosses the first row of conductive contacts 235 from left to right, then "turns" and crosses the next (second) row of conductive contacts 235 (adjacent to the first row) from right to left. The trench 350 "turns" again and crosses the next (third) row of conductive contacts 235 (adjacent to the second row) from left to right. The trench 350 "turns" again and crosses the next (fourth) row of conductive contacts 235 (adjacent to the third row) from right to left and then "turns" again and crosses Figure 3A the next (fifth) row of conductive contacts 235 (adjacent to the fourth row) at the bottom of

[0053] The trench 350 may bifurcate each plane of the conductive material 245 into at least two parts: a first part 308 and a second part 309. Each part of the plane of the conductive material 245 may be different access lines of a stack (e.g., even digit lines or odd digit lines). For example, the first part 308 may be the first access line of a stack of the 3D memory array 200-c and the second part 309 may be the second access line of the same stack of the 3D memory array 200-c. The extension of the fingers forming the even or odd planes may be defined based on the resistivity of the electrodes used and the level of current delivery requested. Specifically, the depth of the grooves is defined depending on the thickness required for the memory cells.

[0054] Figure 3B Illustrates forming a plurality of grooves 315 in the conductive material 245 in each of the planes of the memory array 200-d. For example, a selective etching operation may be performed to form a plurality of grooves 315 in an isotropic manner in the sidewalls 390 and 391 of the trench 350. In some examples, the trench 350 includes a first sidewall 390 spaced apart from a second sidewall 391, where a first part 392 of the first sidewall 390 formed of the first insulating material 240 is spaced apart from a first part 393 of the second sidewall 391 formed of the first insulating material 240 by a first distance. A second part 394 of the first sidewall 390 formed of the first conductive material 245 may be spaced apart from a second part 396 of the second sidewall 391 formed of the first conductive material 245 by a second distance greater than the first distance. In some examples, the portions of the sidewalls 390 and 391 of the trench 350 formed of the first conductive material 245 are recessed relative to the portions of the sidewalls 390 and 391 of the trench 350 formed of the first insulating material 240.

[0055] The etching operation may include one or more vertical etching processes (e.g., an anisotropic etching process or a dry etching process or a combination thereof) or a horizontal etching process (e.g., an isotropic etching process) or a combination thereof. For example, a vertical etching process may be performed to vertically etch the trench 350 and a horizontal etching process may be used to form at least one recess 315 in at least one conductive material 245. The etching parameters may be selected such that, for example, the conductive material 245 is etched faster than the second insulating material 240.

[0056] Figure 3C Illustrate depositing a dielectric material 318 in the trench 350. The dielectric material 318 may contact the sidewalls of the trench 350. The dielectric material 318 may fill the trench 350. In some cases, the dielectric material 318 may be an example of an insulating material.

[0057] Figure 3D Illustrate a top view of an example 3D memory array 200-e after depositing the dielectric material 318 as shown in Figure 3C In Figure 3D the dielectric material 318 formed in the trench 350 bifurcates each plane of the conductive material 245 into a first portion 308 and a second portion 309.

[0058] Figure 4 Illustrate Figure 3D various partial views of the example 3D memory array 200-e shown in Figure 4 As shown in Figure 4 in (a) of Figure 3C an opening 401 in the trench 350 may be formed by etching away a portion of the dielectric material 318. The opening 401 is desirably positioned to be aligned with the contact 235 such that forming the opening 401 exposes at least a portion of the contact 235 extending through the substrate 104 as shown in

[0059] It should be noted that for simplicity purposes Figure 4 only one opening 401 is illustrated in Figure 2A In fact, a plurality of openings 401 may be formed, each of which may be positioned to be aligned with one of a plurality of contacts 235 as shown in

[0060] In Figure 4In (b), after the opening 401 is formed, another etching process (e.g., an isotropic wet etching process) can be performed to expand the opening 401 in each plane of the conductive material such that the expanded opening 403 is tangent to the first portion 308 and the second portion 309 of the conductive material 245 (with a certain excess tolerance). In some examples, the wet etching process can etch away a portion of the dielectric material 318 and a portion of the conductive material 245 (e.g., the first portion 308 and the second portion 309).

[0061] In Figure 4 In (c), a storage element material 465 (e.g., a chalcogenide material) can be deposited in the expanded opening 403. In some examples, the filling of the expanded opening can be facilitated by top / bottom growth of the storage element material 465. In some examples, the storage element material can include an amorphous chalcogenide material configured to act as both a selector element and a storage element in a memory cell that can be a self-selecting memory cell. In some examples, the storage element material 465 is configured not to change phase when programmed in different logic states, e.g., it remains an amorphous material. After depositing the storage element material 465, a portion of the storage element material 465 can contact the first portion 308 and the second portion 309 of the conductive material 245. A portion of the storage element material 465 can be removed from the opening portion such that only the storage element material in the arched recess is retained. After removing a portion of the storage element material 465, an opening 405 communicating with the opening 401 can be formed. In some examples, the storage element material 465 can be further etched to expose the wall of the dielectric material 318 in the opening 405. As Figure 4 shown in (c), the arched recess is located on opposite sides of the opening 405. In some examples, the arched recess can be defined by the conductive material 245 (e.g., the first portion 308 and / or the second portion 309), the dielectric material 318, and the insulating material 240 (e.g., Figure 3B shown in).

[0062] In Figure 4 In (d), a conductive pillar 407 can be formed in the opening 403 that contains the storage element material in the arched recess. In some examples, the storage element material 465 can contact the conductive material 245 (e.g., the first portion 308 and the second portion 309) at the middle (e.g., the apex) of the arched recess while contacting the conductive pillar 407 at the bottom (e.g., the wider bottom) of the arched recess. In some examples, the storage element material 465 can contact the dielectric material 318 at opposite sides of the arched recess between the middle and the bottom. In some examples, the storage element material 465 can contact the insulating material 240 in a direction perpendicular to the plane of the conductive material 245( Figure 3Bas shown in FIG. In other words, the storage element material 465 can be surrounded by the conductive material 245, the dielectric material 318, the conductive pillar 407, and the insulating material 240. The conductive pillar 407 can be an example of a digit line. The conductive pillar 407 can be arranged to extend into (e.g., substantially perpendicular to) the plane of the conductive material and the substrate.

[0063] Note that, for simplicity purposes, Figure 4 only one conductive pillar 407 is illustrated in FIG. In fact, a plurality of conductive pillars 407 can be formed, and each of them can be positioned to align with one of the plurality of contact members 235 shown in FIG. for example. Figure 2A In some instances, each conductive pillar 407 can be coupled to a different conductive contact. In some instances, the conductive pillar 407 can be formed of a barrier material and a conductive material, which will be described in detail below.

[0064] In some instances, the contact area between the storage element material 465 and the conductive material 245 (e.g., the first portion 308 and / or the second portion 309) can be smaller than the contact area between the storage element material 465 and the conductive pillar 407. In other words, the storage element material 465 can have a tapered profile in the direction from the digit line (e.g., the conductive pillar 407) to the word line (e.g., the first portion 308 and / or the second portion 309 of the conductive material 245). In some instances, the contact area between the storage element material 465 and the conductive material 245 (e.g., the first portion 308 and / or the second portion 309) can be controlled by the alignment of the conductive pillar 407 relative to the conductive material 245 (e.g., the first portion 308 and / or the second portion 309). For example, if the average intercept / contact is 17 nm and the conductive pillar radius is equal to 20 nm, then a fluctuation of + / - 1 nm at its center can result in a contact size fluctuation of + / - 4 nm. Appropriate over-depression can reduce this variability and allow for better dimensional control.

[0065] Figures 5A to 6 Another example of the present disclosure is illustrated, where a conformal material 320 is formed between the conductive material 245 and the dielectric material 318. Figure 5A Illustrates the formation of the conformal material 320 (e.g., a sacrificial material or a sacrificial layer). The conformal material 320 can be deposited into the trench 350 of the memory array 200 - e'. The conformal material 320 can be formed in the recess 315 ( Figure 3B as shown in FIG.) by conformally depositing the conformal material 320. The conformal material 320 contacts the first sidewall 390, the second sidewall 391, and the bottom wall 395 of each trench 350. Although Figure 5AIt is shown that conformal material 320 can be formed on the sidewalls of trench 350 (e.g., on the surfaces of the second insulating material 240 and the conductive material 245 in different layers facing trench 350) during the formation of conformal material 320 in multiple recesses 315, but the examples are not limited thereto. For example, in some cases, conformal material 320 can be limited to multiple recesses 315 in the conductive material 245 in different layers. In some cases, conformal material 320 can be referred to as a conformal layer or a sacrificial layer.

[0066] In some cases, an etching operation can be performed after the formation of conformal material 320. In the etching operation, conformal material 320 can be etched to form an opening or trench 350. The etching operation can cause the surface of conformal material 320 (e.g., the surface facing trench 350) to be separated from the surface of the second insulating material 240 (e.g., the surface facing trench 350). In some cases, the etching operation can cause the surface of conformal material 320 (e.g., the surface facing trench 350) to be substantially coplanar with the surface of the second insulating material 240 (e.g., the surface facing trench 350), and thereby form a continuous sidewall of the trench. The etching operation described herein can be a vertical etching process (e.g., an anisotropic etching process or a dry etching process or a combination thereof) or a horizontal etching process (e.g., an isotropic etching process).

[0067] Figure 5B It is illustrated that a dielectric material 318 is deposited on top of conformal material 320 in trench 350 of memory array 200-f. Dielectric material 318 can contact conformal material 320. Dielectric material 318 and conformal material 320 can cooperate to fill trench 350. In some cases, dielectric material 318 can be an example of an insulating material. In some examples, conformal material 320 can be selectively etched back to form a coplanar surface with dielectric material 318. The depth of the recess can be defined depending on the desired thickness.

[0068] Figure 5C It is illustrated a top view of an example 3D memory array 200-f after the deposition of dielectric material 318 as Figure 5B shown. In Figure 5C it, conformal material 320 and dielectric material 318 formed in trench 350 bifurcate each plane of conductive material 245 into a first portion 308 and a second portion 309.

[0069] Figure 6 It is illustrated Figure 5C various partial views of the example 3D memory array 200-f shown in Figure 6In (a), two openings 601 in the trench 350 can be formed by etching away portions of the dielectric material 318. In some instances, the etching can include a selective etching process, e.g., for example, an etching process that removes the dielectric material 318 at a rate higher than that at which it removes the conformal material 320. The two openings 601 are desirably positioned to be aligned with the contacts 235 such that forming the openings 601 exposes at least a portion of the contacts 235 that extend through the substrate 104 ( Figure 3C shown in). The etching process can be a vertical etching process. In some instances, the etching operation can be a dry etching process. In some instances, the openings 601 can be surrounded by the dielectric material 317 and the conformal material 320.

[0070] It should be noted that, for purposes of simplicity, Figure 6 only two openings 601 are illustrated in. In fact, a plurality of openings 601 can be formed, and each two or more of them can be positioned to be aligned with one of the plurality of contacts 235 shown in, e.g., Figure 2A . In this way, the density of the conductive pillars to be formed in the openings 601 and coupled to the contacts 235 can be increased.

[0071] In some instances, the openings 601 can expose portions of the substrate 104, the plurality of conductive contacts 235, and the conformal material 320 and the insulating material 240. In some instances, the openings 601 can be formed in an oval shape, as depicted in the bottom of Figure 6 (a). In some instances, other geometric configurations of the openings are considered. For example, rectangular openings can be formed, as depicted in the top of Figure 6 (a). In some instances, the walls of the dielectric material 318 can be exposed in the openings 601.

[0072] In Figure 6In (b) thereof, it shows that a memory element material 465 is formed in the arched recess. In some examples, after forming the opening 601, another etching process (for example, an isotropic wet etching process) may be performed to expand the opening 601 in each plane of the conductive material 245, such that a portion of the conformal material 320 is etched away and an arched recess is formed in the conformal material 320 and between the conductive material 245 (for example, the first portion 308 and / or the second portion 309) and the dielectric material 318. In some examples, the arched recess is tangent (with a certain excess tolerance) to the conductive material 245 (for example, the first portion 308 and / or the second portion 309). The memory element material 465 (for example, a chalcogenide material) may be deposited in the expanded opening 603. The memory element material 465 may be partially removed from the opening 603 such that only the memory element material 465 in the arched recess is retained. In some examples, the memory element material 465 in the arched recess may contact the conductive material 245 (for example, the first portion 308 and / or the second portion 309) at the middle part (for example, the apex) of the recess, contact the conformal material 320 at the opposite sides of the recess between the middle part and the bottom (for example, the wider bottom), and contact the insulating material 240 in a direction perpendicular to the plane of the conductive material 245. In some examples, each of the arched recesses may be defined by the conductive material 245, the conformal material 320, and the insulating material 240.

[0073] In some examples, conductive pillars ( Figure 6 not shown in the figure) may be formed in the opening 603 that includes the memory element material 465 in the arched recess. In some examples, the memory element material 465 may contact the conductive material 245 at the middle part (for example, the apex) of the arched recess, while contacting the conductive pillar at the bottom (for example, the wider bottom) of the arched recess. In some examples, the memory element material 465 may contact the conformal material 320 at the opposite sides of the arched recess between the middle part and the bottom. The conductive pillar may be an example of a digital line. The conductive pillars may be arranged to extend to (for example, substantially perpendicular to) the plane of the conductive material 245 and the substrate 104. In some examples, each conductive pillar may be coupled to a different conductive contact 235. In some examples, the conductive pillar may be formed of a barrier material and a conductive material, which will be described in detail below.

[0074] In some examples, the contact area between the memory element material 465 and the conductive material 245 (for example, the first portion 308 and / or the second portion 309) may be smaller than the contact area between the memory element material 465 and the conductive pillar ( Figure 6The contact area between (not shown in the figure). In other words, the storage element material 465 may have a tapered profile in the direction from the digital line (e.g., the conductive pillar) to the word line (e.g., the first part 308 and / or the second part 309 of the conductive material 245). In some examples, the contact area between the storage element material 465 and the conductive material 245 (e.g., the first part 308 and / or the second part 309) can be controlled by the alignment of the conductive pillar relative to the conductive material 245. For example, if the average intercept / contact is 17 nm and the radius of the conductive pillar is equal to 20 nm, then a fluctuation of + / - 1 nm at its center can result in a contact size fluctuation of + / - 4 nm. Appropriate over-denting can reduce this variability and allow for better size control.

[0075] Figure 7A and 7B illustrates the formation of the storage element material 465 in the arch-shaped recesses in each of the planes of the conductive material 245. As Figure 7A shown, the storage element material 465 can be formed in a plurality of arch-shaped recesses by conformally depositing the storage element material 465 into the openings 401 and / or 601 in the trench 350 ( Figure 4 and 6 shown). The storage element material 465 can be deposited to contact the sidewalls 390 and 391 and the bottom wall 395 of the trench 350 exposed by etching the dielectric material 318 and / or the conformal material 320. When the storage element material 465 contacts the bottom wall 395 of the trench 350, the storage element material 465 covers the exposed contact 235.

[0076] An example of the storage element material 465 can be a chalcogenide material (e.g., a chalcogenide alloy and / or glass), which can act as a self-selective storage element material (e.g., a material that can act as both a selection device and a storage element). For example, the storage element material 465 can respond to an applied voltage (e.g., a programming pulse). For an applied voltage less than the threshold voltage, the storage element material 465 can remain in a non-conductive state (e.g., the "off" state). Alternatively, in response to an applied voltage greater than the threshold voltage, the storage element material 465 can enter a conductive state (e.g., the "on" state).

[0077] The memory element material 465 can be programmed to a target state by applying a pulse (e.g., a programming pulse) that meets a programming threshold. The amplitude, shape, or other characteristics of the programming pulse can be configured to cause the memory element material 465 to exhibit the target state. For example, after applying the programming pulse, ions in the memory element material 465 can be redistributed throughout the memory element, thereby changing the resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of the memory element material 465 can vary based on the applied programming pulse.

[0078] The state stored by the memory element material 465 can be sensed, detected, or read by applying a read pulse to the memory element material 465. The amplitude, shape, or other characteristics of the read pulse can be configured to allow the sensing component to determine the state stored on the memory element material 465. For example, in some cases, the amplitude of the read pulse is configured to be at a level such that the memory element material 465 will be in an "on" state (e.g., current is conducted through the material) for a first state but in an "off" state (e.g., little current is conducted through the material) for a second state.

[0079] In some cases, the polarity (programming or reading) of the pulse applied to the memory element material 465 can affect the result of the operation performed. For example, if the memory element material 465 stores a first state, a read pulse of a first polarity can cause the memory element material 465 to exhibit an "on" state while a read pulse of a second polarity can cause the memory element material 465 to exhibit an "off" state. This can occur due to an asymmetric distribution of ions or other materials in the memory element material 465 when the state is stored. A similar principle applies to programming pulses and other pulses or voltages.

[0080] Examples of chalcogenide materials that can serve as the storage element material 465 include indium (In)-antimony (Sb)-tellurium (Te) (IST) materials (such as In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc.) and germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) materials (such as Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, or the like) and other chalcogenide materials, including (for example) alloys that do not change phase during operation (e.g., selenium-based chalcogenide alloys). In addition, the chalcogenide materials can include smaller concentrations of other dopant materials. Other examples of chalcogenide materials can include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), sulfur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc) materials and combinations thereof. Hyphenated chemical composition symbols as used herein indicate the elements included in a particular mixture or compound and are intended to represent all stoichiometries involving the indicated elements. In some instances, the chalcogenide materials can be chalcogenide glasses or amorphous chalcogenide materials. In some instances, chalcogenide materials that primarily have selenium (Se), arsenic (As), and germanium (Ge) can be referred to as SAG alloys. In some instances, the SAG alloys can include silicon (Si) and such chalcogenide materials can be referred to as SiSAG alloys. In some instances, the chalcogenide glasses can include additional elements in their atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F). In some instances, the conductivity can be controlled by doping with various chemical species. For example, doping can include incorporating Group 3 (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or Group 4 (tin (Sn), carbon (C), silicon (Si), etc.) elements into the composition.

[0081] As Figure 7B shown, an etch operation can be performed subsequent to the formation of the storage element material 465 such that the surface of the storage element material 465 (e.g., the surface facing the trench 350 or the opening 401 / 601 ( Figure 7B not shown in the figure)) is substantially coplanar with the surface of the insulating material 240 (e.g., the surface facing the trench 350). Etching of the storage element material 465 can form continuous sidewalls and remove the top layer 466 of the storage element material 465 ( Figure 7AAs shown in [figure number], the cells of the memory element material 465 are formed only in the arched recesses. In each recess, each cell of the memory element material 465 can contact a single conductive material 245 (e.g., a single conductive material 245 positioned adjacent to the cell of the memory element material 465) and at least two insulating material layers (e.g., a top insulating material layer and a bottom insulating material layer positioned on top of and at the bottom of the cell of the memory element material 465). Etching of the memory element material 465 can provide a configuration in which the memory element materials 465 are separated from each other. Etching of the memory element material 465 can also expose the contacts 235 in the substrate 104.

[0082] Figure 8 Side view of an example 3D memory array 200-i according to an example of the present disclosure. In Figure 8 the conductive pillars 580 can be formed in the openings 401 and / or 601 shown in Figure 4 and 6 In some examples, a conductive material 575 can be deposited in the openings to form the conductive pillars 580. In some examples, the conductive pillars 580 can include a barrier material 570 and a conductive material 575. As Figure 8 shown in [[figure number]], a capping layer 585 (e.g., an insulating material, such as a dielectric layer) can be deposited to cap the conductive pillars 580 of the memory array 200-i. In some examples, the conductive pillars 580 can be the conductive pillars 407 shown in Figure 4 and the conductive pillars of the example shown in Figure 6 The memory array 200-i can include a plurality of vertical stacks. Each respective stack can include conductive pillars 580, conductive contacts 235 coupled to the conductive pillars 580, memory element material 465 formed to contact the first portion 308 and the conductive pillars 580, and memory element material 465 formed to contact the second portion 309 and the conductive pillars 580.

[0083] The conductive pillars 580 can contact the conductive contacts 235 and the insulating material 240, and contact the memory element material 465. In some cases, the memory element material 465 is partially (e.g., not completely) formed around the conductive pillars 580.

[0084] Although not shown in [[figure number]] for clarity and to avoid obscuring the examples of the present disclosure, other materials can be formed before, after, and / or between the memory element material 465 and / or the conductive pillars 580, for example, to form an adhesion layer or a barrier to prevent interdiffusion of materials and / or mitigate composition mixing.

[0085] Although not shown in [[figure number]] for clarity and to avoid obscuring the examples of the present disclosure, other materials can be formed before, after, and / or between the memory element material 465 and / or the conductive pillars 580, for example, to form an adhesion layer or a barrier to prevent interdiffusion of materials and / or mitigate composition mixing. Figure 8 Although not shown in [[figure number]] for clarity and to avoid obscuring the examples of the present disclosure, other materials can be formed before, after, and / or between the memory element material 465 and / or the conductive pillars 580, for example, to form an adhesion layer or a barrier to prevent interdiffusion of materials and / or mitigate composition mixing.

[0086] Figure 9FIG. 0 is a flow chart showing a method 900 for manufacturing a 3D memory array according to aspects of the present disclosure. The operations of method 900 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute an instruction set to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0087] At S910, method 900 may include forming a plurality of conductive contacts extending through a substrate, each conductive contact being associated with a respective one of a plurality of digital lines. The operations of S910 may be performed according to the methods described herein.

[0088] At S920, method 900 may include forming a plurality of conductive layers separated from each other by respective ones of a plurality of dielectric layers, the plurality of conductive layers being configured as word lines. The operations of S920 may be performed according to the methods described herein.

[0089] At S930, method 900 may include forming a trench through the plurality of conductive layers and the plurality of dielectric layers, the trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines. The operations of S930 may be performed according to the methods described herein.

[0090] At S940, method 900 may include depositing a dielectric material in the trench. The operations of S940 may be performed according to the methods described herein.

[0091] At S950, method 900 may include forming a plurality of openings by etching a portion of the dielectric material, each opening being above a respective contact and exposing the respective contact. The operations of S950 may be performed according to the methods described herein.

[0092] At S960, method 900 may include forming a plurality of recesses in the openings in a plurality of planes in which the conductive layers are located. The operations of S960 may be performed according to the methods described herein.

[0093] At S970, method 900 may include forming a chalcogenide material in the plurality of recesses. The operations of S970 may be performed according to the methods described herein.

[0094] At S980, method 900 may include forming a plurality of conductive pillars, each conductive pillar being in a respective one of a plurality of openings and in contact with a chalcogenide material formed in a respective one of a plurality of recesses, the plurality of conductive pillars being configured as digit lines, wherein each of the plurality of recesses has an arch shape and is between a respective word line and a respective digit line, and the chalcogenide material in the recess contacts the respective word line at a middle portion of the recess and contacts the respective digit line at a bottom portion of the recess. The operations of S980 may be performed according to the methods described herein.

[0095] In some instances, the contact area between the chalcogenide material and the respective word line may be smaller than the contact area between the chalcogenide material and the respective digit line.

[0096] In some instances, the contact area between the chalcogenide material and the respective word line may be controlled by alignment of the respective digit line relative to the respective word line.

[0097] In some instances, the chalcogenide material in the recess may contact a dielectric material at opposite sides of the recess between the middle and the bottom.

[0098] Additionally or alternatively, method 900 for manufacturing a 3D memory array may further include forming conformal materials between the dielectric material and the first and second sets of word lines, respectively, and wherein the chalcogenide material in the recess may contact the conformal material at opposite sides of the recess between the middle and the bottom.

[0099] In some instances, the step of forming the opening may include performing a vertical etching process to vertically etch the dielectric material, and wherein the vertical etching process may be a dry etching process.

[0100] In some instances, the step of forming the recess may include performing a horizontal etching process after the vertical etching process to form at least one recess in a plane where the conductive layer is located, and wherein the horizontal etching process may be an isotropic wet etching process.

[0101] In some instances, the conductive pillars of the plurality of conductive pillars may further include a barrier layer contacting at least a portion of the chalcogenide material and a conductive material contacting the barrier layer.

[0102] In some instances, the plurality of conductive pillars formed above the plurality of contacts may interrupt the continuity of the dielectric material extending over the substrate in a serpentine shape.

[0103] In some instances, the step of forming the trench may include performing a vertical etching process to vertically etch the trench, and performing a horizontal etching process after the vertical etching process to form at least one groove in the conductive layer.

[0104] In some instances, a trench may include a first sidewall spaced apart from a second sidewall, where a first portion of the first sidewall formed through a dielectric layer is spaced apart from a first portion of the second sidewall formed through the dielectric layer by a first distance, and a second portion of the first sidewall formed through a conductive layer is spaced apart from a second portion of the second sidewall formed through the conductive layer by a second distance greater than the first distance.

[0105] Figure 10 FIG. 4 shows a flowchart of another method 1000 for manufacturing a 3D memory array in accordance with aspects of the present disclosure. The operations of method 1000 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute an instruction set to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0106] At S1010, method 1000 may include forming a trench that passes through a plurality of conductive layers and a plurality of dielectric layers of a 3D memory array, the trench exposing a substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines. The operations of S1010 may be performed according to the methods described herein.

[0107] At S1020, method 1000 may include depositing a dielectric material in the trench. The operations of S1020 may be performed according to the methods described herein.

[0108] At S1030, method 1000 may include forming a plurality of openings that each expose the substrate by etching a portion of the dielectric material. The operations of S1030 may be performed according to the methods described herein.

[0109] At S1040, method 1000 may include forming a plurality of recesses in the openings in a plurality of planes where the conductive layers are located. The operations of S1040 may be performed according to the methods described herein.

[0110] At S1050, method 1000 may include forming a chalcogenide material in the plurality of recesses, and wherein each of the plurality of recesses has an arch shape, and the chalcogenide material in the recess contacts a corresponding word line at the apex of the arch of the recess. The operations of S1050 may be performed according to the methods described herein.

[0111] Additionally or alternatively, method 1000 for fabricating a 3D memory array may further include forming a plurality of conductive pillars, each conductive pillar being in a respective one of the plurality of openings and in contact with a chalcogenide material formed in a respective one of the plurality of recesses, the plurality of conductive pillars being configured as digit lines, and wherein each of the plurality of recesses is between a respective word line and a respective digit line, and the chalcogenide material in the recess contacts the respective digit line at the bottom of the recess.

[0112] In some instances, the contact area between the chalcogenide material and the respective word line may be less than the contact area between the chalcogenide material and the respective digit line.

[0113] In some instances, the contact area between the chalcogenide material and the respective word line may be controlled by the alignment of the respective digit line relative to the respective word line.

[0114] In some instances, the chalcogenide material in the recess may contact a dielectric material at opposite sides of the recess between the vault and the bottom.

[0115] Alternatively, method 1000 for fabricating a 3D memory array may further include forming conformal materials between a dielectric material and first and second sets of word lines, respectively, and wherein the chalcogenide material in the recess contacts the conformal material at opposite sides of the recess adjacent the vault.

[0116] In some instances, the step of forming the chalcogenide material may include depositing an amorphous chalcogenide material configured to act as both a selector element and a storage element in a memory cell that may be a self - select memory cell. In some instances, the storage element material is configured to not change phase when programmed in different logic states, e.g., it remains an amorphous material.

[0117] Figure 11 is a block diagram of a device in the form of a memory device 1100 according to an example as disclosed herein. As used herein, "device" may refer to (but is not limited to) any one of a variety of structures or combinations of structures, such as (by way of example) a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. As Figure 11 shown, memory device 1100 may include a 3D memory array 1110. 3D memory array 1110 may be similar to the 3D memory array 200 - i described previously in connection with Figure 8 description. Although a single 3D memory array 1110 is shown for clarity and to avoid obscuring the examples of the present disclosure, Figure 11 memory device 1100 may include any number of 3D memory arrays 1110.

[0118] As Figure 11As shown, the memory device 1100 may include decoding circuitry 1120 coupled to a 3D memory array 1110. The decoding circuitry 1120 may be included on the same physical device (e.g., the same die) as the 3D memory array 1110. The decoding circuitry 1120 may be included on a separate physical device communicatively coupled to the physical device including the 3D memory array 1110.

[0119] The decoding circuitry 1120 may receive and decode address signals during programming and / or sensing operations performed on the 3D memory array 1110 to access memory cells of the 3D memory array 1110 as mentioned above with reference to Figure 1 the memory cells mentioned. For example, the decoding circuitry 1120 may include portions of decoder circuitry for selecting a particular memory cell of the 3D memory array 1110 to access during a programming or sensing operation. For example, a first portion of the decoder circuitry may be used to select word lines and a second portion of the decoder circuitry may be used to select digit lines.

[0120] Figure 11 The examples described may include additional circuitry, logic, and / or components not described so as not to obscure the present disclosure. For example, the memory device 1100 may include a controller for sending commands to perform operations on the 3D memory array 1110 (e.g., sensing (e.g., reading), programming (e.g., writing), moving, and / or erasing data operations, and other operations). Additionally, the memory device 1100 may include address circuitry for latching address signals provided via an I / O connector through input / output (I / O) circuitry. Additionally, the memory device 1100 may include a main memory separate from and / or in addition to the memory array 1110, such as (e.g.) DRAM or SDRAM.

[0121] Describes a vertical 3D memory device. In some examples, the vertical 3D memory device may include: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from each other by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a dielectric material positioned between the first plurality of word line plates and the second plurality of word line plates, the dielectric material extending in a serpentine shape over the substrate; a plurality of pillars formed over the plurality of contacts and coupled to the plurality of contacts; and a plurality of memory elements, each including a chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, wherein the recess has an arch shape, and the chalcogenide material in the recess contacts the respective word line plate at a middle portion of the recess and contacts the respective pillar at a bottom portion of the recess.

[0122] In some instances, the contact area between the chalcogenide material and the corresponding word line plate is smaller than the contact area between the chalcogenide material and the corresponding pillar.

[0123] In some instances, the contact area between the chalcogenide material and the corresponding word line plate is controlled by the alignment of the corresponding pillar relative to the corresponding word line plate.

[0124] In some instances, the chalcogenide material in the recess contacts the dielectric material at opposite sides of the recess between the middle and the bottom.

[0125] In some instances, a vertical 3D memory device may include conformal materials respectively positioned between the dielectric material and a first plurality of word line plates and a second plurality of word line plates, wherein the chalcogenide material in the recess contacts the conformal material at opposite sides of the recess between the middle and the bottom.

[0126] In some instances, the pillars of the plurality of pillars further include a barrier layer contacting at least a portion of the chalcogenide material and a conductive material contacting the barrier layer and configured as a digit line.

[0127] In some instances, the plurality of pillars formed above the plurality of contacts interrupt the continuity of the dielectric material extending over the substrate in a serpentine shape.

[0128] In some instances, the plurality of contacts are arranged in a staggered pattern.

[0129] In some instances, the plurality of contacts are arranged in a grid.

[0130] In some instances, a vertical 3D memory device may include circuitry configured to select a corresponding word line and a corresponding digit line during a programming operation or a sensing operation performed on the vertical 3D memory device.

[0131] Disclosed is a method of manufacturing a vertical 3D memory array. In some examples, the method may include: forming a plurality of conductive contacts extending through a substrate, each conductive contact being associated with a respective one of a plurality of digit lines; forming a plurality of conductive layers separated from each other by respective ones of a plurality of dielectric layers, the plurality of conductive layers being configured as word lines; forming a trench through the plurality of conductive layers and the plurality of dielectric layers, the trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines; depositing a dielectric material in the trench; forming a plurality of openings each above a respective contact and exposing the respective contact by etching a portion of the dielectric material; forming a plurality of recesses in the plurality of openings in a plurality of planes in which the plurality of conductive layers are located; forming a chalcogenide material in the plurality of recesses; and forming a plurality of conductive pillars, each conductive pillar being in a respective one of the plurality of openings and in contact with the chalcogenide material formed in a respective one of the plurality of recesses, the plurality of conductive pillars being configured as digit lines, wherein each of the plurality of recesses has an arch shape and is between a respective word line and a respective digit line, and the chalcogenide material in the recess contacts the respective word line at a middle portion of the recess and contacts the respective digit line at a bottom portion of the recess.

[0132] In some examples, the contact area between the chalcogenide material and the respective word line is smaller than the contact area between the chalcogenide material and the respective digit line.

[0133] In some examples, the contact area between the chalcogenide material and the respective word line is controlled by alignment of the respective digit line relative to the respective word line.

[0134] In some examples, the chalcogenide material in the recess contacts the dielectric material at opposite sides of the recess between the middle and the bottom.

[0135] In some examples, the method may include forming a conformal material between the dielectric material and the first set of word lines and the second set of word lines, respectively, wherein the chalcogenide material in the recess contacts the conformal material at opposite sides of the recess between the middle and the bottom.

[0136] In some examples, forming the plurality of openings may include performing a vertical etching process to vertically etch the dielectric material, wherein the vertical etching process is a dry etching process.

[0137] In some examples, forming the plurality of recesses may include performing a horizontal etching process after the vertical etching process to form at least one recess in at least one plane of a plurality of planes in which at least one of the plurality of conductive layers is located, wherein the horizontal etching process is an isotropic wet etching process.

[0138] In some examples, the conductive pillars of the plurality of conductive pillars further include a barrier layer contacting at least a portion of the chalcogenide material and a conductive material contacting the barrier layer.

[0139] In some examples, the plurality of conductive pillars formed over the plurality of contacts interrupt the continuity of the dielectric material extending over the substrate in a serpentine shape.

[0140] In some examples, forming the trench may include performing a vertical etching process to vertically etch the trench and performing a horizontal etching process after the vertical etching process to form at least one recess in at least one of the plurality of conductive layers.

[0141] In some examples, the trench includes a first sidewall spaced apart from a second sidewall, wherein a first portion of the first sidewall formed by the plurality of dielectric layers is spaced apart from a first portion of the second sidewall formed by the plurality of dielectric layers by a first distance, and a second portion of the first sidewall formed by the plurality of conductive layers is spaced apart from a second portion of the second sidewall formed by the plurality of conductive layers by a second distance greater than the first distance.

[0142] A method of manufacturing a vertical 3D memory array is described. In some examples, the method may include: forming a trench through a plurality of conductive layers and a plurality of dielectric layers of the 3D memory array, the trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines; depositing a dielectric material in the trench; forming a plurality of openings each exposing the substrate by etching a portion of the dielectric material; forming a plurality of recesses in a plurality of planes where the plurality of conductive layers are located in the plurality of openings; and forming a chalcogenide material in the plurality of recesses, wherein each of the plurality of recesses has an arch shape, and the chalcogenide material in the recess contacts the corresponding word line at the apex of the arch of the recess.

[0143] In some examples, the method may include forming a plurality of conductive pillars, each conductive pillar being in a corresponding one of the plurality of openings and contacting the chalcogenide material formed in a corresponding one of the plurality of recesses, the plurality of conductive pillars being configured as digit lines, wherein each of the plurality of recesses is between a corresponding word line and a corresponding digit line, and the chalcogenide material in the recess further contacts the corresponding digit line at the bottom of the recess.

[0144] In some examples, the contact area between the chalcogenide material and the corresponding word line is smaller than the contact area between the chalcogenide material and the corresponding digit line.

[0145] In some examples, the contact area between the chalcogenide material and the corresponding word line is controlled by the alignment of the corresponding digit line relative to the corresponding word line.

[0146] In some instances, the chalcogenide material in the recess contacts the dielectric material at opposite sides of the recess between the vault and the bottom.

[0147] In some instances, the method may include forming conformal materials between the dielectric material and the first set of word lines and the second set of word lines, respectively, wherein the chalcogenide material in the recess contacts the conformal material at opposite sides of the recess adjacent to the vault.

[0148] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0149] Various illustrative blocks and modules described in connection with the present disclosure may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0150] The functions described herein may be implemented in hardware, in software executed by a processor, in firmware, or in any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or code on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The features implementing the functions may also be physically located in various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0151] In addition, as used herein, the "or" used in a list of items, such as in a claim (e.g., a list of items beginning with a phrase such as "at least one of... " or "one or more of... ") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0152] The description provided herein enables one of ordinary skill in the art to make or use the present disclosure. One of ordinary skill in the art will recognize various modifications to the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A vertical 3D memory device, comprising: A plurality of contacts associated with a plurality of digital lines and extending through a substrate; A plurality of word line plates separated from each other by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; A dielectric material positioned between the first plurality of word line plates and the second plurality of word line plates, the dielectric material extending over the substrate in a serpentine shape; A plurality of pillars formed above the plurality of contacts and coupled to the plurality of contacts; And A plurality of memory elements, each including a chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, Wherein the recess has an arched shape, and the chalcogenide material in the recess contacts the respective word line plate at a middle portion of the recess and contacts the respective pillar at a bottom portion of the recess, and wherein a first memory element among the plurality of memory elements is separated from a second memory element among the plurality of memory elements by a respective dielectric layer in the respective dielectric layers.

2. The vertical 3D memory device according to claim 1, wherein: The chalcogenide material in the recess contacts the dielectric material at opposite sides of the recess between the middle portion and the bottom portion.

3. The vertical 3D memory device according to claim 1, further comprising: A conformal material positioned respectively between the dielectric material and the first plurality of word line plates and the second plurality of word line plates, Wherein the chalcogenide material in the recess contacts the conformal material at opposite sides of the recess between the middle portion and the bottom portion.

4. The vertical 3D memory device according to claim 1, wherein: A pillar among the plurality of pillars further includes a barrier layer contacting at least a portion of the chalcogenide material and a conductive material contacting the barrier layer and configured as a digital line.

5. The vertical 3D memory device according to claim 1, wherein: The plurality of contacts are arranged in a staggered pattern.

6. The vertical 3D memory device according to claim 1, wherein: The plurality of contacts are arranged in a grid.

7. The vertical 3D memory device according to claim 1, further comprising: A circuitry configured to select a respective word line plate and a respective digital line during a programming operation or a sensing operation performed on the vertical 3D memory device.

8. A vertical 3D memory device, comprising: A plurality of contacts associated with a plurality of digital lines and extending through a substrate; A plurality of word line plates separated from each other by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; A dielectric material positioned between the first plurality of word line plates and the second plurality of word line plates, the dielectric material extending over the substrate in a serpentine shape; A plurality of pillars formed above the plurality of contacts and coupled to the plurality of contacts; And A plurality of memory elements, each including a chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, Wherein the recess has an arch shape, and the chalcogenide material in the recess contacts the corresponding word line plate at the middle of the recess and contacts the corresponding pillar at the bottom of the recess, and wherein the contact area between the chalcogenide material and the corresponding word line plate is smaller than the contact area between the chalcogenide material and the corresponding pillar.

9. The vertical 3D memory device according to claim 8, wherein: The contact area between the chalcogenide material and the corresponding word line plate is controlled by the alignment of the corresponding pillar relative to the corresponding word line plate.

10. A vertical 3D memory device, comprising: A plurality of contacts associated with a plurality of digital lines and extending through a substrate; A plurality of word line plates separated from each other by corresponding dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; A dielectric material positioned between the first plurality of word line plates and the second plurality of word line plates, the dielectric material extending in a serpentine shape above the substrate; A plurality of pillars formed above the plurality of contacts and coupled to the plurality of contacts; And A plurality of memory elements, each including a chalcogenide material positioned in a recess between a corresponding word line plate and a corresponding pillar, Wherein the recess has an arch shape, and the chalcogenide material in the recess contacts the corresponding word line plate at the middle of the recess and contacts the corresponding pillar at the bottom of the recess, and wherein the plurality of pillars formed above the plurality of contacts interrupt the continuity of the dielectric material extending in the serpentine shape above the substrate.

11. A method of manufacturing a vertical 3D memory array, comprising: Forming a plurality of conductive contacts extending through a substrate, each associated with a corresponding one of a plurality of digital lines; Forming a plurality of conductive layers separated from each other by corresponding ones of a plurality of dielectric layers, the plurality of conductive layers configured as word lines; Forming a trench through the plurality of conductive layers and the plurality of dielectric layers, the trench exposing the substrate and dividing the plurality of conductive layers into a first group of word lines and a second group of word lines; Depositing a dielectric material in the trench; Forming a plurality of openings by etching a portion of the dielectric material, each opening above a corresponding contact and exposing the corresponding contact; Forming a plurality of recesses in the plurality of openings in a plurality of planes in which the plurality of conductive layers are located; Forming a chalcogenide material in the plurality of recesses; And Forming a plurality of conductive pillars, each conductive pillar in a corresponding one of the plurality of openings and contacting the chalcogenide material formed in a corresponding one of the plurality of recesses, the plurality of conductive pillars configured as digital lines, wherein each of the plurality of recesses has an arch shape and is between a corresponding word line and a corresponding digital line, and the chalcogenide material in the recess contacts the corresponding word line at the middle of the recess and contacts the corresponding digital line at the bottom of the recess, and wherein a first chalcogenide material formed in a first recess of the plurality of recesses is separated from a second chalcogenide material by a corresponding one of the plurality of dielectric layers, wherein the second chalcogenide material is formed in a second recess of the plurality of recesses.

12. The method according to claim 11, wherein: the chalcogenide material in the recess contacts the dielectric material at opposite sides of the recess between the middle portion and the bottom portion.

13. The method according to claim 11, further comprising: forming conformal materials between the dielectric material and the first set of word lines and the second set of word lines respectively, wherein the chalcogenide material in the recess contacts the conformal material at opposite sides of the recess between the middle portion and the bottom portion.

14. The method according to claim 11, wherein forming the plurality of openings comprises: performing a vertical etching process to vertically etch the dielectric material, wherein the vertical etching process is a dry etching process.

15. The method according to claim 14, wherein forming the plurality of recesses comprises: performing a horizontal etching process after the vertical etching process to form at least one recess in at least one of the plurality of planes where at least one of the plurality of conductive layers is located, wherein the horizontal etching process is an isotropic wet etching process.

16. The method according to claim 11, wherein: the conductive pillars of the plurality of conductive pillars further comprise a barrier layer contacting at least a portion of the chalcogenide material and a conductive material contacting the barrier layer.

17. The method according to claim 11, wherein forming the trench comprises: performing a vertical etching process to vertically etch the trench; and performing a horizontal etching process after the vertical etching process to form at least one groove in at least one of the plurality of conductive layers.

18. The method according to claim 17, wherein: the trench comprises a first sidewall spaced apart from a second sidewall, wherein a first portion of the first sidewall formed by the plurality of dielectric layers is spaced apart from a first portion of the second sidewall formed by the plurality of dielectric layers by a first distance, and a second portion of the first sidewall formed by the plurality of conductive layers is spaced apart from a second portion of the second sidewall formed by the plurality of conductive layers by a second distance greater than the first distance.

19. A method of manufacturing a vertical 3D memory array, comprising: forming a plurality of conductive contacts extending through a substrate, each associated with a corresponding one of a plurality of digital lines; forming a plurality of conductive layers separated from each other by respective ones of a plurality of dielectric layers, the plurality of conductive layers configured as word lines; forming a trench through the plurality of conductive layers and the plurality of dielectric layers, the trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines; depositing a dielectric material in the trench; forming a plurality of openings by etching a portion of the dielectric material, each opening being above a corresponding contact and exposing the corresponding contact; forming a plurality of recesses in the plurality of openings in a plurality of planes where the plurality of conductive layers are located; forming a chalcogenide material in the plurality of recesses; and Forming a plurality of conductive pillars, each conductive pillar being in a respective one of the plurality of openings and in contact with the chalcogenide material formed in a respective one of the plurality of recesses, the plurality of conductive pillars being configured as digit lines, wherein each of the plurality of recesses has an arched shape and is between a respective word line and a respective digit line, and the chalcogenide material in the recess contacts the respective word line at a middle portion of the recess and contacts the respective digit line at a bottom portion of the recess, and wherein a contact area between the chalcogenide material and the respective word line is smaller than a contact area between the chalcogenide material and the respective digit line.

20. The method according to claim 19, wherein: The contact area between the chalcogenide material and the respective word line is controlled by alignment of the respective digit line relative to the respective word line.

21. A method of manufacturing a vertical 3D memory array, comprising: Forming a plurality of conductive contacts extending through a substrate, each associated with a respective one of a plurality of digit lines; Forming a plurality of conductive layers separated from each other using respective ones of a plurality of dielectric layers, the plurality of conductive layers being configured as word lines; Forming trenches through the plurality of conductive layers and the plurality of dielectric layers, the trenches exposing the substrate and dividing the plurality of conductive layers into a first group of word lines and a second group of word lines; Depositing a dielectric material in the trenches; Forming a plurality of openings by etching a portion of the dielectric material, each opening being above a respective contact and exposing the respective contact; Forming a plurality of recesses in the plurality of openings in a plurality of planes in which the plurality of conductive layers are located; Forming a chalcogenide material in the plurality of recesses; and Forming a plurality of conductive pillars, each conductive pillar being in a respective one of the plurality of openings and in contact with the chalcogenide material formed in a respective one of the plurality of recesses, the plurality of conductive pillars being configured as digit lines, wherein each of the plurality of recesses has an arched shape and is between a respective word line and a respective digit line, and the chalcogenide material in the recess contacts the respective word line at a middle portion of the recess and contacts the respective digit line at a bottom portion of the recess, and wherein the plurality of conductive pillars formed above the plurality of conductive contacts interrupt a continuity of the dielectric material extending above the substrate in a serpentine shape.

22. A method of manufacturing a vertical 3D memory array, comprising: Forming trenches through a plurality of conductive layers and a plurality of dielectric layers of the vertical 3D memory array, the trenches exposing a substrate and dividing the plurality of conductive layers into a first group of word lines and a second group of word lines; Depositing a dielectric material in the trenches; Forming a plurality of openings each exposing the substrate by etching a portion of the dielectric material; Forming a plurality of recesses in the plurality of openings in a plurality of planes in which the plurality of conductive layers are located; and Forming a chalcogenide material in the plurality of recesses Each of the plurality of recesses has an arch, and the chalcogenide material in the corresponding recess contacts the corresponding word line at the apex of the arch of the corresponding recess, and wherein the first chalcogenide material formed in the first recess of the plurality of recesses is separated from the second chalcogenide material by a corresponding one of the plurality of dielectric layers, wherein the second chalcogenide material is formed in a second recess of the plurality of recesses.

23. The method according to claim 22, further comprising: Forming a plurality of conductive pillars, each conductive pillar being in a corresponding one of the plurality of openings and in contact with the chalcogenide material formed in a corresponding one of the plurality of recesses, the plurality of conductive pillars being configured as digit lines, wherein each of the plurality of recesses is between a corresponding word line and a corresponding digit line, and the chalcogenide material in the corresponding recess further contacts the corresponding digit line at the bottom of the corresponding recess.

24. The method according to claim 23, wherein: The chalcogenide material in the corresponding recess contacts the dielectric material at an opposite side of the corresponding recess between the apex and the bottom.

25. The method according to claim 22, further comprising: Forming conformal materials between the dielectric material and the first set of word lines and the second set of word lines, respectively, wherein the chalcogenide material in the corresponding recess contacts the conformal material at an opposite side of the corresponding recess adjacent to the apex.

26. A method of manufacturing a vertical 3D memory array, comprising: Forming trenches through a plurality of conductive layers and a plurality of dielectric layers of the vertical 3D memory array, the trenches exposing a substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines; Depositing a dielectric material in the trenches; Forming a plurality of openings each exposing the substrate by etching a portion of the dielectric material; Forming a plurality of recesses in the plurality of openings in a plurality of planes in which the plurality of conductive layers are located; Forming a chalcogenide material in the plurality of recesses, and Forming a plurality of conductive pillars, each conductive pillar being in a corresponding one of the plurality of openings and in contact with the chalcogenide material formed in a corresponding one of the plurality of recesses, the plurality of conductive pillars being configured as digit lines, wherein each of the plurality of recesses has an arch and is between a corresponding word line and a corresponding digit line, and the chalcogenide material in the corresponding recess contacts the corresponding word line at the apex of the corresponding recess and further contacts the corresponding digit line at the bottom of the corresponding recess, and wherein the contact area between the chalcogenide material and the corresponding word line is smaller than the contact area between the chalcogenide material and the corresponding digit line.

27. The method according to claim 26, wherein: The contact area between the chalcogenide material and the corresponding word line is controlled by alignment of the corresponding digit line relative to the corresponding word line.

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