Chip with power glitch detection and power glitch self-test function
By integrating a glitch detector and self-test circuit inside the chip, and using a phase-locked loop to generate a sharp self-test glitch signal, the problem of power supply glitch attack detection is solved, realizing self-testing and protection without the need for additional test pads, thus enhancing the chip's security and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MEDIATEK INC
- Filing Date
- 2022-12-29
- Publication Date
- 2026-08-04
AI Technical Summary
Existing technologies are insufficient to effectively detect and defend against power supply glitches, especially in system-on-a-chip designs, where hackers may exploit power supply glitches to attack chips and leak secrets.
The chip integrates a glitch detector and a self-test circuit. It uses a phase-locked loop to generate a sharp self-test glitch signal, which is switched between normal mode and self-test mode by a multiplexer. Combined with a self-test verifier and a safety switch, it achieves self-testing and protection.
It enables self-testing without additional test pads, improves the chip's ability to detect power supply glitches, enhances safety and reliability, and prevents interference from external glitches.
Smart Images
Figure CN116400206B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to power-glitch detection and power-glitch self-testing on chips. Background Technology
[0002] Today, it is known that hackers use power glitches, a sophisticated attack designed to confuse chips in electronic devices in order to reveal their secrets.
[0003] Detecting such malicious attacks is a critical issue in system-on-chip (SoC) design. Summary of the Invention
[0004] Techniques related to power glitch detection and power glitch self-testing on chips are illustrated.
[0005] A chip with power glitch detection and power glitch self-test according to an exemplary embodiment of the present invention includes a processor, a glitch detector, and a self-test circuit. The processor has a power terminal for receiving power. The glitch detector is coupled to the processor's power terminal for detecting power glitch. The self-test circuit includes a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-test glitch signal within the chip to test the glitch detector.
[0006] The self-test glitch signal in this application is generated by the chip itself. No additional test pads are required to test the glitch detector.
[0007] In an exemplary embodiment, the chip has a multiplexer. In normal mode, the multiplexer couples the processor's power supply to a glitch detector, and in power glitch self-test mode, the self-test glitch signal is coupled to the glitch detector.
[0008] In an exemplary embodiment, the glitch controller includes a phase-locked loop that generates a clock signal, and the glitch controller operates according to the clock signal. Therefore, a sharp signal can be generated for use as a self-test glitch signal.
[0009] In an exemplary embodiment, the glitch controller further includes a shift register and a pulse generator. The shift register operates according to a clock signal generated by a phase-locked loop. The pulse generator is driven by the shift register to generate a pulse signal, which is transmitted to the glitch generator to determine the pulse width of the self-test glitch signal.
[0010] In an exemplary embodiment, the glitch generator includes a voltage divider and a plurality of switches. The voltage divider provides a plurality of selectable voltages, and the switches are used to select one of the selectable voltages as a self-test glitch signal. A glitch controller controls the switches of the glitch generator to activate the selected switch using the pulse signal, the selected switch being the switch corresponding to the selected selectable voltage.
[0011] In one exemplary embodiment, the self-test glitch signal is fed back to the glitch controller for verification, and the glitch controller presents an error flag to indicate an error in the self-test glitch signal.
[0012] In an exemplary embodiment, the glitch controller generates a first trigger signal and a second trigger signal based on the pulse signal to detect the rising transition of the inverted signal of the self-test glitch signal and the rising transition of the self-test glitch signal. When the rising transition of the inverted signal of the self-test glitch signal is detected based on the first trigger signal and the rising transition of the self-test glitch signal is detected based on the second trigger signal, the error flag is de-asserted to indicate that the self-test glitch signal is operating normally.
[0013] In an exemplary embodiment, the glitch controller includes a first D flip-flop, a second D flip-flop, a third D flip-flop, and an AND gate. The D terminal of the first D flip-flop receives the inverted signal of a self-test glitch signal, and its clock terminal receives a first trigger signal. The D terminal of the second D flip-flop receives the self-test glitch signal, and its clock terminal receives a second trigger signal. The Q terminals of the first and second D flip-flops are coupled to the inputs of the AND gate. The D terminal of the third D flip-flop is connected to a high level. The clock terminal of the third D flip-flop receives the output of the AND gate, and its QB terminal indicates an error flag.
[0014] In an exemplary embodiment, the chip also includes a test pad and a safety switch. The safety switch is coupled between the test pad and the self-test glitch input of the multiplexer. When the enable signal is deactivated to disable the use of the test pad, the safety switch prevents external glitch signals from entering through the test pad.
[0015] In one exemplary embodiment, the chip also has a variable resistor coupled between the chip's power supply terminal and the multiplexer's self-test glitch input terminal for IR compensation.
[0016] The embodiments will now be described in detail with reference to the accompanying drawings. Attached Figure Description
[0017] The invention will be more fully understood by referring to the following detailed description and embodiments, in which:
[0018] Figure 1A chip 100 is depicted according to an exemplary embodiment of the present invention;
[0019] Figure 2 A self-test circuit 200 according to an exemplary embodiment is depicted;
[0020] Figure 3 A self-test circuit 300 with a verification circuit according to an exemplary embodiment of the present invention is depicted;
[0021] Figure 4 A self-testing checker 400 according to an exemplary embodiment of the present invention is depicted;
[0022] Figure 5 The signal waveform diagram depicts the operation of the self-test verifier 400.
[0023] Figure 6 This illustrates the security design of the Test_pad; and
[0024] Figure 7 A safety switch 700 according to an exemplary embodiment of the present invention is depicted. Detailed Implementation
[0025] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by referring to the appended claims.
[0026] Figure 1 A chip 100 according to an exemplary embodiment of the present invention is depicted, having a processor 102 (e.g., a central processing unit (CPU), a tensor processing unit (TPU), etc.) and a glitch detection design. The processor 102 may have multiple power terminals VDD_P configured to receive power. Each power terminal VDD_P may be coupled to a glitch detection module.
[0027] The glitch detection module 104 includes a glitch detector 106 and a self-test circuit 108. Besides being coupled to the power supply terminal VDD_P to detect glitch signals that may be caused by a hacker attack, the glitch detector 106 can be tested by the self-test circuit 108. The self-test circuit 108 has a glitch generator 110 and a glitch controller 112. The glitch controller 112 controls the glitch generator 110 to generate a self-test glitch signal STsig within the chip 100 to test the glitch detector 106.
[0028] Since the glitch detector 106 is tested within the chip 100, there is no need to design additional test pads to receive external glitch test signals for testing the glitch detector 106. Therefore, there is no need to provide complex tracerouting to transmit external glitch test signals to different glitch detectors.
[0029] In some exemplary embodiments, the proposed chip is a system-on-chip (SoC) design and may have more than one embedded processor. The power supply terminals of different processors may each be coupled to a glitch detection module 104 for glitch detection and glitch detection self-testing.
[0030] exist Figure 1 In the process, each glitch detection module 104 has a multiplexer 114 for coupling the power supply terminal VDD_P of the processor 102 to the glitch detector 106 in normal mode, and coupling the self-test glitch signal STsig to the glitch detector 106 in power-glitch self-testing mode.
[0031] The self-test circuit 108 includes a phase-locked loop (PLL) 116, a shift register 118, and a pulse generator 120. The PLL 116 generates a clock signal, for example... Figure 5 The CLK is 500MHz. The glitch controller 112 operates according to the clock signal. Since the PLL 116 is a high-frequency component, the self-test glitch signal STsig generated based on the PLL 116 can be very sharp (e.g., with an extremely short pulse width of 2.5ns to 40.96us), even sharper than the external glitch test signal generated by an external professional glitch amplifier.
[0032] In this example, shift register 118 operates according to a clock signal generated by phase-locked loop 116. Pulse generator 120 is driven by shift register 118 to generate a pulse signal, which is sent to glitch generator 110 to determine the pulse width of self-test glitch signal STsig.
[0033] In an exemplary embodiment, the self-test glitch signal STsig can have different amplitudes. Figure 2 A self-test circuit 200 according to such an exemplary embodiment is depicted.
[0034] The glitch generator 202 includes a voltage divider 204 providing multiple selectable voltages (100%, 50%, or 25% VDD), and multiple switches (SW1, SW2, and SW3) for selecting one of the multiple selectable voltages as the self-test glitch signal STsig. A glitch controller 206 controls the switches (SW1, SW2, and SW3) of the glitch generator 202 such that a pulse signal generated by a phase-locked loop (PLL) 208 based on the glitch controller 206 can turn on the switch corresponding to the selected selectable voltage. The multiple amplitude selections of the self-test glitch signal STsig ensure the sensitivity of the glitch detector 106.
[0035] Figure 3 A self-test circuit 300 with a verification circuit according to an exemplary embodiment of the present invention is depicted.
[0036] The self-test circuit 300 has a frequency meter 302 for monitoring malfunctions in the phase-locked loop (PLL) 304 or shift register 306 within the glitch controller 308.
[0037] The self-test circuit 300 includes a self-testing checker 310. The self-test glitch signal STsig generated by the glitch generator 312 is fed back to the self-testing checker 310 of the glitch controller 308 for verification. When an error occurs in the self-test glitch signal STsig, the glitch controller 308 displays an error flag Err_flag, as shown in the figure. When an error occurs in the self-test glitch signal STsig, the self-testing checker 310 outputs the error flag Err_flag.
[0038] In an exemplary embodiment, the glitch controller 308 may generate a first trigger signal (Trg1) and a second trigger signal (Trg2) dependent on the pulse signal generated by the pulse generator 314 (which is generated to control the pulse width of the self-test glitch signal STsig generated by the glitch generator 312) to detect the rising transition of the inverted signal (STsigB) of the self-test glitch signal STsig and the rising transition of the self-test glitch signal STsig. When the rising transition of the inverted signal STsigB of the self-test glitch signal STsig is detected based on the first trigger signal (Trg1) and the rising transition of the self-test glitch signal STsig is detected based on the second trigger signal (Trg2), the error flag Err_falg is de-asserted to indicate that the self-test glitch signal STsig is operating normally.
[0039] Figure 4 A self-test checker 400 according to an exemplary embodiment of the present invention is depicted, comprising a first D flip-flop DFF_1, a second D flip-flop DFF_2, a third D flip-flop DFF_3, and an AND gate 402. The D terminal of the first D flip-flop DFF_1 receives the inverted signal STsigB of the self-test glitch signal STsig, and its clock terminal receives a first trigger signal Trg1. The D terminal of the second D flip-flop DFF_2 receives the self-test glitch signal STsig, and its clock terminal receives a second trigger signal Trg2. The Q terminals of the first D flip-flop DFF_1 and the second D flip-flop DFF_2 are coupled to the input of the AND gate 402. The D terminal of the third D flip-flop DFF_3 is connected to a high level (TieH), its clock terminal receives the output of the AND gate 402, and its QB terminal displays an error flag Err_falg.
[0040] Figure 5 The diagram illustrates signal waveforms describing the operation of the self-test verifyer 400. The first trigger signal Trg1 and the second trigger signal Trg2 depend on the pulse width of the pulse signal (generated by the pulse generator 314). The time difference between the transition edge (e.g., rising edge) of the first trigger signal Trg1 and the transition edge (e.g., rising edge) of the second trigger signal Trg2 can be equal to the pulse width of the pulse signal. For example, the rising edge of the pulse signal generated by the pulse generator is aligned with the rising edge of the first clock cycle in the clock signal, and the falling edge of the pulse signal generated by the pulse generator is aligned with the rising edge of the second clock cycle in the clock signal. The falling edge of the first clock cycle triggers the generation of the first trigger signal Trg1, and the falling edge of the second clock cycle triggers the generation of the second trigger signal Trg2. For instance, the falling edge of the first clock cycle is aligned with the rising edge of the first trigger signal Trg1, and the falling edge of the second clock cycle is aligned with the rising edge of the second trigger signal Trg2. When the inverted signal STsigB of the self-test glitch signal STsig is high, the Q output of the first D flip-flop DFF_1, based on the rising edge of Trg1, is high. When the self-test glitch signal STsig is high, the Q output of the second D flip-flop DFF_2, based on the rising edge of Trg2, is high. Therefore, the output of AND gate 402 switches high. The error flag Err_falg presented at the QB output of the third D flip-flop DFF_3 is deactivated. This means that the self-test glitch signal STsig is functioning correctly. The pulse width of the self-test glitch signal STsig is set according to the pulse width of the pulse signal.
[0041] In an exemplary embodiment, the chip still has a test pad coupled to the glitch detector 106. Figure 6The safety design of the test pad (Test_pad) is illustrated. A safety switch (Security_SW) is coupled between the test pad (Test_PAD) and the self-test glitch input (also labeled STsig) of multiplexer 114. When the enable signal (EN) of the test pad (Test_PAD) is deactivated to disable the test pad (Test_PAD), the safety switch (Security_SW) prevents external glitch signals from entering through the test pad (Test_PAD).
[0042] Figure 7 A safety switch 700 according to an exemplary embodiment of the present invention is depicted, which has a high voltage (HV) input protection circuit 702 and a low voltage (LV) input protection circuit 704.
[0043] When the use of the Test_PAD is disabled (EN=0), the high voltage input protection circuit 702 prevents high voltage glitch signals (such as signals exceeding the highest threshold (e.g., chip power supply VDD, etc.)) from entering through the Test_PAD.
[0044] The high-voltage input protection circuit 702 includes an inverter Inv1 and a protection transmission gate T1. Inverter Inv1 may include a PMOS and an NMOS, with the gates of the PMOS and NMOS coupled to the input terminal. One end of the PMOS is coupled to the power supply terminal, and the other end of the PMOS is coupled to the NMOS. The input terminal of inverter Inv1 receives an enable signal EN. The power supply terminal of inverter Inv1 is coupled to the test pad Test_PAD via a path control transmission gate Tpc1 controlled by the enable signal EN and its inverted signal ENb. Protection transmission gate T1 is coupled between the power supply terminal of inverter Inv1 and the self-test glitch input STsig of multiplexer 114. Protection transmission gate T1 includes a PMOS and an NMOS, with the two ends of the PMOS coupled to the two ends of the NMOS, respectively. The PMOS of protection transmission gate T1 has a gate controlled by the output of inverter Inv1, and the NMOS of protection transmission gate T1 is controlled by the enable signal EN. The PMOS protecting the transmission gate T1 has a well coupled to the power supply terminal of the inverter Inv1.
[0045] When the test pad Test_PAD is disabled (EN=0 and ENb=1) and a high-voltage glitch signal (e.g., greater than VDD) is coupled to the test pad Test_PAD, the high-voltage glitch signal is coupled to the gate of the PMOS of the protection transmission gate T1 through the PMOS of the inverter Inv1. Therefore, the protection transmission gate T1 is completely turned off. The high-voltage glitch signal is blocked and not transmitted to the self-test glitch input STsig of the multiplexer 114.
[0046] When the use of the Test_PAD is disabled (EN=0), the low-voltage input protection circuit 704 prevents low-voltage glitch signals (e.g., signals below a minimum threshold (e.g., 0V for chip ground)) from entering through the Test_PAD.
[0047] The low-voltage input protection circuit 704 has an inverter Inv2 and a protection transmission gate T2. The input of inverter Inv2 receives the inverted signal ENb of the enable signal EN of test pad Test_PAD, and the ground terminal of inverter Inv2 is coupled to test pad Test_PAD. One end of protection transmission gate T2 is coupled to the ground terminal of inverter Inv2, and the other end is coupled to the self-test glitch input terminal STsig of multiplexer 114 through path control transmission gate Tpc2 (controlled by the enable signal EN and the inverted signal ENb of enable signal EN).
[0048] When the test pad Test_PAD is disabled (EN=0 and ENb=1) and a low-voltage glitch signal (e.g., below 0V) is coupled to the test pad Test_PAD, the low-voltage glitch signal is coupled to the gate of the NMOS of the protection transmission gate T2 through the NMOS of the inverter Inv2. Therefore, the protection transmission gate T2 is completely turned off. The low-voltage glitch signal is blocked and not transmitted to the self-test glitch input STsig of the multiplexer 114.
[0049] like Figure 6 As shown, the IR compensation circuit IR_com is implemented by a variable resistor R. The variable resistor R is coupled between the chip power supply VDD and the self-test glitch input terminal STsig of the multiplexer 114 for IR (voltage) compensation, such as IR compensation for the self-test glitch signal at the self-test glitch input terminal STsig.
[0050] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.
Claims
1. A chip with power glitch detection and power glitch self-test functions, characterized in that, include: The processor has a power supply terminal for receiving power. A glitch detector, coupled to the power supply terminal of the processor, is used to detect power glitch. as well as The self-test circuit includes a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-test glitch signal within the chip to test the glitch detector. The self-test glitch signal is fed back to the glitch controller to check whether the self-test glitch signal has an error. The glitch controller generates a first trigger signal and a second trigger signal based on a pulse signal, and the pulse signal is sent to the glitch generator to determine the pulse width of the self-test glitch signal; The glitch controller has a first D flip-flop, a second D flip-flop, a third D flip-flop, and an AND gate; The first D flip-flop has a D terminal and a clock terminal. The D terminal of the first D flip-flop receives the inverted signal of the self-test glitch signal, and the clock terminal receives the first trigger signal. The second D flip-flop has a D terminal and a clock terminal. The D terminal of the second D flip-flop receives the self-test glitch signal, and the clock terminal receives the second trigger signal. The Q-terminus of the first D flip-flop and the Q-terminus of the second D flip-flop are coupled to the input of the AND gate; and The third D flip-flop has a D terminal, a clock terminal, and a QB terminal. The D terminal of the third D flip-flop is connected to a high level. The clock terminal receives the output of the AND gate. The QB terminal displays an error flag used to present the error of the self-test glitch signal.
2. The chip as described in claim 1, characterized in that, Also includes: The multiplexer couples the power supply terminal of the processor to the glitch detector in normal mode, and couples the self-test glitch signal to the glitch detector in power glitch self-test mode.
3. The chip as described in claim 1 or 2, characterized in that, The glitch controller includes a phase-locked loop that generates a clock signal; and The glitch controller operates according to the clock signal.
4. The chip as described in claim 3, characterized in that, The burr controller includes: A shift register, operated according to a clock signal generated by the phase-locked loop; and A pulse generator is driven by the shift register to generate the pulse signal.
5. The chip as described in claim 4, characterized in that, The glitch generator includes: a voltage divider and multiple switches, the voltage divider providing multiple selectable voltages, and the multiple switches for selecting one of the multiple selectable voltages as the self-test glitch signal; and The burr controller controls the switch of the burr generator to activate a selected switch using the pulse signal, the selected switch being the switch corresponding to a selectable voltage.
6. The chip as described in claim 4, characterized in that, The self-test circuit also includes: A frequency meter is used to monitor for faults in the phase-locked loop or the shift register.
7. The chip as described in claim 1, characterized in that, The burr controller outputs the pulse signal to the burr generator; The glitch controller generates the first trigger signal and the second trigger signal based on the pulse signal to detect the rising transition of the inverted signal of the self-test glitch signal and the rising transition of the self-test glitch signal. When the rising transition of the inverted signal of the self-test glitch signal is detected based on the first trigger signal, and the rising transition of the self-test glitch signal is detected based on the second trigger signal, the error flag is deactivated to indicate that the self-test glitch signal is operating normally.
8. The chip as described in claim 2, characterized in that, Also includes: Test pad; as well as A safety switch is coupled between the test pad and the self-test glitch input terminal of the multiplexer. The self-test glitch signal is coupled to the multiplexer through the self-test glitch input terminal. Specifically, when the enable signal of the test pad is deactivated to disable the test pad, the safety switch prevents external burr signals from entering through the test pad.
9. The chip as described in claim 8, characterized in that, The safety switch includes: A high-voltage input protection circuit prevents high-voltage glitch signals from entering through the test pad when the use of the test pad is disabled, wherein the high-voltage glitch signal is greater than the highest threshold.
10. The chip as described in claim 9, characterized in that, The high-voltage input protection circuit includes: An inverter having an input terminal for receiving the enable signal, wherein the power supply terminal of the inverter is coupled to the test pad via a path control transmission gate, the path control transmission gate being controlled by the enable signal and its inverted signal; and A protection transmission gate is coupled between the power supply terminal of the inverter and the self-test glitch input terminal of the multiplexer. The gate of the PMOS of the protection transmission gate is controlled by the output of the inverter, and the NMOS of the protection transmission gate is controlled by the enable signal.
11. The chip as described in claim 10, characterized in that, The PMOS of the protection transmission gate has a well coupled to the power supply terminal of the inverter.
12. The chip as described in claim 8, characterized in that, The safety switch includes: A low-voltage input protection circuit prevents low-voltage glitch signals from entering through the test pad when the use of the test pad is disabled, wherein the low-voltage glitch signal is below a minimum threshold.
13. The chip as described in claim 12, characterized in that, The low-voltage input protection circuit includes: An inverter having an input terminal that receives an inverted signal of an enable signal from the test pad, wherein the ground terminal of the inverter is coupled to the test pad; and A protection transmission gate is provided, one end of which is coupled to the ground terminal of the inverter, and the other end of which is coupled to the self-test glitch input terminal of the multiplexer via a path control transmission gate. The path control transmission gate is controlled by the enable signal and its inverted signal. The gate of the NMOS of the protection transmission gate is controlled by the output of the inverter, and the PMOS of the protection transmission gate is controlled by the inverted signal of the enable signal.
14. The chip as described in claim 2, characterized in that, Also includes: A variable resistor, coupled between the power supply terminal of the chip and the self-test glitch input terminal of the multiplexer, is used for IR compensation; The self-test glitch signal is coupled to the multiplexer through the self-test glitch input terminal.