Chip with power supply glitch detection function

Abstract

This invention provides a chip with power glitch detection function, comprising a power supply terminal for receiving power supply voltage, an inverter, and a backup power storage device coupled to the power supply terminal. The inverter has an input terminal coupled to the power supply terminal. The backup power storage device converts the power supply voltage into a backup power supply. When a power glitch occurs at the power supply terminal, the inverter is powered by the backup power supply, and the power glitch is reflected at the output terminal of the inverter.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to detection techniques, and more specifically, to power-glitch detection on chips. Background Technology

[0002] Hackers may employ a power-glitch attack, a sophisticated attack designed to confuse chips in electronic devices and reveal their secrets. Typically, a power-glitch attack involves rapidly altering the voltage input to the chip (e.g., intentionally introducing glitches on the chip's power pins), causing the chip's operation to be affected, resulting in skipped instructions or erroneous operations. This allows hidden information within the chip to be leaked as a result of the error.

[0003] Detecting such malicious attacks is a critical issue in system-on-chip (SoC) design. Summary of the Invention

[0004] The following summary is illustrative only and is not intended to be limiting in any way. That is, it provides an overview to introduce the concepts, key points, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Therefore, the following summary is neither intended to identify the essential features of the claimed subject matter nor to define the scope of the claimed subject matter.

[0005] In view of this, the present invention provides a chip with power supply glitch detection function.

[0006] A chip with power glitch detection function includes: a power supply terminal for receiving a power supply voltage; a first inverter having an input terminal coupled to the power supply terminal; and a backup power storage device coupled to the power supply terminal for converting the power supply voltage into a backup power supply; wherein, when a power glitch occurs on the power supply terminal, the first inverter is powered by the backup power supply, and the power glitch is reflected at the output terminal of the first inverter.

[0007] In some embodiments, the backup power storage device includes a resistor and a capacitor connected in series; and the connection between the resistor and the capacitor is coupled to the first inverter to provide backup power to the first inverter in the event of a power glitch.

[0008] In some embodiments, the chip further includes: a latch for presenting a detection result indicating a power glitch, having a positive output terminal that is low before the power glitch and a negative output terminal that is high before the power glitch; and a switch that is turned on when the power glitch is reflected at the output of the first inverter to connect the negative output terminal of the latch to the positive output terminal of the latch; wherein the latch further includes a first capacitor and a second capacitor, the first capacitor coupling the positive output terminal to the power supply terminal after the power glitch to pull up the voltage level of the positive output terminal, and the second capacitor coupling the negative output terminal to ground.

[0009] In some embodiments, when the positive output terminal is high and the negative output terminal is low, it indicates that a power supply glitch has been detected.

[0010] In some embodiments, the chip further includes a latch for presenting a detection result indicating a power supply glitch, and the latch includes: a first PMOS with its source coupled to the power supply terminal; a first NMOS with its drain coupled to the drain of the first PMOS, its gate coupled to the gate of the first PMOS, and its source coupled to ground, wherein the drain of the first PMOS serves as the positive output terminal of the latch; a second PMOS with its source coupled to the power supply terminal; and a second NMOS with its drain coupled to the second PMOS. The drain of S, the gate of the second NMOS is coupled to the gate of the second PMOS, the source of the second NMOS is coupled to the ground terminal, wherein the drain of the second PMOS serves as the negative output terminal of the latch; wherein: the gates of the first PMOS and the first NMOS are connected to the drains of the second PMOS and the second NMOS; the gates of the second PMOS and the second NMOS are connected to the drains of the first PMOS and the first NMOS; and, when the power supply glitches are reflected at the output terminal of the first inverter, the negative output terminal of the latch is connected to the positive output terminal of the latch.

[0011] In some embodiments, the chip further includes a switch (e.g., an NMOS switch) that is turned on when the power supply glitches are reflected at the output of the first inverter, so as to connect the negative output of the latch to the positive output of the latch.

[0012] In some embodiments, the positive output terminal is at a low level before the power glitch; the negative output terminal is at a high level before the power glitch; the latch also has a first capacitor and a second capacitor, the first capacitor coupling the positive output terminal to the power supply terminal after the power glitch to pull up the voltage level of the positive output terminal, and the second capacitor coupling the negative output terminal to the ground terminal.

[0013] In some embodiments, when the positive output terminal is high and the negative output terminal is low, it indicates that a power supply glitch has been detected.

[0014] In some embodiments, the chip further includes: a D flip-flop having a D terminal coupled to the output terminal of the first inverter, a clock terminal coupled to the power supply terminal, and a Q terminal; wherein, when the Q terminal of the D flip-flop is high, it indicates that a power supply glitch is detected.

[0015] In some embodiments, the chip further includes: a second inverter coupled to the first inverter to form a first latch for latching the output of the first inverter; and a reset circuit for resetting the first latch to detect a next power glitch.

[0016] In some embodiments, the reset circuit includes a first reset transistor and a second reset transistor. The first reset transistor is a PMOS, used to disconnect the backup power supply from the first inverter when the reset signal is valid. The second reset transistor is an NMOS, used to connect the output terminal of the first inverter to the ground terminal when the reset signal is valid.

[0017] In some embodiments, the first latch further includes an NMOS having a gate coupled to the output of the second inverter, a drain coupled to the drain of the PMOS of the first inverter, and a source coupled to the drain of the NMOS of the first inverter; and the output of the first inverter is coupled to the input of the second inverter.

[0018] In some embodiments, the chip further includes: a second latch for presenting a detection result indicating a power glitch, having a positive output terminal that is low before the power glitch and a negative output terminal that is high before the power glitch; and a switch that is turned on when the power glitch is reflected at the output of the first inverter to connect the negative output terminal of the latch to the positive output terminal of the latch; wherein the second latch further includes a first capacitor and a second capacitor, the first capacitor coupling the positive output terminal to the power supply terminal after the power glitch to pull up the voltage level of the positive output terminal, and the second capacitor coupling the negative output terminal to ground.

[0019] In some embodiments, when the positive output terminal is high and the negative output terminal is low, it indicates that a power supply glitch has been detected.

[0020] In some embodiments, the chip further includes: a D flip-flop having a D terminal coupled to the output terminal of the first inverter, a clock terminal coupled to the power supply terminal, and a Q terminal; wherein, when the Q terminal of the D flip-flop is high, it indicates that a power supply glitch is detected.

[0021] In some embodiments, the first inverter and the backup power storage device are housed within a single glitch detection unit; the chip is a system-on-a-chip (SoC); and each processor embedded in the SoC has a power supply terminal for receiving power, each power supply terminal being connected to a corresponding glitch detection unit.

[0022] These and other objects of the invention will be readily understood by those skilled in the art upon reading the following detailed description of the preferred embodiments illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings (in which the same numerals denote the same components) illustrate embodiments of the present invention. The included drawings are used to provide a further understanding of embodiments of the present disclosure, and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. It is understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to actual dimensions in order to clearly illustrate the concepts of the embodiments of the present disclosure.

[0024] Figure 1 A chip with a system-on-chip (SoC) design is shown.

[0025] Figure 2 A portion of a GDU (Glitch Detection Unit) is shown, which is a latch 200 used to present the detection results indicating power supply glitch.

[0026] Figure 3 Another important part of each burr detection unit (GDU) is shown, which is used to deterministically pull down the voltage level of the negative output terminal VMB.

[0027] Figure 4 This is a waveform diagram of the signal associated with the burr detection unit (GDU).

[0028] Figure 5 Another circuit is shown that is operated to connect the positive output terminal VM and the negative output terminal VMB in response to a power supply glitch.

[0029] Figure 6 A burr detection unit (GDU) according to another exemplary embodiment is shown.

[0030] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art can more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation

[0031] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0032] Unless otherwise indicated, the corresponding numbers and symbols in the various figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0033] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.

[0034] Figure 1A chip with a System-on-Chip (SoC) design is shown. Chip 100 has one or more processors embedded thereon, such as a central processing unit (CPU), a tensor processing unit (TPU), etc. Each processor has one or more power terminals VDD (which can also be described as "supply voltage") for receiving power (which may also be referred to as "supply voltage"), and each power terminal is coupled to a corresponding glitch detection unit (GDU) for detecting power glitch (which may also be described as "voltage glitch").

[0035] Figure 2 A portion of the GDU (Glass Detection Unit) is shown. Figure 2In the example, the example GDU (Glitch Detection Unit) is a latch 200 used to present the detection results indicating power glitch. The first PMOS (p-type metal-oxide-semiconductor) Mp1 and the first NMOS (n-type metal-oxide-semiconductor) Mn1 form an inverter. The second PMOS Mp2 and the second NMOS Mn2 form another inverter. The source of the first PMOS Mp1 is coupled to the power supply terminal VDD. The drain of the first NMOS Mn1 is coupled to the drain of the first PMOS Mp1 (which serves as the positive output terminal VM of latch 200), the gate of the first NMOS Mn1 is coupled to the gate of the first PMOS Mp1, and the source of the first NMOS Mn1 is coupled to the ground terminal VSS. The source of the second PMOS Mp2 is coupled to the power supply terminal VDD. The drain of the second NMOS Mn2 is coupled to the drain of the second PMOS Mp2 (which serves as the negative output terminal VMB of latch 200), and the second NMOS Mn2... The gate of Mn2 is coupled to the gate of the second PMOS Mp2, and the source of the second NMOS Mn2 is coupled to the ground terminal VSS. The gates of the first PMOS Mp1 and the first NMOS Mn1 are connected to the drains of the second PMOS Mp2 and the second NMOS Mn2. The gates of the second PMOS Mp2 and the second NMOS Mn2 are connected to the drains of the first PMOS Mp1 and the first NMOS Mn1. It should be noted that the present invention does not use uppercase and lowercase references to indicate different designations. For example, in the embodiments of the present invention, VMB and VMb refer to the same thing, both referring to the negative output terminal of the latch.

[0036] Latch 200 may also include a reset design (controlled by a reset signal RST), a set design (controlled by a set signal SET; for example, the set design may be primarily for testing purposes, forcing the output of GDU to 1), and a MOS (metal-oxide-semiconductor) connected to a high-level tieH and acting as a diode. Before a power glitch occurs at the power supply terminal VDD, the positive output terminal VM is at a low level, and the negative output terminal VMB is at a high level. Latch 200 also has a first capacitor C1 that, after a power glitch occurs at the power supply terminal VDD, couples the positive output terminal VM to the power supply terminal VDD, pulling up the voltage level of the positive output terminal VM. Optionally, latch 200 also has a second capacitor C2 that couples the negative output terminal VMB to the ground terminal VSS. When the positive output terminal VM has switched from low to high and the negative output terminal VMB has switched from high to low, it indicates that a power supply glitch has been detected.

[0037] Because the supply voltage (or alternatively, the "supply voltage") of semiconductors is becoming increasingly lower, the discharge capability of a MOS may be too weak to discharge the negative output terminal VMB to a low level in time during the brief duration of a glitch. Power glitch detection may fail. Figure 3 Another important part of each glitch detection unit (GDU) is shown, used to deterministically pull down the voltage level of the negative output terminal VMB.

[0038] like Figure 3 As shown, the glitch detection unit (GDU) also includes a backup power storage device 302, an inverter 304, and a switch (e.g., a switch implemented using NMOS; for ease of explanation and understanding, this embodiment of the invention uses an NMOS switch as an example, but the invention is not limited to this example) 306. In response to the output terminal UV of the inverter 304 reflecting a power glitch on the power supply terminal, the NMOS switch 306 is closed (or can be interchangeably described as "on", "closed", or "closed") to connect the negative output terminal VMB of the latch 200 to (or, can be described as "electrically connected") the positive output terminal VM of the latch 200.

[0039] A backup power supply 302, coupled to the power supply terminal VDD, converts the power from VDD to backup power VR_UV. The input of an inverter 304 is coupled to VDD. When a power glitch occurs on VDD, the inverter 304 is powered by the backup power VR_UV. The power glitch is reflected at the output UV of the inverter 304 (e.g., the output UV of the inverter 304 is high to indicate a power glitch on VDD, such as a downward glitch; understandably, the label UV can also be used to represent an output / (output) signal at the output UV), thereby turning on the NMOS switch 306, and connecting the negative output VMB of the latch 200 to the positive output VM of the latch 200.

[0040] Figure 4 The waveforms of the signals associated with the burr detection unit (GDU) are shown. Figure 2 Compared to the weak discharge capability provided in the embodiment, in Figure 3 In the illustrated embodiment, once a power glitch occurs on the power supply terminal VDD, the inverter 304, powered by the backup power supply VR_UV, can react quickly. The output of the inverter 304's output terminal UV rapidly changes from low to high to turn on the NMOS switch 306, thereby connecting the negative output terminal VMB of the latch 200 to the positive output terminal VM of the latch 200. Therefore, once a power glitch occurs, both the negative output terminal VMB and the positive output terminal VM will be pulled low. After the power glitch passes, Figure 2 The first capacitor C1 in the circuit pulls up the voltage level of the output terminal VM. Therefore, VM at a high level and VMB at a low level correctly indicate the detection of a power supply glitch.

[0041] By Figure 3 In this circuit, the MOS of latch 200 (which is connected to a high level TieH and acts as diodes D1 and D2) is not necessary. In some exemplary embodiments, the MOS acting as diodes D1 and D2 and connected to a high level TieH can be removed from latch 200. That is, by means of Figure 3 The circuit, Figure 2 The MOSFETs used as diodes D1 and D2 are optional.

[0042] In some exemplary embodiments, latch 200 and NMOS switch 306 are optional. For example, power supply glitches can be observed directly from the output / output (UV) terminals of inverter 304. For example, in Figure 3 In the embodiment shown, from Figure 4 The waveform clearly shows that when the output signal (UV) of inverter 304 changes from low to high, it indicates that a power supply glitch has occurred on the power supply terminal VDD.

[0043] exist Figure 3 In this configuration, the backup power storage device 302 has a resistor R and a capacitor C connected in series. The connection between the resistor R and the capacitor C is coupled to an inverter 304 to provide backup power VR_UV to the inverter 304 in the event of a power glitch.

[0044] The backup energy storage device 302, inverter 304, or NMOS switch 306 can be modified.

[0045] Figure 5 Another circuit is shown, operable to connect the positive output terminal VM and the negative output terminal VMB in response to a power supply glitch. Besides the first inverter formed by NMOS Mn and PMOS Mp, Figure 5 A second inverter 502 is also shown. The second inverter 502 is coupled to the first inverter (which includes Mn and Mp) to form a latch for latching the output (UV) of the first inverter. In this way, the output UV is held at its ideal level without being discharged by parasitic components. Thus, the control of the NMOS switch 306 becomes more reliable.

[0046] In order to reset the latch ( Figure 5 To detect the next power supply glitches, this invention proposes a reset circuit. As shown, the reset circuit includes a first reset transistor Mr1 and a second reset transistor Mr2. The first reset transistor Mr1 is a PMOS, used to disconnect the backup power supply VR_UV from the first inverter (Mn and Mp) when the reset signal RST is asserted. The second reset transistor Mr2 is an NMOS, used to connect the output terminal UV of the first inverter to the ground terminal VSS when the reset signal RST is asserted.

[0047] exist Figure 5 In this circuit, the latch also includes an NMOS ML, whose gate is coupled to the output of the second inverter 502, its drain is coupled to the drain of the PMOS Mp of the first inverter, and its source is coupled to the drain of the NMOS Mn of the first inverter. The output terminal UV of the first inverter is coupled to the input terminal of the second inverter 502.

[0048] Figure 6 A burr detection unit (GDU) according to another exemplary embodiment of the present invention is shown. Different from... Figure 5The circuit shown includes a D flip-flop 602, controlled by the output signal UV of a first inverter (comprising Mp and Mn). The D terminal of the D flip-flop 602 is coupled to the output UV of the first inverter (comprising Mp and Mn), the clock terminal of the D flip-flop 602 is coupled to the power supply terminal VDD, and the Q terminal of the D flip-flop 602 outputs a signal VO1. In response to a power glitch, the signal VO1 is asserted (or interchangeably described as "valid," meaning it reflects an event indicating a power glitch is detected). For example, a high Q terminal of the D flip-flop 602 indicates a power glitch has been detected.

[0049] Figure 5 The output signal UV generated in the circuit can be used to control the D flip-flop 602 instead of the NMOS switch 306. That is to say, Figure 5 The NMOS switch in the illustrated embodiment can be replaced with Figure 6 The D flip-flop 602 in the illustrated embodiment.

[0050] The use of ordinal terms such as “first,” “second,” and “third” in the claims to modify claim elements does not in itself indicate any priority, precedence, or order of one claim element relative to another claim element, or the chronological order of the execution of method actions. Rather, it is merely used as a marker to distinguish one claim element with the same name from another claim element with the same name.

[0051] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.

Claims

1. A chip with power supply glitch detection function, characterized in that, include: The power supply terminal is used to receive the power supply voltage. The first inverter has an input terminal coupled to the power supply terminal; as well as, A backup energy storage device, coupled to the power supply terminal, is used to convert the power supply voltage into a backup power supply; When a power glitch occurs at the power supply terminal, the first inverter is powered by the backup power supply, and the power glitch is reflected at the output terminal of the first inverter. The chip also includes: A first latch, used to present the detection result indicating a power glitch, has a positive output terminal that is low before the power glitch and a negative output terminal that is high before the power glitch; and, A switch is turned on when the power glitch is reflected at the output of the first inverter, so as to connect the negative output of the first latch to the positive output of the first latch. The first latch also includes a first capacitor and a second capacitor. The first capacitor couples the positive output terminal to the power supply terminal to pull up the voltage level of the positive output terminal after the power supply glitch, and the second capacitor couples the negative output terminal to the ground terminal.

2. The chip with power supply glitch detection function as described in claim 1, characterized in that: The backup power storage device includes a resistor and a capacitor connected in series; as well as, The connection between the resistor and the capacitor is coupled to the first inverter to provide backup power to the first inverter in the event of a power glitch.

3. The chip with power supply glitch detection function as described in claim 1, characterized in that, The first latch includes: The first PMOS has its source coupled to the power supply terminal; The first NMOS has its drain coupled to the drain of the first PMOS, its gate coupled to the gate of the first PMOS, and its source coupled to ground. The drain of the first PMOS serves as the positive output terminal of the first latch. The second PMOS, whose source is coupled to the power supply terminal; and... The second NMOS has its drain coupled to the drain of the second PMOS, its gate coupled to the gate of the second PMOS, and its source coupled to the ground terminal. The drain of the second PMOS serves as the negative output terminal of the first latch. in: The gates of the first PMOS and the first NMOS are connected to the drains of the second PMOS and the second NMOS; The gates of the second PMOS and the second NMOS are connected to the drains of the first PMOS and the first NMOS.

4. The chip with power supply glitch detection function as described in claim 1, characterized in that, The chip also includes: A second inverter, coupled to the first inverter, forms a second latch for latching the output of the first inverter; and, A reset circuit is used to reset the second latch in order to detect the next power glitches.

5. The chip with power supply glitch detection function as described in claim 4, characterized in that: The reset circuit includes a first reset transistor and a second reset transistor. The first reset transistor is a PMOS, used to disconnect the backup power supply from the first inverter when the reset signal is valid. The second reset transistor is an NMOS, used to connect the output terminal of the first inverter to the ground terminal when the reset signal is valid.

6. The chip with power supply glitch detection function as described in claim 4, characterized in that: The second latch also includes an NMOS, which has a gate coupled to the output of the second inverter, a drain coupled to the drain of the PMOS of the first inverter, and a source coupled to the drain of the NMOS of the first inverter. as well as, The output of the first inverter is coupled to the input of the second inverter.

7. The chip with power supply glitch detection function as described in claim 1, characterized in that: When the positive output terminal is high and the negative output terminal is low, it indicates that a power supply glitch has been detected.

8. The chip with power supply glitch detection function as described in claim 1, characterized in that: The first inverter and the backup power storage device are housed within a single burr detection unit; This chip is a system-on-a-chip; and, Each processor embedded in the system-on-a-chip has a power supply terminal for receiving power, and each power supply terminal is connected to a corresponding glitch detection unit.

9. A chip with power supply glitch detection function, characterized in that, include: The power supply terminal is used to receive the power supply voltage. The first inverter has an input terminal coupled to the power supply terminal; as well as, A backup energy storage device, coupled to the power supply terminal, is used to convert the power supply voltage into a backup power supply; When a power glitch occurs at the power supply terminal, the first inverter is powered by the backup power supply, and the power glitch is reflected at the output terminal of the first inverter. A D flip-flop has a D terminal coupled to the output terminal of the first inverter, a clock terminal coupled to the power supply terminal, and a Q terminal; When the Q output of the D flip-flop is high, it indicates that a power supply glitch has been detected.

10. A chip with power supply glitch detection function, characterized in that, include: The power supply terminal is used to receive the power supply voltage. The first inverter has an input terminal coupled to the power supply terminal; as well as, A backup energy storage device, coupled to the power supply terminal, is used to convert the power supply voltage into a backup power supply; When a power glitch occurs at the power supply terminal, the first inverter is powered by the backup power supply, and the power glitch is reflected at the output terminal of the first inverter. A second inverter, coupled to the first inverter, forms a latch for latching the output of the first inverter; and, A reset circuit is used to reset the latch in order to detect the next power glitches.

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