Time-to-digital conversion method based on single-tube coupled fine delay generation circuit

Abstract

The application discloses a time-to-digital conversion method based on a single-tube coupled fine delay generation circuit, and particularly relates to the technical field of integrated circuits, which comprises measuring rising edges of two signals, start and stop, with a certain time interval through a time-to-digital converter; when there is a fixed phase difference between all inverters and their coupled inputs in a ring oscillator, the oscillation frequency of each ring oscillator is the same; the phase difference between the inverter and the coupled input in each ring oscillator is fixed over time, so that the phase output of the ring oscillator can be equal to the phase output of the previous ring oscillator after experiencing N rings; the fine time generation circuit of the N ring oscillators coupled by a single small-size NMOS tube and the technology of using the same for time-to-digital conversion can avoid the two-loop "competition" phenomenon to a certain extent, completely eliminate the influence of the parasitic capacitance of the PMOS tube, and can obtain a higher ring oscillator oscillation frequency and superior working stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a time-to-digital conversion method based on a single-pipe coupled fine delay generation circuit. BACKGROUND

[0002] High-precision time measurement technology is of great significance in many modern fields, such as laser ranging, astronomical observation, quantum physics, radar positioning, molecular imaging, and the like. The development of national defense technology and industrial technology also puts forward higher and higher requirements for time measurement. Researching the measurement method of fine time interval and further improving the resolution and measurement range of time measurement is one of the hotspots of current research. A time-to-digital converter (TDC) is a commonly used time measurement circuit. It can convert the time domain signal to be measured into a digital signal through time-to-digital conversion technology. A digital code representing the measured time quantity is obtained by processing the digital signal. Through simple operation of the delay unit delay and the digital code value, a measurement time interval with picosecond-level resolution can be obtained. High-resolution TDCs have a wide range of applications in many fields.

[0003] In the prior art, the common method for improving the resolution of a time-to-digital converter is to reduce the minimum delay of a single delay unit. An N-ring oscillator is coupled by a CMOS inverter to generate a fine delay unit by injection locking.

[0004] In the above prior art, the CMOS inverter is used to couple the ring oscillator to generate the minimum delay difference. Since the same size inverter as the ring oscillator is used for coupling, the load of the circuit increases, and the PMOS transistor parasitic capacitance in the inverter affects the oscillation frequency of the entire ring. At the same time, when the number of vertical cascades is greater than the number of inverters in the ring oscillator, the main ring and the auxiliary ring of the oscillator will switch, and the highest oscillation frequency is determined by the vertical cascade, thereby limiting the highest oscillation frequency of the coupled ring oscillator. Limiting the highest oscillation frequency will limit the minimum delay unit delay of the TDC, and thus limit the measurement resolution of the TDC. Since the same size inverters are used for the horizontal main ring and the vertical main ring of the ring oscillator, the competition phenomenon between the two rings will occur when they are disturbed by external interference, thereby causing the system to malfunction.

[0005] The present application is based on the above problems, and proposes a fine time generation circuit based on single tube ring oscillator coupling to perform time-to-digital conversion, which can ensure the number of phases required by time-to-digital conversion, high operation stability, improve the resolution of TDC on a simple TDC structure, and has high linearity and large measurement range while having high resolution.

[0006] To this end, the present application provides a time-to-digital conversion method based on single tube coupled fine delay generation circuit. SUMMARY

[0007] The present application aims to provide a time-to-digital conversion method based on single tube coupled fine delay generation circuit to solve the problems in the background art.

[0008] Term explanation:

[0009] Time-to-Digital Converter (TDC): is an effective means of converting time interval into digital signal. The resolution of TDC is the minimum time interval that can be measured by TDC, which depends on the size of the unit gate delay. The accuracy of TDC measurement can reach picosecond level, and can support continuous measurement and integration;

[0010] Single tube coupling: only a single PMOS or NMOS is used to connect between two systems;

[0011] Fine delay generation circuit: a circuit that can generate sub-gate delay;

[0012] Ring oscillator: is a machine with three or more odd number of inverter output and input connected in a ring. The output of the circuit is two high and low level oscillation. Tau is the minimum delay of a single inverter, and N is the number of inverters in the ring oscillator. The oscillation period T = 2 * tau * N;

[0013] Injection locking: refers to the frequency effect that a ring oscillator is disturbed by another ring oscillator with similar frequency. When the oscillation frequency of the second ring oscillator is close enough to the first ring oscillator, and the coupling between the two ring oscillators is large enough, the first ring oscillator will follow the second ring oscillator. When the balance is reached, the oscillation frequencies of the two are equal.

[0014] To achieve the above object, the present application provides the following technical scheme:

[0015] A time-to-digital conversion method based on single tube coupled fine delay generation circuit, comprising:

[0016] The rising edges of two signals with a certain time interval, start and stop, are measured by a time-to-digital converter, when the start signal reaches the D flip-flop faster than the stop signal, the D flip-flop outputs a high level code value 1, when the start signal reaches the D flip-flop slower than the stop signal, the D flip-flop outputs a low level code value 0, by making the start signal pass through a delay chain composed of a series of delay units, the time when the start signal reaches the D flip-flop in the flip-flop array is gradually slower than the stop signal, and then a series of digital code values are output from the Q end of the D flip-flop, the delay between start and stop is obtained, the time interval to be measured is quantized, and time-to-digital conversion is realized;

[0017] The ring oscillator is based on the ring oscillator structure of M inverters, and the inverters are composed of M1 and M2, wherein the width-length ratio of M2 is twice that of M1,

[0018] Oscillation frequency:

[0019] Delay time: T d = RC tot

[0020] R = R1||R2

[0021] N is the number of oscillator delay unit stages, R is the equivalent impedance of the delay unit output node, R1 is the equivalent impedance of M1, R2 is the equivalent impedance of M2, C tot is the equivalent capacitance of the delay unit output, and its size is:

[0022]

[0023] C tot , C in , C out , C ox , W1, L1, W2 and L2 represent the total capacitance of the delay unit output node, the input capacitance, the output capacitance, the gate oxide capacitance, the width of M1, the length of M1, the width of M2 and the length of M2, respectively, and from the above formula, Ctot∝W1L1+W2L2, because

[0024]

[0025] k1, k2 are process-related quantities and k1≠k2, so we can get:

[0026]

[0027] From the above formula, it can be seen that the delay time Td is independent of the width of M1 and M2, and is closely related to the length of M1 and M2,

[0028] The outputs of the N ring oscillators are coupled by a single NMOS transistor to form a fine delay generation circuit, the NMOS transistor at the output of the top ring is connected to the NMOS transistor below the bottom ring, the width W of the NMOS transistor is the same as that of the M1 transistor in the ring oscillator, the width W of the NMOS transistor used for coupling between the rings is one fourth of the width of the NMOS transistor in the delay unit, when the ring oscillator reaches equilibrium after injection locking, the phase difference between the top ring and the bottom ring is two inverters, that is, 2π, thus the phase difference between each ring from top to bottom is 2π / N, and the delay difference between the rising edges of the outputs of each ring oscillator is T d / N, T d is the delay time of a single inverter, 9 D flip-flops are connected to the outputs of the ring oscillator at the rising edges of the start and stop signals respectively, the sampling results of the D flip-flops are encoded in order according to the phase relationship, two digital codes are obtained, the phase difference x between the start and stop signals in a single inverter period T is obtained by subtracting the two digital codes, the loop counter is used to count the rising edges of the loop outputs after the rising edge of the start signal, and a count value y is obtained, the time interval Ts between the start and stop signals is obtained by the formula: Ts=x*τ+y*T, wherein τ is the phase difference delay, and the quantization of the time interval Ts to be measured by the digital codes x and y is completed.

[0029] Preferably, the delay between the start and stop is defined as T, wherein,

[0030] T=N x *t

[0031] N x is the number of sampling 1, and t is the minimum delay of each delay unit.

[0032] Preferably, the ring oscillator is based on a ring oscillator structure of M inverters, and M is an odd number.

[0033] Compared with the prior art, the beneficial effects of the present application are that the fine time generation circuit of N ring oscillators coupled by a single small-size NMOS transistor and the time-to-digital conversion technology using the same can avoid the "competition" phenomenon between two loops to a certain extent, completely eliminate the influence of the parasitic capacitance of the PMOS transistor, and obtain a higher oscillation frequency of the ring oscillator and superior working stability. The time-to-digital conversion interval obtained by sampling the single jump edge of the fine time generation circuit of the present application by the D flip-flop is smaller, so that the time-to-digital conversion technology in the present application has higher resolution, and thus the time-to-digital converter using the present application has higher resolution. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 This is a schematic diagram of the circuit structure of the time-to-digital converter in the time-to-digital conversion method based on a single-tube coupled fine delay generation circuit of the present invention.

[0035] Figure 2 This is a schematic diagram of the circuit structure of the ring oscillator in the time-to-digital conversion method based on a single-tube coupled fine delay generation circuit according to the present invention.

[0036] Figure 3 This is a schematic diagram of the circuit structure of an N-stage ring oscillator coupled with a single NMOS transistor in an embodiment of the present invention;

[0037] Figure 4 This is the overall time-to-digital conversion structure based on a single-tube coupled fine delay generation circuit in this embodiment of the invention;

[0038] Figure 5 This is a schematic diagram illustrating the principle of time-to-digital conversion in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Please see Figures 1-5 This invention provides a technical solution: a time-to-digital conversion method based on a single-transistor coupled fine delay generation circuit, comprising:

[0041] like Figure 1 As shown, a time-to-digital converter measures the rising edges of two signals, start and stop, with a certain time interval. When the start signal arrives at the D flip-flop before the stop signal, the D flip-flop outputs a high-level code value of 1; when the start signal arrives at the D flip-flop after the stop signal, the D flip-flop outputs a low-level code value of 0. By allowing the start signal to pass through a delay chain composed of a series of delay units, the arrival time of the start signal at the D flip-flop in the flip-flop array gradually becomes slower than that of the stop signal. Consequently, the Q terminal of the D flip-flop outputs a series of digital code values, such as 11110000, to obtain the delay between start and stop, thereby quantifying the measured time interval and realizing time-to-digital conversion. Through this principle analysis, we can know that N and t determine the final result of the time-to-digital conversion technology. Therefore, reducing t can give the time-to-digital conversion a higher resolution. When t is very small, in order to ensure a large measurement range, N also needs to be large, thus requiring a certain number of phases in the circuit.

[0042] The delay between the start and stop is defined as T, wherein,

[0043] T = N x *t

[0044] N x N is the number of samples, and t is the minimum delay of each delay unit.

[0045] The ring oscillator is based on a ring oscillator structure of M inverters, wherein M is an odd number, and the inverters are composed of M1 and M2, wherein the width-to-length ratio of M2 is twice that of M1,

[0046] Oscillation frequency:

[0047] Delay time: T d = RC tot

[0048] R = R1||R2

[0049] R is the equivalent impedance of the output node of the delay unit, R1 is the equivalent impedance of M1, R2 is the equivalent impedance of M2, and C tot is the equivalent capacitance of the output of the delay unit, and its size is:

[0050]

[0051] C tot , C in , C out , C ox , W1, L1, W2, and L2 represent the total capacitance of the output node of the delay unit, the input capacitance, the output capacitance, the gate oxide capacitance, the width of M1, the length of M1, the width of M2, and the length of M2, respectively. From the above formula, we can get: Ctot∝W1L1+W2L2, because

[0052]

[0053] k1 and k2 are process-related quantities and k1≠k2, so we can get:

[0054]

[0055] From the above formula, we can get that the delay time Td is independent of the width of M1 and M2, and is closely related to the length of M1 and M2,

[0056] N fine delay generation circuits composed of the above ring oscillators are coupled through a single NMOS transistor, and the uppermost end Ti is connected to the lower Bi+2, as shown in Figure 3As shown, the width W of the NMOS transistor is the same as M1 in the ring oscillator, but m is one-quarter of the width of M1. When there is a fixed phase difference between all inverters and their coupled inputs in the ring oscillator, since the delay time of the inverters in each ring oscillator is equal, the oscillation frequency of each ring oscillator is the same. This results in the phase difference between the inverters and the coupled inputs in each ring oscillator becoming fixed over time. This ensures that after N rings, the phase output of the ring oscillator is equal to the phase output of the previous ring oscillator. By injecting Ti at the top end and... The bottom output Bi+2 is connected. Based on the above principle, when the ring oscillator reaches equilibrium after injection lock, the phase difference between the top and bottom rings is the phase difference of two inverters, i.e., 2π. Thus, the phase difference between each ring from top to bottom is 2π / N. The delay difference between the rising edges of each ring oscillator output is Td / N, where Td is the delay time of a single inverter. Nine D flip-flops are connected via start and stop to sample each phase output of the ring oscillator. Based on the phase relationship, the D flip-flop sampling results are encoded in the order shown in the figure to obtain two digital codes (e.g., ...). Figure Five (e.g., 1111100000 and 1111000000), subtracting these digital codes yields the phase difference x between the start and stop signals within one inverter cycle T (e.g., ...). Figure Five The loop counter, x = 3 - 4 = -1, counts the rising edge of the loop output after the rising edge of the start signal arrives, obtaining the count value y. The time interval Ts between the start and stop signals can be obtained using the formula: Ts = x * τ + y * T, where y is the phase difference delay. This completes the quantization of the time interval Ts to be measured using digital codes x and y. The coupled transistor is much smaller than the transistor in the ring oscillator, allowing the transverse ring oscillator to dominate the circuit. This reduces the "competition" between the transverse and longitudinal rings, thus improving the overall circuit stability. Single-transistor coupling causes a fine delay, making the output of the circuit insensitive to the falling edge; that is, the falling edge is distorted relative to the normal ring oscillation. However, since the time-to-digital conversion structure only samples the rising edge of the clock, this distortion does not have a significant impact.

[0057] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is not intended to exclude myriad other embodiments of the present application that other inventors can develop based on the same general inventive concepts embodied by the described embodiments. That is, although the present application is described in terms of particular embodiments and illustrative figures, it should be apparent that the scope of the present application is not limited to these specific embodiments.

[0058] While the embodiments of the application have been shown and described herein, it will be understood by those skilled in the art that many changes, modifications, substitutions and alterations to these embodiments can be made without departing from the principles and spirits of the application, and it is intended that the scope of the application be limited solely by the scope of the appended claims and the equivalents thereof.

Claims

1. A time-to-digital conversion method based on a single-transistor coupled fine delay generation circuit, characterized in that, include: The rising edges of two signals, start and stop, with a certain time interval are measured by a time-to-digital converter. When the start signal arrives at the D flip-flop before the stop signal, the D flip-flop outputs a high-level code value of 1. When the start signal arrives at the D flip-flop after the stop signal, the D flip-flop outputs a low-level code value of 0. By allowing the start signal to pass through a delay chain composed of a series of delay units, the arrival time of the start signal at the D flip-flop in the flip-flop array gradually becomes slower than that of the stop signal. Then, a series of digital code values ​​are output from the Q terminal of the D flip-flop to obtain the delay between start and stop, so as to quantify the time interval to be measured and realize the time-to-digital conversion. A ring oscillator is a ring oscillator based on an M-stage inverter, which consists of M1 and M2, where the aspect ratio of M2 is twice that of M1. Oscillation frequency: Delay time of a single inverter: T d =RC tot R = R1||R2 N is the number of oscillator delay unit stages, R is the equivalent impedance of the output node of the delay unit, R1 is the equivalent impedance of transistor M1, R2 is the equivalent impedance of transistor M2, and C... tot The equivalent capacitance of the delay unit output is: C in C out C ox W1, L1, W2, and L2 represent the input capacitance, output capacitance, gate oxide capacitance, M1 transistor width, M1 transistor length, M2 transistor width, and M2 transistor length, respectively. From the above formula, we obtain: C tot ∝W1L1+W2L2, because k1 and k2 are process-related quantities and k1 ≠ k2, therefore we get: From the above formula, we can see that the delay time Td is independent of the widths of M1 and M2, but closely related to the lengths of M1 and M2. The outputs of the N M-level ring oscillators are coupled through a single NMOS transistor to form a fine delay generation circuit. The NMOS transistor at the Ti output of the uppermost ring is connected to Bi+2 below the lowermost ring N. The width W of the NMOS transistor is the same as that of the M1 transistor in the ring oscillator. The width W of the NMOS transistor used for coupling between rings is one-quarter of the width of the NMOS transistor in the delay unit. When the ring oscillator reaches equilibrium after injection lock occurs, the phase difference between the uppermost ring and the lowermost ring is 2π, which is the phase difference between two inverters. Thus, the phase difference between each ring from top to bottom is 2π / N, and the delay difference between the rising edges of each ring oscillator output is T. d / N, nine D flip-flops are connected to the start and stop terminals respectively to sample the output of each phase of the ring oscillator. Based on the phase relationship, the sampling results of the D flip-flops are encoded sequentially to obtain two digital codes. The difference between the two digital codes yields the start and stop signals within one inverter cycle T. d The phase difference x within the loop is used by the loop counter to count the rising edge of the loop output after the rising edge of the start signal arrives, obtaining the count value y, which is obtained through the formula: Ts=x*τ+y * T is the time interval Ts between the start and stop signals, where t is the fine delay T produced after coupling. d / N, which quantizes the time interval Ts to be tested using digital codes x and y.

2. The time-to-digital conversion method based on a single-transistor coupled fine delay generation circuit according to claim 1, characterized in that, The delay between the start and stop is defined as T, where, T=N x *t N x t represents the number of samples of 1, and t represents the minimum delay for each delay unit.

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