Driving circuit, driving method, and display device

Abstract

The application provides a driving circuit, a driving method and a display device. The driving circuit comprises a first node control circuit, a second node control circuit, a third node control circuit, a first output circuit and a second output circuit; the third node control circuit controls the potential of a third node according to a first output control signal; and the second output circuit controls the communication or disconnection between a first output clock signal end and a driving output end under the control of the potential of the third node. Under the control of the first output control signal provided by the first output control end, the driving signal provided by the driving output end is pulled down or pulled up through the first output clock signal end, so as to reduce the falling time or rising time of the driving signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a driving circuit, driving method, and display device. Background Technology

[0002] The application of OLED (Organic Light Emitting Diode) displays has gradually expanded from small and medium-sized watches, mobile phones, and tablets to PCs (Personal Computers) and monitors. These applications are characterized by high PPI (Pixels Per Inch) but high absolute resolution. Due to the diverse usage scenarios faced by PCs, the requirements for refresh rates vary greatly. For example, text reading or power-saving modes generally require refresh rates below 10Hz, while web browsing and video playback require 48Hz to 60Hz. Gaming and other scenarios require refresh rates of 120Hz to 144Hz or even above 240Hz. This necessitates good display performance across refresh rates ranging from a few Hz to 200Hz to 300Hz.

[0003] In related technologies, a pixel structure is employed that separates the threshold voltage compensation and data voltage writing operations. Because this structure separates data voltage writing and threshold voltage compensation, the threshold voltage compensation time can be set to be longer according to display needs (compensation effect, afterimage effect, etc.). The related driving circuit uses an alternating output of off and on voltages for convenient pulse width control. However, an additional bootstrap structure is required to pull the output voltage low or high. Therefore, the falling or rising edge width of the driving method provided by the driving circuit reaches the time of one line, which carries the risk of causing mura (display unevenness). Summary of the Invention

[0004] The main objective of this invention is to provide a driving circuit, driving method, and display device that solves the problem that existing driving circuits require an additional bootstrap structure to pull the output voltage down or up, resulting in a large falling or rising edge of the driving signal provided by the driving circuit, thus causing mura.

[0005] This invention provides a driving circuit, including a first node control circuit, a second node control circuit, a third node control circuit, a first output circuit, a first energy storage circuit, and a second output circuit.

[0006] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0007] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0008] The third node control circuit is electrically connected to the first output control terminal and the third node respectively, and is used to control the potential of the third node according to the first output control signal provided by the first output control terminal;

[0009] The first output circuit is electrically connected to the first node, the second node and the drive output terminal respectively, and is used to control the drive output terminal to output a drive signal under the control of the potential of the first node and the potential of the second node;

[0010] The second output circuit is electrically connected to the third node, the first output clock signal terminal, and the drive output terminal, respectively, and is used to control the connection or disconnection between the first output clock signal terminal and the drive output terminal under the control of the potential of the third node.

[0011] Optionally, the first output control terminal is electrically connected to the reset control signal output terminal of the reset control signal generation circuit;

[0012] The reset control signal generation circuit is electrically connected to the control terminal of the reset circuit in the pixel circuit through the reset control signal output terminal. The reset control signal generation circuit is used to provide a reset control signal to the control terminal of the reset circuit.

[0013] The pixel circuit also includes a driving transistor;

[0014] The reset circuit is electrically connected to the gate of the driving transistor and is used to reset the potential of the gate of the driving transistor under the control of the reset control signal.

[0015] Optionally, the third node control circuit is also electrically connected to the first voltage terminal, and is used to control the connection or disconnection between the first voltage terminal and the third node under the control of the first output control signal.

[0016] Optionally, the third node control circuit is also electrically connected to the first clock signal terminal, and is used to control the connection or disconnection between the third node and the first output control terminal under the control of the first clock signal provided by the first clock signal terminal.

[0017] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first energy storage circuit, a first control circuit, and a second control circuit;

[0018] The first energy storage circuit is electrically connected to the third node and the drive output terminal respectively, and is used to store electrical energy;

[0019] The first control circuit is electrically connected to the second clock signal terminal, the starting voltage terminal, the fourth node, the second voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the starting voltage terminal and the fourth node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection or disconnection between the first node and the second voltage terminal under the control of the potential of the fourth node.

[0020] The second control circuit is electrically connected to the first control node, the third node, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the second voltage terminal under the control of the potential of the first control node.

[0021] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a fourth node control circuit, wherein the second node control circuit includes a second energy storage circuit and a third control circuit.

[0022] The fourth node control circuit is electrically connected to the second control node, the second voltage terminal, the fourth node, and the first clock signal terminal, respectively. It is used to control the connection or disconnection between the fourth node and the second voltage terminal under the control of the potential of the second control node, and to control the connection or disconnection between the fourth node and the first clock signal terminal under the control of the potential of the second node.

[0023] The second energy storage circuit is electrically connected to the fourth node and the second node respectively, and is used to control the potential of the second node according to the potential of the fourth node;

[0024] The third control circuit is electrically connected to the third clock signal terminal, the starting voltage terminal and the first control node respectively, and is used to control the connection or disconnection between the first control node and the starting voltage terminal under the control of the third clock signal provided by the third clock signal terminal.

[0025] The first control node is connected to the second node; or, the driving circuit further includes a first on / off control circuit; the first on / off control circuit is electrically connected to the third voltage terminal, the second node and the first control node respectively, and is used to control the connection or disconnection between the second node and the first control node under the control of the third voltage signal provided by the third voltage terminal.

[0026] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a control node control circuit;

[0027] The control node control circuit is electrically connected to the third clock signal terminal, the first voltage terminal, the second control node, and the first control node, respectively. It is used to control the connection or disconnection between the second control node and the first voltage terminal under the control of the third clock signal provided by the third clock signal terminal, and to control the connection or disconnection between the second control node and the third clock signal terminal under the control of the potential of the first control node.

[0028] Optionally, the first node control circuit is electrically connected to the third control node, the first clock signal terminal, the fourth control node, and the first node, respectively. It is used to control the connection or disconnection between the fourth control node and the first clock signal terminal under the control of the potential of the third control node, and to control the potential of the fourth control node according to the potential of the third control node. Under the control of the first clock signal provided by the first clock signal terminal, it controls the connection or disconnection between the fourth control node and the first node, and is used to maintain the potential of the first node.

[0029] The second control node is connected to the third control node; or...

[0030] The driving circuit further includes a second on / off control circuit; the second on / off control circuit is electrically connected to the fourth voltage terminal, the second control node and the third control node respectively, and is used to control the connection or disconnection between the second control node and the third control node under the control of the fourth voltage signal provided by the fourth voltage terminal.

[0031] Optionally, the third node control circuit includes a first transistor;

[0032] The gate of the first transistor is electrically connected to the first output control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0033] Optionally, the third node control circuit includes a first transistor;

[0034] The gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first output control terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0035] Optionally, the first energy storage circuit includes a first capacitor, and the second output circuit includes a second transistor;

[0036] The gate of the second transistor is electrically connected to the third node, the first terminal of the second transistor is electrically connected to the first output clock signal terminal, and the second terminal of the second transistor is electrically connected to the drive output terminal.

[0037] The first terminal of the first capacitor is electrically connected to the third node, and the second terminal of the first capacitor is electrically connected to the drive output terminal.

[0038] The first control circuit includes a third transistor and a fourth transistor;

[0039] The gate of the third transistor is electrically connected to the second clock signal terminal, the first terminal of the third transistor is electrically connected to the starting voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0040] The gate of the fourth transistor is electrically connected to the fourth node, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0041] The second control circuit includes a fifth transistor;

[0042] The gate of the fifth transistor is electrically connected to the first control node, the first terminal of the fifth transistor is electrically connected to the second voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

[0043] Optionally, the fourth node control circuit includes a sixth transistor and a seventh transistor; the second energy storage circuit includes a second capacitor;

[0044] The gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the first clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the fourth node.

[0045] The gate of the seventh transistor is electrically connected to the second control node, the first terminal of the seventh transistor is electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node;

[0046] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the second node;

[0047] The third control circuit includes an eighth transistor;

[0048] The gate of the eighth transistor is electrically connected to the third clock signal terminal, the first terminal of the eighth transistor is electrically connected to the starting voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first control node.

[0049] The first on / off control circuit includes a ninth transistor;

[0050] The gate of the ninth transistor is electrically connected to the third voltage terminal, the first terminal of the ninth transistor is electrically connected to the first control node, and the second terminal of the ninth transistor is electrically connected to the second node.

[0051] Optionally, the control node control circuit includes a tenth transistor and an eleventh transistor;

[0052] The gate of the tenth transistor is electrically connected to the third clock signal terminal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the second control node.

[0053] The gate of the eleventh transistor is electrically connected to the first control node, the first terminal of the eleventh transistor is electrically connected to the third clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second control node.

[0054] Optionally, the first node control circuit includes a twelfth transistor, a thirteenth transistor, a third capacitor, and a fourth capacitor;

[0055] The gate of the twelfth transistor is electrically connected to the third control node, the first terminal of the twelfth transistor is electrically connected to the first clock signal terminal, and the second terminal of the twelfth transistor is electrically connected to the fourth control node.

[0056] The gate of the thirteenth transistor is electrically connected to the first clock signal terminal, the first terminal of the thirteenth transistor is electrically connected to the fourth control node, and the second terminal of the thirteenth transistor is electrically connected to the first node.

[0057] The first terminal of the third capacitor is electrically connected to the third control node, and the second terminal of the third capacitor is electrically connected to the fourth control node;

[0058] The first terminal of the fourth capacitor is electrically connected to the first node, and the second terminal of the fourth capacitor is electrically connected to the second voltage terminal.

[0059] When the driving circuit further includes a second on / off control circuit, the second on / off control circuit includes a fourteenth transistor;

[0060] The gate of the fourteenth transistor is electrically connected to the fourth voltage terminal, the first terminal of the fourteenth transistor is electrically connected to the second control node, and the second terminal of the fourteenth transistor is electrically connected to the third control node.

[0061] The first output circuit includes a fifteenth transistor and a sixteenth transistor;

[0062] The gate of the fifteenth transistor is electrically connected to the first node, the first terminal of the fifteenth transistor is electrically connected to the second voltage terminal, and the second terminal of the fifteenth transistor is electrically connected to the drive output terminal.

[0063] The gate of the sixteenth transistor is electrically connected to the second node, the first terminal of the sixteenth transistor is electrically connected to the drive output terminal, and the second terminal of the sixteenth transistor is electrically connected to the first voltage terminal.

[0064] This invention also provides a driving method applied to the above-described driving circuit, the driving method comprising:

[0065] The first node control circuit controls the potential of the first node;

[0066] The second node control circuit controls the potential of the second node;

[0067] The third node control circuit controls the potential of the third node according to the first output control signal;

[0068] The first output circuit controls the output of a drive signal at the drive output terminal under the control of the potential of the first node and the potential of the second node.

[0069] The second output circuit, under the control of the potential of the third node, controls the connection or disconnection between the first output clock signal terminal and the drive output terminal.

[0070] This invention also provides a display device including the driving circuit described above.

[0071] In this embodiment of the invention, under the control of the first output control signal provided by the first output control terminal, the drive signal provided by the drive output terminal is pulled down or pulled up through the first output clock signal terminal to reduce the fall time or rise time of the drive signal. Attached Figure Description

[0072] Figure 1 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0073] Figure 2 This is a circuit diagram of at least one embodiment of the reset control signal generation circuit;

[0074] Figure 3 yes Figure 2 The timing diagram of at least one embodiment of the reset control signal generation circuit shown is as follows:

[0075] Figure 4 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0076] Figure 5This is a circuit diagram of at least one embodiment of a pixel circuit;

[0077] Figure 6 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0078] Figure 7 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0079] Figure 8 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0080] Figure 9 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0081] Figure 10 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0082] Figure 11 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0083] Figure 12 This is the present invention. Figure 11 The timing diagram of at least one embodiment of the driving circuit shown;

[0084] Figure 13 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0085] Figure 14 This is the present invention. Figure 13 The timing diagram shows the operation of at least one embodiment of the driving circuit. Detailed Implementation

[0086] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0087] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode, and the other as the second electrode.

[0088] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0089] The driving circuit described in this embodiment of the invention includes a first node control circuit, a second node control circuit, a third node control circuit, a first output circuit, and a second output circuit.

[0090] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0091] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0092] The third node control circuit is electrically connected to the first output control terminal and the third node respectively, and is used to control the potential of the third node according to the first output control signal provided by the first output control terminal;

[0093] The first output circuit is electrically connected to the first node, the second node and the drive output terminal respectively, and is used to control the drive output terminal to output a drive signal under the control of the potential of the first node and the potential of the second node;

[0094] The second output circuit is electrically connected to the third node, the first output clock signal terminal, and the drive output terminal, respectively, and is used to control the connection or disconnection between the first output clock signal terminal and the drive output terminal under the control of the potential of the third node.

[0095] The driving circuit described in this embodiment of the invention employs a third node control circuit and a second output circuit. The third node control circuit controls the potential of the third node according to a first output control signal. Under the control of the potential of the third node, the output circuit controls the connection or disconnection between the first output clock signal terminal and the driving output terminal. Under the control of the first output control signal provided by the first output control terminal, the driving circuit described in this embodiment of the invention pulls down or pulls up the driving signal provided by the driving output terminal through the first output clock signal terminal to reduce the fall time or rise time of the driving signal.

[0096] Optionally, the first energy storage circuit is electrically connected to the third node and the drive output terminal respectively, for storing electrical energy.

[0097] According to one specific embodiment, the third node control circuit is also electrically connected to the first voltage terminal, and is used to control the connection or disconnection between the first voltage terminal and the third node under the control of the first output control signal.

[0098] According to another specific embodiment, the third node control circuit is also electrically connected to the first clock signal terminal, and is used to control the connection or disconnection between the third node and the first output control terminal under the control of the first clock signal provided by the first clock signal terminal.

[0099] like Figure 1 As shown, the driving circuit of at least one embodiment of the present invention includes a first node control circuit 11, a second node control circuit 12, a third node control circuit 13, a first output circuit 14, a first energy storage circuit 15, and a second output circuit 16.

[0100] The first node control circuit 11 is electrically connected to the first node N1 and is used to control the potential of the first node N1;

[0101] The second node control circuit 12 is electrically connected to the second node N2 and is used to control the potential of the second node N2;

[0102] The third node control circuit 13 is electrically connected to the first output control terminal ROUT, the first voltage terminal V1 and the third node N3 respectively, and is used to control the connection or disconnection between the first voltage terminal V1 and the third node N3 under the control of the first output control signal provided by the first output control terminal ROUT.

[0103] The first energy storage circuit 15 is electrically connected to the third node N3 and the drive output terminal AZOUT respectively, and is used to store electrical energy;

[0104] The first output circuit 14 is electrically connected to the first node N1, the second node N2 and the drive output terminal AZOUT respectively, and is used to control the drive output terminal AZOUT to output a drive signal under the control of the potential of the first node N1 and the potential of the second node N2.

[0105] The second output circuit 16 is electrically connected to the third node N3, the first output clock signal terminal CKO1 and the drive output terminal AZOUT, respectively, and is used to control the connection or disconnection between the first output clock signal terminal CKO1 and the drive output terminal AZOUT under the control of the potential of the third node N3.

[0106] Optionally, the first voltage terminal V1 can be a low voltage terminal, but it is not limited to this.

[0107] This invention Figure 1 At least one embodiment of the driving circuit shown, when in operation,

[0108] During the input phase, ROUT provides a first voltage signal. Under the control of the first output control signal provided by ROUT, the third node control circuit 13 controls the connection between the first voltage terminal V1 and the third node N3. Under the control of the potential of the third node N3, the second output circuit 16 controls the connection between the first output clock signal terminal CKO1 and the drive output terminal AZOUT.

[0109] In the first output stage, the second output circuit 16, under the control of the potential of the third node N3, controls the connection between the first output clock signal terminal CKO1 and the drive output terminal AZOUT. The potential of the first output clock signal provided by the first output clock signal terminal CKO1 jumps from the second voltage to the first voltage, so that the potential of the drive signal provided by the drive output terminal AZOUT jumps from the second voltage to the first voltage.

[0110] In at least one embodiment of the present invention, the first voltage may be a low voltage and the second voltage may be a high voltage, but this is not a limitation.

[0111] In at least one embodiment of the present invention, the first output control terminal is electrically connected to the reset control signal output terminal of the reset control signal generation circuit;

[0112] The reset control signal generation circuit is electrically connected to the control terminal of the reset circuit in the pixel circuit through the reset control signal output terminal. The reset control signal generation circuit is used to provide a reset control signal to the control terminal of the reset circuit.

[0113] The pixel circuit also includes a driving transistor;

[0114] The reset circuit is electrically connected to the gate of the driving transistor and is used to reset the potential of the gate of the driving transistor under the control of the reset control signal.

[0115] In a specific implementation, the first output control terminal can be electrically connected to the reset control signal output terminal of the reset control signal generation circuit, and the reset control signal is multiplexed as the first output control signal.

[0116] In actual operation, the reset control signal output terminal can also be electrically connected to the control terminal of the initialization circuit included in the pixel circuit;

[0117] The initialization circuit can be electrically connected to the first electrode of the light-emitting element in the pixel circuit, and is used to initialize the potential of the first electrode of the light-emitting element under the control of the reset control signal, but is not limited thereto.

[0118] like Figure 2 As shown, at least one embodiment of the reset control signal generation circuit may include a first generating transistor T01, a second generating transistor T02, a third generating transistor T03, a fourth generating transistor T04, a fifth generating transistor T05, a sixth generating transistor T06, a seventh generating transistor T07, an eighth generating transistor T08, a first generating capacitor C01, and a second generating capacitor C02.

[0119] The gate of T01 is electrically connected to the first generated clock signal terminal CK, the source of T01 is electrically connected to the start signal terminal STV, and the drain of T01 is electrically connected to the gate of T02.

[0120] The source of T02 is electrically connected to the first generated clock signal terminal CK, and the drain of T02 is electrically connected to the gate of T06.

[0121] The gate of T03 is electrically connected to the first generated clock signal terminal CK, the source of T02 is electrically connected to the low voltage terminal VGL, and the drain of T03 is electrically connected to the gate of T06.

[0122] The gate of T04 is electrically connected to the gate of T06, the source of T04 is electrically connected to the high voltage terminal VGH, and the drain of T04 is electrically connected to the reset control signal output terminal RO.

[0123] The gate of T05 is electrically connected to the drain of T08, the source of T05 is electrically connected to the reset control signal output terminal RO, and the drain of T05 is electrically connected to the second generated clock signal terminal CB.

[0124] The source of T06 is electrically connected to the high voltage terminal VGH, and the drain of T06 is electrically connected to the source of T07.

[0125] The gate of T07 is electrically connected to the second generated clock signal terminal CB, and the drain of T07 is electrically connected to the source of T08.

[0126] The gate of T08 is electrically connected to the low-voltage terminal VGL;

[0127] The first terminal of C01 is electrically connected to the gate of T04, and the second terminal of C01 is electrically connected to the high voltage terminal VGH.

[0128] The first end of C02 is electrically connected to the gate of T05, and the second end of C02 is electrically connected to the reset control signal output terminal RO.

[0129] exist Figure 2 In at least one embodiment of the reset control signal generation circuit shown, all transistors are p-type transistors, but this is not a limitation.

[0130] Figure 3 yes Figure 2 The timing diagram shows the operation of at least one embodiment of the reset control signal generation circuit.

[0131] like Figure 3 As shown, Figure 2 At least one embodiment of the reset control signal generation circuit shown in the diagram, during operation,

[0132] First, STV provides a low voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, T01 is turned on, T08 is turned on, the gate of T05 is connected to a low voltage signal, T05 is turned on, T03 is turned on, T02 is turned on, the gate of T04 is connected to a low voltage signal, T04 is turned on, RO is connected to VGH, RO is connected to CB, and RO outputs a high voltage signal.

[0133] Afterwards, STV provides a high voltage signal, CK provides a high voltage signal, T02 turns on, the gate of T04 is connected to CK, T04 turns off, the gate potential of T05 is maintained at a low voltage, T05 turns on, and when CB provides a low voltage signal, RO outputs a low voltage signal.

[0134] Subsequently, STV provides a high voltage signal, CK provides a low voltage signal, T03 turns on, the gate potential of T04 becomes low, T04 turns on, and RO outputs a high voltage signal. Figure 4 As shown, the driving circuit of at least one embodiment of the present invention includes a first node control circuit 11, a second node control circuit 12, a third node control circuit 13, a first output circuit 14, a first energy storage circuit 15, and a second output circuit 16.

[0135] The first node control circuit 11 is electrically connected to the first node N1 and is used to control the potential of the first node N1;

[0136] The second node control circuit 12 is electrically connected to the second node N2 and is used to control the potential of the second node N2;

[0137] The third node control circuit 13 is electrically connected to the first output control terminal ROUT, the first clock signal terminal CK1 and the third node N3 respectively, and is used to control the connection or disconnection between the third node N3 and the first output control terminal ROUT under the control of the first clock signal provided by the first clock signal terminal CK1.

[0138] The first energy storage circuit 15 is electrically connected to the third node N3 and the drive output terminal AZOUT respectively, and is used to store electrical energy;

[0139] The first output circuit 14 is electrically connected to the first node N1, the second node N2 and the drive output terminal AZOUT respectively, and is used to control the drive output terminal AZOUT to output a drive signal under the control of the potential of the first node N1 and the potential of the second node N2.

[0140] The second output circuit 16 is electrically connected to the third node N3, the first output clock signal terminal CKO1 and the drive output terminal AZOUT, respectively, and is used to control the connection or disconnection between the first output clock signal terminal CKO1 and the drive output terminal AZOUT under the control of the potential of the third node N3.

[0141] Optionally, the first voltage terminal V1 can be a low voltage terminal, but it is not limited to this.

[0142] This invention Figure 4 At least one embodiment of the driving circuit shown, when in operation,

[0143] During the input phase, ROUT provides a first voltage signal. Under the control of the first clock signal provided by the first clock signal terminal CK1, the third node control circuit 13 controls the connection between the third node N3 and the first output control terminal ROUT. Under the control of the potential of the third node N3, the second output circuit 16 controls the connection between the first output clock signal terminal CKO1 and the drive output terminal AZOUT.

[0144] In the first output stage, the second output circuit 16, under the control of the potential of the third node N3, controls the connection between the first output clock signal terminal CKO1 and the drive output terminal AZOUT. The potential of the first output clock signal provided by the first output clock signal terminal CKO1 jumps from the second voltage to the first voltage, so that the potential of the drive signal provided by the drive output terminal AZOUT jumps from the second voltage to the first voltage.

[0145] In related technologies, data writing and threshold voltage compensation are performed by the same circuit structure. This results in the inability to fully compensate for the threshold voltage within a very short line time (high-frequency frames). Simultaneously, the non-uniformity of the driving transistor characteristics amplifies the impact on pixel data writing, leading to a significant degradation in display quality. Therefore, alternative threshold voltage compensation methods are needed to improve the accuracy of pixel data writing and the threshold voltage compensation time, thereby enhancing image quality. To address these issues, a pixel structure that separates threshold voltage compensation and data voltage writing is adopted. Because this pixel structure separates data voltage writing and threshold voltage compensation, the threshold voltage compensation time can be set to be longer according to display needs (compensation effect, image retention effect, etc.).

[0146] like Figure 5As shown, at least one embodiment of the pixel circuit may include an organic light-emitting diode O1, a first display control transistor M1, a second display control transistor M2, a third display control transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a ninth display control transistor M9, a first display control capacitor Cx1, and a second display control capacitor Cx2.

[0147] The gate of M1 is electrically connected to the first output control terminal ROUT, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the first display control node.

[0148] The gate of M2 is electrically connected to the drive output terminal AZOUT, and the source of M2 is electrically connected to the first display control node.

[0149] The gate of M3 is electrically connected to the first display control node, the source of M3 is electrically connected to the high-level terminal VDD, and the drain of M3 is electrically connected to the drain of M2.

[0150] The gate of M4 is electrically connected to the light-emitting control terminal EOUT, the source of M4 is electrically connected to the drain of M3, the drain of M4 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal VSS.

[0151] The gate of M5 is electrically connected to the first output control terminal ROUT, the source of M5 is electrically connected to the high-level terminal VDD, and the drain of M5 is electrically connected to the second display control node.

[0152] The gate of M6 is electrically connected to the drive output terminal AZOUT, the source of M6 is electrically connected to the high-level terminal VDD, and the drain of M6 is electrically connected to the second display control node.

[0153] The gate of M7 is electrically connected to the scan terminal GOUT, the source of M7 is connected to the data voltage Vdt, and the drain of M7 is connected to the third display control node.

[0154] The gate of M8 is electrically connected to the light-emitting control terminal, the source of M8 is connected to the reference voltage Vref, and the drain of M8 is electrically connected to the third display control node.

[0155] The first end of the first display control capacitor Cx1 is electrically connected to the first display control node, and the second end of the first display control capacitor Cx1 is electrically connected to the second display control node;

[0156] The first end of the second display control capacitor Cx2 is electrically connected to the second display control node, and the second end of the second display control capacitor Cx2 is electrically connected to the third display control node.

[0157] exist Figure 5In at least one embodiment of the pixel circuit shown, all transistors may be p-type transistors, but are not limited thereto.

[0158] exist Figure 5 In at least one embodiment of the pixel circuit shown, M1 may be a transistor included in the reset circuit of the pixel circuit, and M9 may be a transistor included in the initialization circuit of the pixel circuit, but is not limited thereto.

[0159] Figure 6 for Figure 5 The timing diagram shows the operation of at least one embodiment of the pixel circuit.

[0160] Figure 5 In at least one embodiment of the pixel circuit shown, threshold voltage compensation is controlled by AZOUT and data voltage writing is controlled by GOUT during operation.

[0161] exist Figure 5 In at least one embodiment of the pixel circuit shown, T2 can be a p-type transistor, and the low-voltage pulse time of the drive signal provided by the drive output terminal AZOUT needs to be adjustable. Traditional drive circuits use an alternating output of the turn-off voltage and the turn-on voltage Vgl because it is convenient to control the pulse width. However, since the voltage at the gate of the output transistor is also the turn-on voltage Vgl when the turn-on voltage Vgl is output, the limit of the output voltage is Vgl-Vth, where Vth is the threshold voltage of the output transistor. Therefore, it is impossible to reduce the output voltage to Vgl within one line time. An additional pull-down bootstrap structure is required to pull the output voltage down to Vgl. As a result, the falling edge width reaches the time of one line, which poses a risk of mura (display inhomogeneity).

[0162] Based on this, in this embodiment of the invention, the first output control terminal ROUT controls the potential of the third node, and then the second output circuit, under the control of the potential of the third node, controls the connection or disconnection between the first output clock signal terminal and the drive output terminal, thereby pulling down the potential of the drive signal provided by the drive output terminal AZOUT, reducing the fall time of the drive signal, and enabling the pulse width of the drive signal to be adjustable.

[0163] The driving circuit described in at least one embodiment of the present invention further includes a first control circuit;

[0164] The first control circuit is electrically connected to the second clock signal terminal, the starting voltage terminal, the fourth node, the second voltage terminal, and the first node, respectively. It is used to control the connection or disconnection between the starting voltage terminal and the fourth node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection or disconnection between the first node and the second voltage terminal under the control of the potential of the fourth node.

[0165] In a specific implementation, the driving circuit may further include a first control circuit. Under the control of the second clock signal, the first control circuit controls the connection or disconnection between the starting voltage terminal and the fourth node. Under the control of the potential of the fourth node, it controls the connection or disconnection between the first node and the second voltage terminal to control the potential of the first node.

[0166] Optionally, the second voltage terminal can be a high voltage terminal, but is not limited thereto.

[0167] like Figure 7 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first control circuit 41;

[0168] The first control circuit 41 is electrically connected to the second clock signal terminal CK2, the starting voltage terminal AZSTV, the fourth node N4, the second voltage terminal V2, and the first node N1, respectively. It is used to control the connection or disconnection between the starting voltage terminal AZSTV and the fourth node N4 under the control of the second clock signal provided by the second clock signal terminal CK2, and to control the connection or disconnection between the first node N1 and the second voltage terminal V2 under the control of the potential of the fourth node N4.

[0169] like Figure 8 As shown, in Figure 4 Based on the embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first control circuit 41;

[0170] The first control circuit 41 is electrically connected to the second clock signal terminal CK2, the starting voltage terminal AZSTV, the fourth node N4, the second voltage terminal V2, and the first node N1, respectively. It is used to control the connection or disconnection between the starting voltage terminal AZSTV and the fourth node N4 under the control of the second clock signal provided by the second clock signal terminal CK2, and to control the connection or disconnection between the first node N1 and the second voltage terminal V2 under the control of the potential of the fourth node N4.

[0171] The driving circuit described in at least one embodiment of the present invention further includes a second control circuit;

[0172] The second control circuit is electrically connected to the first control node, the third node, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the second voltage terminal under the control of the potential of the first control node.

[0173] In a specific implementation, the driving circuit may further include a second control circuit. Under the control of the potential of the first control node, the second control circuit controls the connection or disconnection between the third node and the second voltage terminal to control the potential of the third node.

[0174] In at least one embodiment of the present invention, the driving circuit further includes a fourth node control circuit, and the second node control circuit includes a second energy storage circuit.

[0175] The fourth node control circuit is electrically connected to the second control node, the second voltage terminal, the fourth node, and the first clock signal terminal, respectively. It is used to control the connection or disconnection between the fourth node and the second voltage terminal under the control of the potential of the second control node, and to control the connection or disconnection between the fourth node and the first clock signal terminal under the control of the potential of the second node.

[0176] The second energy storage circuit is electrically connected to the fourth node and the second node respectively, and is used to control the potential of the second node according to the potential of the fourth node.

[0177] In a specific implementation, the driving circuit may further include a fourth node control circuit, and the second node control circuit may further include a second energy storage circuit and a third control circuit. Under the control of the potential of the second control node, the fourth node control circuit controls the connection or disconnection between the fourth node and the second voltage terminal, and under the control of the potential of the second node, controls the connection or disconnection between the fourth node and the first clock signal terminal. The second energy storage circuit controls the potential of the second node according to the potential of the fourth node.

[0178] In at least one embodiment of the present invention, the second node control circuit may further include a third control circuit;

[0179] The third control circuit is electrically connected to the third clock signal terminal, the starting voltage terminal and the first control node respectively, and is used to control the connection or disconnection between the first control node and the starting voltage terminal under the control of the third clock signal provided by the third clock signal terminal.

[0180] The first control node is connected to the second node; or, the driving circuit further includes a first on / off control circuit; the first on / off control circuit is electrically connected to the third voltage terminal, the second node and the first control node respectively, and is used to control the connection or disconnection between the second node and the first control node under the control of the third voltage signal provided by the third voltage terminal.

[0181] In a specific implementation, the second node control circuit may further include a third control circuit. Under the control of a third clock signal, the third control circuit controls the connection or disconnection between the first control node and the starting voltage terminal to control the potential of the second node.

[0182] The driving circuit described in at least one embodiment of the present invention further includes a control node control circuit;

[0183] The control node control circuit is electrically connected to the third clock signal terminal, the first voltage terminal, the second control node, and the first control node, respectively. It is used to control the connection or disconnection between the second control node and the first voltage terminal under the control of the third clock signal provided by the third clock signal terminal, and to control the connection or disconnection between the second control node and the third clock signal terminal under the control of the potential of the first control node.

[0184] In a specific implementation, the driving circuit may further include a control node control circuit. Under the control of a third clock signal, the control node control circuit controls the connection or disconnection between the second control node and the first voltage terminal, and under the control of the potential of the first control node, controls the connection or disconnection between the second control node and the third clock signal terminal.

[0185] Optionally, the first node control circuit is electrically connected to the third control node, the first clock signal terminal, the fourth control node, and the first node, respectively. It is used to control the connection or disconnection between the fourth control node and the first clock signal terminal under the control of the potential of the third control node, and to control the potential of the fourth control node according to the potential of the third control node. Under the control of the first clock signal provided by the first clock signal terminal, it controls the connection or disconnection between the fourth control node and the first node, and is used to maintain the potential of the first node.

[0186] In specific implementation, the first node control circuit, under the control of the potential of the third control node, controls the connection or disconnection between the fourth control node and the first clock signal terminal, controls the potential of the fourth control node according to the potential of the third control node, controls the connection or disconnection between the fourth control node and the first node under the control of the first clock signal, and maintains the potential of the first node.

[0187] In at least one embodiment of the present invention, the second control node and the third control node are connected; or...

[0188] The driving circuit further includes a second on / off control circuit; the second on / off control circuit is electrically connected to the fourth voltage terminal, the second control node and the third control node respectively, and is used to control the connection or disconnection between the second control node and the third control node under the control of the fourth voltage signal provided by the fourth voltage terminal.

[0189] Optionally, the third voltage terminal and the fourth voltage terminal can be low voltage terminals, but are not limited thereto.

[0190] like Figure 9 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a second control circuit 50 and a fourth node control circuit 51;

[0191] The second control circuit 50 is electrically connected to the first control node NC1, the third node N3, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the third node N3 and the second voltage terminal V2 under the control of the potential of the first control node NC1.

[0192] The fourth node control circuit 51 is electrically connected to the second control node NC2, the second voltage terminal V2, the fourth node N4 and the first clock signal terminal CK1 respectively. It is used to control the connection or disconnection between the fourth node N4 and the second voltage terminal V2 under the control of the potential of the second control node NC2, and to control the connection or disconnection between the fourth node N4 and the first clock signal terminal CK1 under the control of the potential of the second node N2.

[0193] The second node control circuit also includes a second energy storage circuit 60 and a third control circuit 52;

[0194] The second energy storage circuit 60 is electrically connected to the fourth node N4 and the second node N2 respectively, and is used to control the potential of the second node N2 according to the potential of the fourth node N4;

[0195] The third control circuit 52 is electrically connected to the third clock signal terminal CK3, the starting voltage terminal AZSTV and the first control node NC1 respectively, and is used to control the connection or disconnection between the first control node NC1 and the starting voltage terminal AZSTV under the control of the third clock signal provided by the third clock signal terminal CK3.

[0196] The driving circuit described in at least one embodiment of the present invention further includes a first on / off control circuit 53;

[0197] The first on / off control circuit 53 is electrically connected to the third voltage terminal V3, the second node N2 and the first control node NC1 respectively, and is used to control the connection or disconnection between the second node N2 and the first control node NC1 under the control of the third voltage signal provided by the third voltage terminal V3.

[0198] The driving circuit described in at least one embodiment of the present invention further includes a control node control circuit 54;

[0199] The control node control circuit 54 is electrically connected to the third clock signal terminal CK3, the first voltage terminal V1, the second control node NC2, and the first control node NC1, respectively. It is used to control the connection or disconnection between the second control node NC2 and the first voltage terminal V1 under the control of the third clock signal provided by the third clock signal terminal CK3, and to control the connection or disconnection between the second control node NC2 and the third clock signal terminal CK3 under the control of the potential of the first control node NC1.

[0200] The first node control circuit 11 is electrically connected to the third control node NC3, the first clock signal terminal CK1, the fourth control node NC4, and the first node N1, respectively. It is used to control the connection or disconnection between the fourth control node NC4 and the first clock signal terminal CK1 under the control of the potential of the third control node NC3, and to control the potential of the fourth control node NC4 according to the potential of the third control node NC3. Under the control of the first clock signal provided by the first clock signal terminal CK1, it controls the connection or disconnection between the fourth control node NC4 and the first node N1, and is used to maintain the potential of the first node N1.

[0201] The driving circuit described in at least one embodiment of the present invention further includes a second on / off control circuit 55;

[0202] The second on / off control circuit 55 is electrically connected to the fourth voltage terminal V4, the second control node NC2 and the third control node NC3 respectively, and is used to control the connection or disconnection between the second control node NC2 and the third control node NC3 under the control of the fourth voltage signal provided by the fourth voltage terminal V4.

[0203] like Figure 10 As shown, in Figure 8Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a fourth node control circuit 51; the fourth node control circuit 51 is electrically connected to the second control node NC2, the second voltage terminal V2, the fourth node N4 and the first clock signal terminal CK1 respectively, and is used to control the fourth node N4 to connect or disconnect from the second voltage terminal V2 under the control of the potential of the second control node NC2, and to control the fourth node N4 to connect or disconnect from the first clock signal terminal CK1 under the control of the potential of the second node N2;

[0204] The second node control circuit also includes a second energy storage circuit 60 and a third control circuit 52;

[0205] The second energy storage circuit 60 is electrically connected to the fourth node N4 and the second node N2 respectively, and is used to control the potential of the second node N2 according to the potential of the fourth node N4;

[0206] The third control circuit 52 is electrically connected to the third clock signal terminal CK3, the starting voltage terminal AZSTV and the first control node NC1 respectively, and is used to control the connection or disconnection between the first control node NC1 and the starting voltage terminal AZSTV under the control of the third clock signal provided by the third clock signal terminal CK3.

[0207] The driving circuit described in at least one embodiment of the present invention further includes a first on / off control circuit 53;

[0208] The first on / off control circuit 53 is electrically connected to the third voltage terminal V3, the second node N2 and the first control node NC1 respectively, and is used to control the connection or disconnection between the second node N2 and the first control node NC1 under the control of the third voltage signal provided by the third voltage terminal V3.

[0209] The driving circuit described in at least one embodiment of the present invention further includes a control node control circuit 54;

[0210] The control node control circuit 54 is electrically connected to the third clock signal terminal CK3, the first voltage terminal V1, the second control node NC2, and the first control node NC1, respectively. It is used to control the connection or disconnection between the second control node NC2 and the first voltage terminal V1 under the control of the third clock signal provided by the third clock signal terminal CK3, and to control the connection or disconnection between the second control node NC2 and the third clock signal terminal CK3 under the control of the potential of the first control node NC1.

[0211] The first node control circuit 11 is electrically connected to the third control node NC3, the first clock signal terminal CK1, the fourth control node NC4, and the first node N1, respectively. It is used to control the connection or disconnection between the fourth control node NC4 and the first clock signal terminal CK1 under the control of the potential of the third control node NC3, and to control the potential of the fourth control node NC4 according to the potential of the third control node NC3. Under the control of the first clock signal provided by the first clock signal terminal CK1, it controls the connection or disconnection between the fourth control node NC4 and the first node N1, and is used to maintain the potential of the first node N1.

[0212] The driving circuit described in at least one embodiment of the present invention further includes a second on / off control circuit 55;

[0213] The second on / off control circuit 55 is electrically connected to the fourth voltage terminal V4, the second control node NC2 and the third control node NC3 respectively, and is used to control the connection or disconnection between the second control node NC2 and the third control node NC3 under the control of the fourth voltage signal provided by the fourth voltage terminal V4.

[0214] Optionally, the third node control circuit includes a first transistor;

[0215] The gate of the first transistor is electrically connected to the first output control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0216] Optionally, the third node control circuit includes a first transistor;

[0217] The gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first output control terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0218] Optionally, the first energy storage circuit includes a first capacitor, and the second output circuit includes a second transistor;

[0219] The gate of the second transistor is electrically connected to the third node, the first terminal of the second transistor is electrically connected to the first output clock signal terminal, and the second terminal of the second transistor is electrically connected to the drive output terminal.

[0220] The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the drive output terminal.

[0221] Optionally, the first control circuit includes a third transistor and a fourth transistor;

[0222] The gate of the third transistor is electrically connected to the second clock signal terminal, the first terminal of the third transistor is electrically connected to the starting voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0223] The gate of the fourth transistor is electrically connected to the fourth node, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0224] Optionally, the second control circuit includes a fifth transistor;

[0225] The gate of the fifth transistor is electrically connected to the first control node, the first terminal of the fifth transistor is electrically connected to the second voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

[0226] Optionally, the fourth node control circuit includes a sixth transistor and a seventh transistor; the second energy storage circuit includes a second capacitor;

[0227] The gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the first clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the fourth node.

[0228] The gate of the seventh transistor is electrically connected to the second control node, the first terminal of the seventh transistor is electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node;

[0229] The first end of the second capacitor is electrically connected to the fourth node, and the second end of the second capacitor is electrically connected to the second node.

[0230] Optionally, the third control circuit includes an eighth transistor;

[0231] The gate of the eighth transistor is electrically connected to the third clock signal terminal, the first terminal of the eighth transistor is electrically connected to the starting voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first control node.

[0232] The first on / off control circuit includes a ninth transistor;

[0233] The gate of the ninth transistor is electrically connected to the third voltage terminal, the first terminal of the ninth transistor is electrically connected to the first control node, and the second terminal of the ninth transistor is electrically connected to the second node.

[0234] Optionally, the control node control circuit includes a tenth transistor and an eleventh transistor;

[0235] The gate of the tenth transistor is electrically connected to the third clock signal terminal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the second control node.

[0236] The gate of the eleventh transistor is electrically connected to the first control node, the first terminal of the eleventh transistor is electrically connected to the third clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second control node.

[0237] Optionally, the first node control circuit includes a twelfth transistor, a thirteenth transistor, a third capacitor, and a fourth capacitor;

[0238] The gate of the twelfth transistor is electrically connected to the third control node, the first terminal of the twelfth transistor is electrically connected to the first clock signal terminal, and the second terminal of the twelfth transistor is electrically connected to the fourth control node.

[0239] The gate of the thirteenth transistor is electrically connected to the first clock signal terminal, the first terminal of the thirteenth transistor is electrically connected to the fourth control node, and the second terminal of the thirteenth transistor is electrically connected to the first node.

[0240] The first terminal of the third capacitor is electrically connected to the third control node, and the second terminal of the third capacitor is electrically connected to the fourth control node;

[0241] The first terminal of the fourth capacitor is electrically connected to the first node, and the second terminal of the fourth capacitor is electrically connected to the second voltage terminal.

[0242] Optionally, the second on / off control circuit includes a fourteenth transistor;

[0243] The gate of the fourteenth transistor is electrically connected to the fourth voltage terminal, the first terminal of the fourteenth transistor is electrically connected to the second control node, and the second terminal of the fourteenth transistor is electrically connected to the third control node.

[0244] Optionally, the first output circuit includes a fifteenth transistor and a sixteenth transistor;

[0245] The gate of the fifteenth transistor is electrically connected to the first node, the first terminal of the fifteenth transistor is electrically connected to the second voltage terminal, and the second terminal of the fifteenth transistor is electrically connected to the drive output terminal.

[0246] The gate of the sixteenth transistor is electrically connected to the second node, the first terminal of the sixteenth transistor is electrically connected to the drive output terminal, and the second terminal of the sixteenth transistor is electrically connected to the first voltage terminal.

[0247] like Figure 11 As shown, in Figure 9 Based on at least one embodiment of the driving circuit shown,

[0248] The third node control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, and the second output circuit includes a second transistor T2.

[0249] The gate of the first transistor T1 is electrically connected to the first output control terminal ROUT, the source of the first transistor T1 is electrically connected to the low voltage terminal VGL, and the drain of the first transistor T1 is electrically connected to the third node N3.

[0250] The gate of the second transistor T2 is electrically connected to the third node N3, the source of the second transistor T2 is electrically connected to the first output clock signal terminal CKO1, and the drain of the second transistor T2 is electrically connected to the drive output terminal AZOUT.

[0251] The first terminal of the first capacitor C1 is electrically connected to the third node N3, and the second terminal of the first capacitor C1 is electrically connected to the drive output terminal AZOUT.

[0252] The first control circuit includes a third transistor T3 and a fourth transistor T4;

[0253] The gate of the third transistor T3 is electrically connected to the second clock signal terminal CK2, the source of the third transistor T3 is electrically connected to the starting voltage terminal AZSTV, and the drain of the third transistor T3 is electrically connected to the fourth node N4.

[0254] The gate of the fourth transistor T4 is electrically connected to the fourth node N4, the source of the fourth transistor T4 is electrically connected to the high voltage terminal VGH, and the drain of the fourth transistor T4 is electrically connected to the first node N1.

[0255] The second control circuit includes a fifth transistor T5;

[0256] The gate of the fifth transistor T5 is electrically connected to the first control node NC1, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the third node N3.

[0257] The fourth node control circuit includes a sixth transistor T6 and a seventh transistor T7; the second energy storage circuit includes a second capacitor C2.

[0258] The gate of the sixth transistor T6 is electrically connected to the second node N2, the source of the sixth transistor T6 is electrically connected to the first clock signal terminal CK1, and the drain of the sixth transistor T6 is electrically connected to the fourth node N4.

[0259] The gate of the seventh transistor T7 is electrically connected to the second control node NC2, the source of the seventh transistor T7 is electrically connected to the high voltage terminal VGH, and the drain of the seventh transistor T7 is electrically connected to the fourth node N4.

[0260] The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the second node N2;

[0261] The third control circuit includes an eighth transistor T8;

[0262] The gate of the eighth transistor T8 is electrically connected to the third clock signal terminal CK3, the source of the eighth transistor T8 is electrically connected to the starting voltage terminal AZSTV, and the drain of the eighth transistor T8 is electrically connected to the first control node NC1.

[0263] The first on / off control circuit includes a ninth transistor T9;

[0264] The gate of the ninth transistor T9 is electrically connected to the low voltage terminal VGL, the source of the ninth transistor T9 is electrically connected to the first control node NC1, and the drain of the ninth transistor T9 is electrically connected to the second node N2.

[0265] The control node control circuit includes a tenth transistor T10 and an eleventh transistor T11;

[0266] The gate of the tenth transistor T10 is electrically connected to the third clock signal terminal CK3, the source of the tenth transistor T10 is electrically connected to the low voltage terminal VGL, and the drain of the tenth transistor T10 is electrically connected to the second control node NC2.

[0267] The gate of the eleventh transistor T11 is electrically connected to the first control node NC1, the source of the eleventh transistor T11 is electrically connected to the third clock signal terminal CK3, and the drain of the eleventh transistor T11 is electrically connected to the second control node NC2.

[0268] The first node control circuit includes a twelfth transistor T12, a thirteenth transistor T13, a third capacitor C3, and a fourth capacitor C4;

[0269] The gate of the twelfth transistor T12 is electrically connected to the third control node NC3, the source of the twelfth transistor T12 is electrically connected to the first clock signal terminal CK1, and the drain of the twelfth transistor T12 is electrically connected to the fourth control node NC4.

[0270] The gate of the thirteenth transistor T13 is electrically connected to the first clock signal terminal CK1, the source of the thirteenth transistor T13 is electrically connected to the fourth control node NC4, and the drain of the thirteenth transistor T13 is electrically connected to the first node N1.

[0271] The first terminal of the third capacitor C3 is electrically connected to the third control node NC3, and the second terminal of the third capacitor C3 is electrically connected to the fourth control node NC4.

[0272] The first terminal of the fourth capacitor C4 is electrically connected to the first node N1, and the second terminal of the fourth capacitor C4 is electrically connected to the high voltage terminal VGH.

[0273] The second on / off control circuit includes a fourteenth transistor T14;

[0274] The gate of the fourteenth transistor T14 is electrically connected to the low voltage terminal VGL, the source of the fourteenth transistor T14 is electrically connected to the second control node NC2, and the drain of the fourteenth transistor T14 is electrically connected to the third control node NC3.

[0275] The first output circuit includes a fifteenth transistor T15 and a sixteenth transistor T16;

[0276] The gate of the fifteenth transistor T15 is electrically connected to the first node N1, the source of the fifteenth transistor T15 is electrically connected to the high voltage terminal VGH, and the drain of the fifteenth transistor T15 is electrically connected to the drive output terminal AZOUT.

[0277] The gate of the sixteenth transistor T16 is electrically connected to the second node N2, the source of the sixteenth transistor T16 is electrically connected to the drive output terminal AZOUT, and the drain of the sixteenth transistor T16 is electrically connected to the low voltage terminal VGL.

[0278] exist Figure 11 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but this is not a limitation.

[0279] like Figure 12 As shown, the present invention Figure 11When at least one embodiment of the driving circuit shown is in operation, the display cycle may include a first stage S1, an input stage S2, a first output stage S3, a second output stage S4, a third output stage S5, and a second stage S6 arranged sequentially.

[0280] In the first stage S1, CK3 provides a low voltage signal, AZSTV provides a high voltage signal, T8 is turned on, NC1 is at a high voltage, N2 is at a high voltage, and T16 is turned off; N1 is maintained at a high voltage, and AZOUT outputs a high voltage signal.

[0281] In the first stage S1, CK3 provides a low voltage signal, T10 is turned on, NC2 is at a low voltage, T7 is turned on, N4 is at a high voltage; T6 is turned off.

[0282] During the input phase S2, CK1 provides a low voltage signal, ROUT provides a low voltage signal, T1 is turned on so that the potential of N3 is low voltage, T2 is turned on, and AZOUT and CKO1 are connected; CKO1 outputs a high voltage signal, and AZOUT outputs a high voltage signal.

[0283] In the first output stage S3, CK2 provides a low voltage signal, AZSTV provides a low voltage signal, T3 is turned on, the gate potential of T4 is low voltage, T4 is turned on, the potential of N1 is high voltage, and T15 is turned off; T2 is turned on, the potential of the first output clock signal provided by CKO1 jumps from high voltage to low voltage, and AZOUT outputs a low voltage signal.

[0284] In the second output stage S4, when CK3 provides a low voltage signal, CK1 and CK2 both provide high voltage signals, AZSTV provides a low voltage signal, T8 is turned on, T9 is turned on, NC1 is at a low voltage, N2 is at a low voltage, T16 is turned on, and AZOUT outputs a low voltage signal; when T5 is turned on, N3 is at a high voltage, and T2 is turned off; when T10 is turned on, NC2 is at a low voltage.

[0285] In the second output stage S4, when CK3 provides a low voltage signal, CK1 and CK2 both provide high voltage signals, AZSTV provides a low voltage signal, N2 has a low voltage potential, NC1 has a low voltage potential, NC2 has a low voltage potential, T6 and T7 are turned on, CK1 provides a high voltage signal, and N4 has a high voltage potential.

[0286] In the second output stage S4, when CK1 provides a low voltage signal, CK2 and CK3 both provide high voltage signals, T8 is turned off, and the potentials of NC1 and N2 remain at low voltage; T11 is turned on, CK3 provides a high voltage signal, the potentials of NC2 and NC3 are high voltage signals, T12 is turned off; T16 is turned on, and AZOUT outputs a low voltage signal.

[0287] In the second output stage S4, when the potential of the first clock signal provided by CK1 changes from high voltage to low voltage, T6 is turned on, pulling down the potential of N2 through C2;

[0288] In the second output stage S4, when CK2 provides a low voltage signal, CK1 and CK3 both provide high voltage signals, AZSTV provides a low voltage signal, T3 is turned on, the gate potential of T4 is low voltage, T4 is turned on, the potential of N1 is high voltage, and T15 is turned off; the potentials of NC1 and N2 are maintained at low voltage, T16 is turned on, and AZOUT outputs a low voltage signal.

[0289] In the third output stage S5, CK3 provides a low voltage signal, AZSTV provides a high voltage signal, T8 is turned on, the potentials of NC1 and N2 are both high voltage, T16 is turned off, CK1 provides a high voltage signal, T13 is turned off, CK2 provides a high voltage signal, T3 is turned off, the potential of N1 remains high voltage, T15 is turned off; ROUT provides a high voltage signal, T1 is turned off, T2 is turned off, AZOUT continues to output a low voltage signal;

[0290] In the third output stage S5, CK3 provides a low voltage signal, AZSTV provides a high voltage signal, T8 is turned on, T9 is turned on, the potentials of NC1 and N2 are both high voltage, T16 is turned off, T10 is turned on, the potential of NC2 is low voltage, T14 is turned on, the potential of NC3 is low voltage; CK1 provides a high voltage signal, T13 is turned off.

[0291] In the second stage S6, CK1 provides a low voltage signal, T12 is turned on, T13 is turned on, the potential of NC2 is maintained at low voltage, the potential of N1 is low voltage, T15 is turned on, and AZOUT outputs a high voltage signal.

[0292] In specific implementation, during the input stage S2, the turn-on time of T1 needs to be less than 1H (one line scan time). The rising edge of the first output control signal provided by ROUT needs to be before the falling edge of the first output clock signal provided by CKO1, so as to ensure that in the first output stage S3, when T1 is turned off, N3 can complete the pull-down bootstrap, so that AZOUT and CKO1 are connected, and AZOUT can output a low voltage signal smoothly.

[0293] In at least one embodiment of the present invention, since the phase difference between the reset control signals generated by the two-stage reset control signal generation circuit is 1H, and the phase difference between the signal output by AZOUT and the signal provided by AZSTV is also 1H, and the falling edge of the signal provided by AZSTV coincides with the falling edge of the first output control signal provided by ROUT, and the low-level pulse width of the first output control signal provided by ROUT is less than 1H, and its rising edge phase also meets the requirements, the reset control signal is multiplexed as the first output control signal. The first output control signal can be provided by the reset control signal generation circuit, so as to save the devices and wiring required to independently set the circuit structure to generate the first output control signal, which is beneficial to save costs and achieve a narrow bezel.

[0294] This invention Figure 11 In at least one embodiment of the driving circuit shown, when in operation, the first output control signal provided by the first output control terminal ROUT is coordinated with a corresponding clock signal. By separating the output clock signal from the control clock signal, the fall time of the driving signal provided by the driving output terminal AZOUT is minimized.

[0295] This invention Figure 11 In at least one embodiment of the driving circuit shown, during operation, in the first output stage S3, T2 is turned on under the control of the potential of the third node N3 to control the connection between AZOUT and CKO1. The potential of the first output clock signal provided by CKO1 jumps from high voltage to low voltage, and AZOUT outputs a low voltage signal. Instead of controlling the potential drop of the driving signal output by AZOUT through T16 to reduce the fall time of the driving signal output by AZOUT.

[0296] This invention Figure 11 In at least one embodiment of the driving circuit shown, the pulse width of the driving signal output by AZOUT can be adjusted by controlling the position of the rising edge and the falling edge of the starting voltage signal provided by AZSTV, the position of the falling edge of the first output clock signal provided by CK1O, and the position of the falling edge of the first clock signal.

[0297] In this invention Figure 11 In at least one embodiment of the driving circuit shown, each transistor can be replaced with an n-type transistor. Figure 11 In at least one embodiment of the driving circuit shown, the waveforms of each signal can be compared with... Figure 12 By inverting the waveform of the signal in the input, the rise time of the drive signal output by AZOUT can be reduced.

[0298] exist Figure 12 and Figure 14In the diagram, the signal labeled CKO2 is the second output clock signal, and the signal labeled CKO3 is the third output clock signal.

[0299] This invention Figure 13 At least one embodiment of the driving circuit shown is related to the present invention. Figure 11 The difference in at least one embodiment of the driving circuit shown is that it does not include a fifth transistor;

[0300] The gate of T1 is electrically connected to the first clock signal terminal CK1, the source of T1 is electrically connected to the first output control terminal ROUT, and the drain of T1 is electrically connected to the third node N3.

[0301] In this invention Figure 13 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but this is not a limitation.

[0302] like Figure 14 As shown, the present invention Figure 13 When at least one embodiment of the driving circuit shown is in operation, the display cycle may include a first stage S1, an input stage S2, a first output stage S3, a second output stage S4, a third output stage S5, and a second stage S6 arranged sequentially.

[0303] In the first stage S1, CK3 provides a low voltage signal, AZSTV provides a high voltage signal, T8 is turned on, NC1 is at a high voltage, N2 is at a high voltage, and T16 is turned off; N1 is maintained at a high voltage, AZOUT outputs a high voltage signal; CK1 provides a high voltage signal, and T1 is turned off.

[0304] In the first stage S1, CK3 provides a low voltage signal, T10 is turned on, NC2 is at a low voltage, T7 is turned on, N4 is at a high voltage; T6 is turned off.

[0305] During the input phase S2, CK1 provides a low voltage signal, ROUT provides a low voltage signal, T1 is turned on so that the potential of N3 is low voltage, T2 is turned on, and AZOUT and CKO1 are connected; CKO1 outputs a high voltage signal, and AZOUT outputs a high voltage signal.

[0306] In the first output stage S3, CK2 provides a low voltage signal, AZSTV provides a low voltage signal, T3 is turned on, the gate potential of T4 is low voltage, T4 is turned on, the potential of N1 is high voltage, and T15 is turned off; T2 is turned on, the potential of the first output clock signal provided by CKO1 jumps from high voltage to low voltage, and AZOUT outputs a low voltage signal.

[0307] In the second output stage S4, when CK3 provides a low voltage signal, CK1 and CK2 both provide high voltage signals, AZSTV provides a low voltage signal, T8 is turned on, T9 is turned on, NC1 is at a low voltage, N2 is at a low voltage, and T16 is turned on; N3 is at a low voltage, T2 is turned on, AZOUT and CKO1 are connected, CKO1 provides a low voltage signal, and AZOUT outputs a low voltage signal; T10 is turned on, and NC2 is at a low voltage.

[0308] In the second output stage S4, when CK3 provides a low voltage signal, CK1 and CK2 both provide high voltage signals, AZSTV provides a low voltage signal, N2 has a low voltage potential, NC1 has a low voltage potential, NC2 has a low voltage potential, T6 and T7 are turned on, CK1 provides a high voltage signal, and N4 has a high voltage potential.

[0309] In the second output stage S4, when CK1 provides a low voltage signal, CK2 and CK3 both provide high voltage signals, T8 is turned off, and the potentials of NC1 and N2 remain low voltage; when ROUT provides a high voltage signal, T1 is turned on; when T11 is turned on, CK3 provides a high voltage signal, the potentials of NC2 and NC3 are high voltage signals, and T12 is turned off; when T16 is turned on, AZOUT outputs a low voltage signal.

[0310] In the second output stage S4, when the potential of the first clock signal provided by CK1 changes from high voltage to low voltage, T6 is turned on, pulling down the potential of N2 through C2;

[0311] In the second output stage S4, when CK2 provides a low voltage signal, CK1 and CK3 both provide high voltage signals, AZSTV provides a low voltage signal, T3 is turned on, the gate potential of T4 is low voltage, T4 is turned on, the potential of N1 is high voltage, and T15 is turned off; the potentials of NC1 and N2 are maintained at low voltage, T16 is turned on, and AZOUT outputs a low voltage signal.

[0312] In the third output stage S5, CK3 provides a low voltage signal, AZSTV provides a high voltage signal, T8 is turned on, the potentials of NC1 and N2 are both high voltage, T16 is turned off, CK1 provides a high voltage signal, T13 is turned off, CK2 provides a high voltage signal, T3 is turned off, the potential of N1 remains high voltage, T15 is turned off; ROUT provides a high voltage signal, T1 is turned off, T2 is turned off, AZOUT continues to output a low voltage signal;

[0313] In the third output stage S5, CK3 provides a low voltage signal, AZSTV provides a high voltage signal, T8 is turned on, T9 is turned on, the potentials of NC1 and N2 are both high voltage, T16 is turned off, T10 is turned on, the potential of NC2 is low voltage, T14 is turned on, the potential of NC3 is low voltage; CK1 provides a high voltage signal, T13 is turned off.

[0314] In the second stage S6, CK1 provides a low voltage signal, T12 is turned on, T13 is turned on, the potential of NC2 is maintained at low voltage, the potential of N1 is low voltage, T15 is turned on, and AZOUT outputs a high voltage signal.

[0315] This invention Figure 13 In at least one embodiment of the driving circuit shown, when in operation, the first output control signal provided by the first output control terminal ROUT is coordinated with a corresponding clock signal. By separating the output clock signal from the control clock signal, the fall time of the driving signal provided by the driving output terminal AZOUT is minimized.

[0316] This invention Figure 13 In at least one embodiment of the driving circuit shown, during operation, in the first output stage S3, T2 is turned on under the control of the potential of the third node N3 to control the connection between AZOUT and CKO1. The potential of the first output clock signal provided by CKO1 jumps from high voltage to low voltage, and AZOUT outputs a low voltage signal. Instead of controlling the potential drop of the driving signal output by AZOUT through T16 to reduce the fall time of the driving signal output by AZOUT.

[0317] This invention Figure 13 In at least one embodiment of the driving circuit shown, the pulse width of the driving signal output by AZOUT can be adjusted by controlling the position of the rising edge and the falling edge of the starting voltage signal provided by AZSTV, the position of the falling edge of the first output clock signal provided by CK1O, and the position of the falling edge of the first clock signal.

[0318] In this invention Figure 13 In at least one embodiment of the driving circuit shown, each transistor can be replaced with an n-type transistor. Figure 13 In at least one embodiment of the driving circuit shown, the waveforms of each signal can be compared with... Figure 14 By inverting the waveform of the signal in the input, the rise time of the drive signal output by AZOUT can be reduced.

[0319] The display device provided in this embodiment of the invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0320] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that, It includes a first node control circuit, a second node control circuit, a third node control circuit, a first output circuit, a first energy storage circuit, and a second output circuit; The first node control circuit is electrically connected to the first node and is used to control the potential of the first node; The second node control circuit is electrically connected to the second node and is used to control the potential of the second node; The third node control circuit is electrically connected to the first output control terminal and the third node respectively, and is used to control the potential of the third node according to the first output control signal provided by the first output control terminal; The first output circuit is electrically connected to the first node, the second node and the drive output terminal respectively, and is used to control the drive output terminal to output a drive signal under the control of the potential of the first node and the potential of the second node; The first energy storage circuit is electrically connected to the third node and the drive output terminal respectively, and is used to store electrical energy; The second output circuit is electrically connected to the third node, the first output clock signal terminal, and the drive output terminal, respectively, and is used to control the connection or disconnection between the first output clock signal terminal and the drive output terminal under the control of the potential of the third node.

2. The driving circuit as described in claim 1, characterized in that, The first output control terminal is electrically connected to the reset control signal output terminal of the reset control signal generation circuit; The reset control signal generation circuit is electrically connected to the control terminal of the reset circuit in the pixel circuit through the reset control signal output terminal. The reset control signal generation circuit is used to provide a reset control signal to the control terminal of the reset circuit. The pixel circuit also includes a driving transistor; The reset circuit is electrically connected to the gate of the driving transistor and is used to reset the potential of the gate of the driving transistor under the control of the reset control signal.

3. The driving circuit as described in claim 2, characterized in that, The third node control circuit is also electrically connected to the first voltage terminal, and is used to control the connection or disconnection between the first voltage terminal and the third node under the control of the first output control signal.

4. The driving circuit as described in claim 2, characterized in that, The third node control circuit is also electrically connected to the first clock signal terminal, and is used to control the connection or disconnection between the third node and the first output control terminal under the control of the first clock signal provided by the first clock signal terminal.

5. The driving circuit according to any one of claims 1 to 4, characterized in that, It also includes a first control circuit and a second control circuit; The first control circuit is electrically connected to the second clock signal terminal, the starting voltage terminal, the fourth node, the second voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the starting voltage terminal and the fourth node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection or disconnection between the first node and the second voltage terminal under the control of the potential of the fourth node. The second control circuit is electrically connected to the first control node, the third node, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the second voltage terminal under the control of the potential of the first control node.

6. The driving circuit according to any one of claims 1 to 4, characterized in that, It also includes a fourth node control circuit, and the second node control circuit includes a second energy storage circuit and a third control circuit; The fourth node control circuit is electrically connected to the second control node, the second voltage terminal, the fourth node, and the first clock signal terminal, respectively. It is used to control the connection or disconnection between the fourth node and the second voltage terminal under the control of the potential of the second control node, and to control the connection or disconnection between the fourth node and the first clock signal terminal under the control of the potential of the second node. The second energy storage circuit is electrically connected to the fourth node and the second node respectively, and is used to control the potential of the second node according to the potential of the fourth node; The third control circuit is electrically connected to the third clock signal terminal, the starting voltage terminal and the first control node respectively, and is used to control the connection or disconnection between the first control node and the starting voltage terminal under the control of the third clock signal provided by the third clock signal terminal. The first control node is connected to the second node; or, the driving circuit further includes a first on / off control circuit; the first on / off control circuit is electrically connected to the third voltage terminal, the second node and the first control node respectively, and is used to control the connection or disconnection between the second node and the first control node under the control of the third voltage signal provided by the third voltage terminal.

7. The driving circuit according to any one of claims 1 to 4, characterized in that, It also includes the control node control circuit; The control node control circuit is electrically connected to the third clock signal terminal, the first voltage terminal, the second control node, and the first control node, respectively. It is used to control the connection or disconnection between the second control node and the first voltage terminal under the control of the third clock signal provided by the third clock signal terminal, and to control the connection or disconnection between the second control node and the third clock signal terminal under the control of the potential of the first control node.

8. The driving circuit according to any one of claims 1 to 4, characterized in that, The first node control circuit is electrically connected to the third control node, the first clock signal terminal, the fourth control node, and the first node, respectively. It is used to control the connection or disconnection between the fourth control node and the first clock signal terminal under the control of the potential of the third control node, and to control the potential of the fourth control node according to the potential of the third control node. Under the control of the first clock signal provided by the first clock signal terminal, it controls the connection or disconnection between the fourth control node and the first node, and is used to maintain the potential of the first node. The second control node is connected to the third control node; or... The driving circuit further includes a second on / off control circuit; the second on / off control circuit is electrically connected to the fourth voltage terminal, the second control node and the third control node respectively, and is used to control the connection or disconnection between the second control node and the third control node under the control of the fourth voltage signal provided by the fourth voltage terminal.

9. The driving circuit as described in claim 3, characterized in that, The third node control circuit includes a first transistor; The gate of the first transistor is electrically connected to the first output control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the third node.

10. The driving circuit as described in claim 4, characterized in that, The third node control circuit includes a first transistor; The gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first output control terminal, and the second electrode of the first transistor is electrically connected to the third node.

11. The driving circuit as described in claim 5, characterized in that, The first energy storage circuit includes a first capacitor, and the second output circuit includes a second transistor; The gate of the second transistor is electrically connected to the third node, the first terminal of the second transistor is electrically connected to the first output clock signal terminal, and the second terminal of the second transistor is electrically connected to the drive output terminal. The first terminal of the first capacitor is electrically connected to the third node, and the second terminal of the first capacitor is electrically connected to the drive output terminal. The first control circuit includes a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the second clock signal terminal, the first terminal of the third transistor is electrically connected to the starting voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node. The gate of the fourth transistor is electrically connected to the fourth node, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node. The second control circuit includes a fifth transistor; The gate of the fifth transistor is electrically connected to the first control node, the first terminal of the fifth transistor is electrically connected to the second voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

12. The driving circuit as described in claim 6, characterized in that, The fourth node control circuit includes a sixth transistor and a seventh transistor; the second energy storage circuit includes a second capacitor. The gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the first clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the fourth node. The gate of the seventh transistor is electrically connected to the second control node, the first terminal of the seventh transistor is electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node; The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the second node; The third control circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the third clock signal terminal, the first terminal of the eighth transistor is electrically connected to the starting voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first control node. The first on / off control circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the third voltage terminal, the first terminal of the ninth transistor is electrically connected to the first control node, and the second terminal of the ninth transistor is electrically connected to the second node.

13. The driving circuit as described in claim 7, characterized in that, The control node control circuit includes a tenth transistor and an eleventh transistor; The gate of the tenth transistor is electrically connected to the third clock signal terminal, the first terminal of the tenth transistor is electrically connected to the first voltage terminal, and the second terminal of the tenth transistor is electrically connected to the second control node. The gate of the eleventh transistor is electrically connected to the first control node, the first terminal of the eleventh transistor is electrically connected to the third clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second control node.

14. The driving circuit as described in claim 8, characterized in that, The first node control circuit includes a twelfth transistor, a thirteenth transistor, a third capacitor, and a fourth capacitor; The gate of the twelfth transistor is electrically connected to the third control node, the first terminal of the twelfth transistor is electrically connected to the first clock signal terminal, and the second terminal of the twelfth transistor is electrically connected to the fourth control node. The gate of the thirteenth transistor is electrically connected to the first clock signal terminal, the first terminal of the thirteenth transistor is electrically connected to the fourth control node, and the second terminal of the thirteenth transistor is electrically connected to the first node. The first terminal of the third capacitor is electrically connected to the third control node, and the second terminal of the third capacitor is electrically connected to the fourth control node; The first terminal of the fourth capacitor is electrically connected to the first node, and the second terminal of the fourth capacitor is electrically connected to the second voltage terminal. When the driving circuit further includes a second on / off control circuit, the second on / off control circuit includes a fourteenth transistor; The gate of the fourteenth transistor is electrically connected to the fourth voltage terminal, the first terminal of the fourteenth transistor is electrically connected to the second control node, and the second terminal of the fourteenth transistor is electrically connected to the third control node. The first output circuit includes a fifteenth transistor and a sixteenth transistor; The gate of the fifteenth transistor is electrically connected to the first node, the first terminal of the fifteenth transistor is electrically connected to the second voltage terminal, and the second terminal of the fifteenth transistor is electrically connected to the drive output terminal. The gate of the sixteenth transistor is electrically connected to the second node, the first terminal of the sixteenth transistor is electrically connected to the drive output terminal, and the second terminal of the sixteenth transistor is electrically connected to the first voltage terminal.

15. A driving method applied to a driving circuit as described in any one of claims 1 to 14, characterized in that, The driving method includes: The first node control circuit controls the potential of the first node; The second node control circuit controls the potential of the second node; The third node control circuit controls the potential of the third node according to the first output control signal; The first output circuit controls the output of a drive signal at the drive output terminal under the control of the potential of the first node and the potential of the second node. The second output circuit, under the control of the potential of the third node, controls the connection or disconnection between the first output clock signal terminal and the drive output terminal.

16. A display device, characterized in that, Includes the drive circuit as described in any one of claims 1 to 14.

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