A double-layer graphene logic inverter

Abstract

The present invention belongs to the technical field of application of nanomaterial heterostructures, and specifically relates to a double-layer graphene logic inverter. In order to improve the switching ratio of graphene transistors, the present invention uses the associated insulating state generated by the interface coupling effect between the two-dimensional antiferromagnetic insulator CrOCl in the double-layer graphene system to respectively realize the P-type / N-type field effect curves for two different field effect devices by changing the gate voltage range, and connects them according to the wiring method of CMOS logic inverters. When Vdd is 0.15V, the input voltage is 3V to 8V, and a double-layer graphene CMOS logic inverter is realized in which Vout flips to 0V when Vin is a certain threshold voltage. This provides a new path for the realization of graphene logic devices.

Description

Technical Field

[0001] The invention belongs to the technical field of nano material heterostructure application, and in particular relates to a double-layer graphene logic inverter. Background Art

[0002] In 1965, in the field of semiconductor integrated circuits, Moore, the founder of Intel, summarized the data of the increase in integration over the years and derived Moore's Law, that is, the average number of transistors integrated on a chip will double every eighteen months. However, as the proportion predicted by Moore's Law decreases, Si field effect transistors also face a series of challenges in order to increase the integration of integrated circuits, increase the operating speed of devices and reduce their power consumption. For example, problems such as short channel effect, hot carrier injection effect and gate oxide leakage. It has become inevitable to explore new materials, new devices and new processes to replace or partially replace existing Si field effect transistors.

[0003] In this context, two scientists from the University of Manchester in the UK were the first in the world to produce single-layer graphene. Through extensive research on graphene, scientists have found that graphene has many excellent properties, such as high mobility - the carrier mobility at room temperature can reach 104cm 2 / V / S; high strength—Young's modulus is 1TPa; high light transmittance—light absorption rate is less than 2.3%; high thermal conductivity—thermal conductivity exceeds 3000W / (m·K), etc.

[0004] Since the band gap of graphene is zero, the on-off ratio of graphene transistors is very low, usually less than 5 orders of magnitude. Therefore, opening the band gap of graphene and improving the on-off ratio of graphene transistors have become very important conditions for preparing graphene transistor logic devices. Based on the above background, we have realized the correlated insulating state in a double-layer graphene system with a two-dimensional antiferromagnetic insulator CrOCl as the substrate, which has opened the band gap of double-layer graphene and increased the on-off ratio to 7 orders of magnitude. This provides a new path for the realization of graphene logic devices. Summary of the invention

[0005] The purpose of the present invention is to provide a double-layer graphene CMOS logic inverter. In a double-layer graphene system of a two-dimensional antiferromagnetic insulator CrOCl, by means of the associated insulating state generated by the interface coupling effect between them, two different field effect devices are respectively realized by changing the gate voltage range to realize P-type / N-type field effect curves, and they are connected according to the wiring method of a CMOS logic inverter. When Vdd is 0.15V, the input voltage is 3V to 8V, and it is measured that Vout flips to 0V when Vin is a certain threshold voltage.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The present invention realizes a double-layer graphene logic inverter based on the correlated insulating state of a double-layer graphene system of a two-dimensional antiferromagnetic insulator CrOCl.

[0008] A double-layer graphene logic inverter includes two field effect devices of a double-layer graphene system based on an antiferromagnetic insulator CrOCl. The field effect device of the double-layer graphene system based on the antiferromagnetic insulator CrOCl is an upper gate, a field effect device, a lower gate and a substrate arranged in sequence from top to bottom. The upper layer of the field effect device uses hexagonal boron nitride as a dielectric and packaging material, the middle layer uses double-layer graphene, and the bottom layer is a two-dimensional antiferromagnetic insulator material CrOCl.

[0009] Furthermore, the two field effect devices based on the double-layer graphene system of the antiferromagnetic insulator CrOCl respectively realize a P-type field effect device and an N-type field effect device by fixing the back gate / top gate voltage and changing the top gate / back gate voltage.

[0010] Furthermore, the preparation method of the field effect device is:

[0011] A two-dimensional antiferromagnetic insulator CrOCl, hexagonal boron nitride and double-layer graphene are artificially stacked to obtain a heterojunction, and then the heterojunction is micro-nano processed to obtain the field effect device.

[0012] Furthermore, the micro-nano processing is electron beam exposure, etching, and evaporation.

[0013] Furthermore, the substrate is a Si substrate, a quartz substrate, a mica sheet or a flexible substrate.

[0014] Furthermore, the upper gate and the lower gate are Au.

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] In the double-layer graphene system with two-dimensional antiferromagnetic insulator CrOCl as substrate, the present invention realizes a double-layer graphene logic inverter with a gain of 1.1 and a power consumption of nW level by utilizing the correlated insulating state generated by the interface coupling effect between CrOCl and the double-layer graphene, providing a new path for the realization of graphene logic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The following are photos of two field effect devices based on the double-layer graphene system of antiferromagnetic insulator CrOCl on the sample holder;

[0018] Figure 2The field effect curves of two field effect devices based on the double-layer graphene system of antiferromagnetic insulator CrOCl;

[0019] Figure 3 The wiring and wiring diagram of two field effect devices based on the double-layer graphene system of antiferromagnetic insulator CrOCl as CMOS logic inverters;

[0020] Figure 4 The performance of graphene CMOS logic inverter;

[0021] Figure 5 Schematic diagram of a field effect device based on a double-layer graphene system of antiferromagnetic insulator CrOCl. DETAILED DESCRIPTION

[0022] The present invention will be further described in the following examples, but the present invention is not limited thereto.

[0023] Example 1

[0024] A double-layer graphene logic inverter includes two field effect devices based on a double-layer graphene system of an antiferromagnetic insulator CrOCl. Figure 5 As shown, the field effect device of the double-layer graphene system based on the antiferromagnetic insulator CrOCl is an upper gate, a field effect device, a lower gate and a substrate arranged in sequence from top to bottom. The upper layer of the field effect device uses hexagonal boron nitride as a dielectric and packaging material, the middle layer uses double-layer graphene, the bottom layer is a two-dimensional antiferromagnetic insulator material CrOCl, the substrate is a Si substrate, and the upper gate and the lower gate are Au.

[0025] Two field effect devices based on the double-layer graphene system of antiferromagnetic insulator CrOCl are realized as P-type field effect devices and N-type field effect devices by fixing the back gate / top gate voltage and changing the top gate / back gate voltage respectively.

[0026] Example 2

[0027] A method for preparing a double-layer graphene logic inverter comprises the following steps:

[0028] (1) A two-dimensional antiferromagnetic insulator CrOCl, hexagonal boron nitride and double-layer graphene are artificially stacked to obtain a heterojunction, and then the heterojunction is subjected to micro-nano processing such as electron beam exposure, etching, and evaporation, and finally two field effect devices based on the double-layer graphene system of the antiferromagnetic insulator CrOCl are obtained according to the design of Example 1.

[0029] (2) Use a wire-bonder to connect the two devices to the same sample holder. Figure 1 shown.

[0030] (3) Load the device into a low-temperature vacuum chamber and cool it to 1.5K.

[0031] (4) Manually push the top gate and bottom gate of the two devices (S22 and S26 are selected in this embodiment) to a larger range (no leakage), start scanning the dual-gate mapping of the two devices, and obtain the gate range of the associated insulating state of the two devices.

[0032] (5) Select device S26 as PMOS, that is, fix the back gate voltage to -2.9V and the top gate voltage to 0V to 10V, and obtain the P-type field effect curve ( Figure 2 a); select device S22 as NMOS, that is, fix the top gate voltage to 12.673V, the back gate voltage to 0V to 10V, and obtain the N-type field effect curve ( Figure 2 (b)

[0033] (6) According to the wiring diagram of CMOS logic inverter ( Figure 3 a) Connect devices S26 and S22 together ( Figure 3 b). (The metal used in the metal electrode is one or more of Cr, Ti, Au, Pd, Sc, and Ni)

[0034] (7) Apply a voltage of Vdd = 0.15V to the connected CMOS logic inverter device, set the input voltage to 3V to 8V, and Vout flips to 0V at a threshold voltage of about 5.2V ( Figure 4 ), resulting in a gain of approximately 1.1 and a maximum Idd of approximately 120nA.

[0035] Example 3

[0036] The difference from Example 2 is that when Vdd=0.2V is fixed, the temperature is changed from 1.5K to 80K, and a series of curves of Vout varying with temperature are obtained. As the temperature increases, the gain of the inverter gradually decreases.

[0037] Example 4

[0038] The difference from Example 2 is that the logic circuit described in step (6) is a NAND logic circuit, and after inputting waveform A and waveform B signals, a typical NAND logic device function can be obtained; and a good NAND logic device function can still be achieved at a temperature of 80K.

[0039] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in the field. Although the illustrative specific embodiments of the present invention are described above to facilitate the understanding of the present invention by the technical personnel in the field, it should be clear that the present invention is not limited to the scope of the specific embodiments. For ordinary technicians in the field of this technology, as long as various changes are within the spirit and scope of the present invention defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A double-layer graphene logic inverter, characterized in that: The invention relates to a field effect device comprising two double-layer graphene systems based on an antiferromagnetic insulator CrOCl, wherein the field effect device based on the double-layer graphene system of the antiferromagnetic insulator CrOCl comprises an upper gate, a field effect device, a lower gate and a substrate arranged in sequence from top to bottom, wherein the upper layer of the field effect device uses hexagonal boron nitride as a dielectric and packaging material, the middle layer uses double-layer graphene, and the bottom layer is a two-dimensional antiferromagnetic insulator material CrOCl; With the help of the correlated insulating state generated by the interface coupling effect between CrOCl and double-layer graphene, the P-type / N-type field effect curves are realized respectively for two different field effect devices by changing the gate voltage range, that is, the P-type field effect device and the N-type field effect device are realized by fixing the back gate / top gate voltage and changing the top gate / back gate voltage, and they are connected according to the wiring method of CMOS logic inverters.

2. A double-layer graphene logic inverter according to claim 1, characterized in that: The preparation method of the field effect device is as follows: A two-dimensional antiferromagnetic insulator CrOCl, hexagonal boron nitride and double-layer graphene are artificially stacked to obtain a heterojunction, and then the heterojunction is micro-nano processed to obtain the field effect device.

3. A double-layer graphene logic inverter according to claim 2, characterized in that: The micro-nano processing includes electron beam exposure, etching and evaporation.

4. A double-layer graphene logic inverter according to claim 1, characterized in that: The substrate is a Si substrate, a quartz substrate, a mica sheet or a flexible substrate.

5. A double-layer graphene logic inverter according to claim 1, characterized in that: The upper gate and the lower gate are Au.

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