Chip testing methods and testing carriers

Abstract

This invention provides a chip testing method and a testing carrier thereof. The chip testing method includes the following steps: First, a testing carrier is provided, wherein the testing carrier includes a carrier body, a plurality of electrical detection heads, and a testing unit. A groove is formed on the carrier body, the plurality of electrical detection heads are coupled to the testing unit, the plurality of electrical detection heads are located in the groove, and the testing unit is disposed on the carrier body. Next, a chip to be tested is provided, wherein the chip to be tested includes a first surface, a second surface, and a plurality of electrical contacts, the first surface being opposite to the second surface, and the plurality of electrical contacts being distributed on the edge of the chip to be tested. Then, the chip to be tested is placed in the groove, the plurality of electrical detection heads directly abutting the plurality of electrical contacts, and the testing unit tests the chip through the plurality of electrical detection heads.

Description

Technical Field

[0001] This invention relates to a chip testing method, and more particularly to a chip testing method that does not require wire bonding. Background Technology

[0002] A known fault detection method for Quad Flat No Leads (QFN) chip packages involves grinding the chip until the back of the die is exposed, then wire bonding the chip to a printed circuit board (PCB). The chip is then programmed and tested via the PCB. However, this wire bonding process is extremely labor-intensive and time-consuming, and it is difficult to remove and reuse the tested chip. Summary of the Invention

[0003] This invention provides a chip testing method to address known technical problems, comprising the following steps: First, a testing carrier is provided, comprising a carrier body, a plurality of electrical detection heads, and a testing unit. A groove is formed on the carrier body, the plurality of electrical detection heads are coupled to the testing unit, the plurality of electrical detection heads are located within the groove, and the testing unit is disposed on the carrier body. Next, a chip to be tested is provided, comprising a first surface, a second surface, and a plurality of electrical contacts, the first surface being opposite to the second surface, and the plurality of electrical contacts being distributed along the edge of the chip to be tested. Then, the chip to be tested is placed in the groove, the plurality of electrical detection heads directly abutting against the plurality of electrical contacts, and the testing unit tests the chip through the plurality of electrical detection heads.

[0004] In one embodiment, the plurality of electrical detection heads and the plurality of electrical contacts are not connected by wire bonding.

[0005] In one embodiment, the first surface is opposite to the second surface, and each electrical contact is at least partially located on the second surface, with the first surface facing the groove when the chip under test is placed in the groove.

[0006] In one embodiment, the chip under test includes multiple chip sidewalls, and each electrical contact is at least partially located on one of the chip sidewalls. The multiple electrical detection heads extend toward the multiple chip sidewalls and directly abut against the multiple electrical contacts.

[0007] In one embodiment, the chip inspection method further includes the following steps: Before placing the chip under test into the recess, a portion of the structure on the second surface of the chip is removed to expose the back surface of the chip. Next, an optical inspection device is provided to perform optical inspection on the second surface of the chip while it is placed in the recess.

[0008] In one embodiment, the chip under test has a metal ground layer located on the second surface, and in the step of removing a portion of the structure on the second surface of the chip, the metal ground layer is completely or partially removed.

[0009] In one embodiment, the carrier body includes a body surface, and when the chip under test is placed within the groove, the height of the second surface of the chip under test is equal to or lower than the height of the body surface.

[0010] In another embodiment, the present invention provides a chip testing carrier suitable for testing a chip under test, comprising a carrier body, a plurality of electrical detection heads, and a testing unit. The carrier body has a recess. The electrical detection heads are disposed on the carrier body, with the plurality of electrical detection heads protruding from the recess. The testing unit is disposed on the carrier body, and the plurality of electrical detection heads are coupled to the testing unit. The chip under test includes a plurality of electrical contacts. When the chip under test is placed in the recess, the plurality of electrical detection heads directly abut against the plurality of electrical contacts, and the testing unit tests the chip through the plurality of electrical detection heads.

[0011] In one embodiment, the plurality of electrical detection heads include spring pin connectors or gold finger springs. When the chip under test is placed in the groove, the plurality of electrical detection heads directly abut the plurality of electrical contacts on the four sides of the chip under test.

[0012] The chip testing method of this invention eliminates the need for the cumbersome wire bonding step of known technologies because the electrical testing heads of the testing carrier directly contact the electrical contacts of the chip under test. Furthermore, the tested chip can be easily removed and reused. Additionally, the testing carrier and the chip under test can be fed together into an optical testing device for optical testing, thus simplifying the testing process and improving testing efficiency. Attached Figure Description

[0013] Figure 1A This is a detection carrier that illustrates an embodiment of the present invention.

[0014] Figure 1B This is the chip under test that demonstrates an embodiment of the present invention.

[0015] Figure 2 This illustrates a scenario where the chip under test (DUT) is placed within a testing carrier, according to an embodiment of the present invention.

[0016] Figure 3 This is a flowchart illustrating the chip detection method according to an embodiment of the present invention.

[0017] Figure 4 This describes the detailed steps of the chip detection method according to an embodiment of the present invention.

[0018] Figure 5 This is an optical detection device that demonstrates an embodiment of the present invention.

[0019] Figure label:

[0020] D: Detection vehicle

[0021] 1: Vehicle Body

[0022] 11: Groove

[0023] 12: Push-pull gap

[0024] 13: Body surface

[0025] 21: Electrical Detection Head

[0026] 22: Detection Unit

[0027] 23: Universal Serial Bus connector

[0028] C: Chip under test

[0029] 31: First Surface

[0030] 32: Second surface

[0031] 33: Chip sidewall

[0032] 35: Electrical contacts

[0033] 39: Circuit Structure

[0034] S11, S12, S13: Steps

[0035] S21, S22: Steps

[0036] 4: Optical inspection device Detailed Implementation

[0037] Figure 1A This is a detection carrier that illustrates an embodiment of the present invention. Figure 1B This is the chip under test that demonstrates an embodiment of the present invention. Figure 2 This illustration shows a scenario where the chip under test (DUT) is placed within a testing carrier, according to an embodiment of the present invention. (See accompanying reference.) Figure 1A , Figure 1B , Figure 2The detection carrier D of this invention is suitable for detecting a chip C to be tested. The detection carrier D includes a carrier body 1, a plurality of electrical detection heads 21, and a detection unit 22. The carrier body 1 has a recess 11. The electrical detection heads 21 are disposed on the carrier body 1, and the plurality of electrical detection heads 21 protrude from the recess 11. The detection unit 22 is disposed on the carrier body 1, and the plurality of electrical detection heads 21 are coupled to the detection unit 22. The chip C to be tested includes a plurality of electrical contacts 35. When the chip C to be tested is placed in the recess 11, the plurality of electrical detection heads 21 directly abut against the plurality of electrical contacts 35, and the detection unit 22 detects the chip C through the plurality of electrical detection heads 21.

[0038] Matching reference Figure 1A , Figure 1B , Figure 2 In one embodiment, the plurality of electrical detection heads 21 can be pogo-pin connectors. When the chip under test (DUT) C is placed in the groove 11, the plurality of electrical detection heads 21 directly abut against the plurality of electrical contacts 35 on the four sides of the DUT C. In this embodiment, since the pogo-pin connector provides elastic force, the plurality of electrical detection heads 21 also provide a clamping and positioning effect on the DUT C. In one embodiment, the plurality of electrical detection heads 21 protrude from the inner wall of the groove 11. In another embodiment, the plurality of electrical detection heads 21 can also be gold finger springs or other forms of detection heads; the above description does not limit the invention.

[0039] In embodiments of the present invention, the plurality of electrical detection heads are electrically connected to the plurality of electrical contacts by means of elastic contact. Therefore, unlike known technologies, the plurality of electrical detection heads and the plurality of electrical contacts in embodiments of the present invention are not connected by wire bonding.

[0040] Matching reference Figure 1A , Figure 1B , Figure 2 The chip under test C includes a first surface 31 and a second surface 32. The first surface 31 is opposite to the second surface 32. Each electrical contact 35 is located at least partially on the second surface 32. When the chip under test C is placed in the groove 11, the first surface 31 faces the groove 11.

[0041] Matching reference Figure 1A , Figure 1B , Figure 2 In one embodiment, the chip under test C includes a plurality of chip sidewalls 33, and each electrical contact 35 is at least partially located on one of the chip sidewalls 33. The plurality of electrical detection heads 21 extend toward the plurality of chip sidewalls 33 and directly abut against the plurality of electrical contacts 35.

[0042] Matching reference Figure 1A , Figure 1B , Figure 2 In one embodiment, the carrier body 1 can be a circuit board. The depth of the groove 11 can be equal to or greater than the thickness of the chip C under test. When the chip C under test is placed in the groove 11, the chip C under test contacts the bottom of the groove 11.

[0043] Matching reference Figure 1A , Figure 1B , Figure 2 In one embodiment, the detection unit 22 can be an in-circuit emulator (ICE). The detection unit 22 can perform detection on the chip under test (DUT) C, for example, by performing programming detection on the DUT C. In one embodiment, the detection carrier D may further include a Universal Serial Bus (USB) connector 23, which is coupled to the detection unit 22.

[0044] Matching reference Figure 1A , Figure 1B , Figure 2 In one embodiment, the carrier body 1 has a push-pull notch 12 formed on the edge of the groove 11. The user can insert a hand tool into the push-pull notch 12 to push the chip C under test in the groove 11 to facilitate the removal of the chip C under test.

[0045] Figure 3 This is a flowchart illustrating a chip detection method according to an embodiment of the present invention. (Refer to...) Figure 3 In one embodiment, the present invention provides a chip testing method, comprising the following steps. First, a testing carrier is provided, wherein the testing carrier includes a carrier body, a plurality of electrical detection heads, and a testing unit. A groove is formed on the carrier body, the plurality of electrical detection heads are coupled to the testing unit, the plurality of electrical detection heads are located in the groove, and the testing unit is disposed on the carrier body (S11). Next, a chip to be tested is provided, wherein the chip to be tested includes a first surface, a second surface, and a plurality of electrical contacts, the first surface being opposite to the second surface, and the plurality of electrical contacts being distributed at the edge of the chip to be tested (S12). Then, the chip to be tested is placed in the groove, the plurality of electrical detection heads directly abutting the plurality of electrical contacts, and the testing unit tests the chip through the plurality of electrical detection heads (S13).

[0046] Figure 4 This describes the detailed steps of the chip detection method according to an embodiment of the present invention. (Refer to...) Figure 4In one embodiment, the chip inspection method further includes the following steps: Before placing the chip under test into the recess, a portion of the structure on the second surface of the chip is removed to expose the back surface of the chip under test (S21). Next, an optical inspection device is provided to perform optical inspection on the second surface of the chip while it is placed in the recess (S22).

[0047] Figure 5 This is an optical detection device illustrating an embodiment of the present invention. See accompanying reference. Figure 1B , Figure 5 In one embodiment, the chip under test C has a metal ground layer (e.g., an E-pad, not shown) located on the second surface 32. During the step of removing a portion of the structure on the second surface of the chip, the metal ground layer is either completely or partially removed (e.g., ...). Figure 1B (As shown). This allows the circuit structure 39 inside the chip C under test to be inspected by an optical inspection device. This optical inspection device 4 can be an optical microscope. The optical inspection device 4 can locate defect hotspots inside the chip C under test.

[0048] Matching reference Figure 2 , Figure 5 In one embodiment, the carrier body 1 includes a body surface 13 (upper surface). When the chip under test C is placed within the groove 11, the height of the second surface 32 of the chip under test C is equal to or lower than the height of the body surface 13. Referring to this... Figure 5 When the optical detection device 4 performs optical detection on the chip C, the optical detection device 4 will not collide with the surface 13 of the carrier body 1 or the chip C (upper surface) under test.

[0049] In one embodiment, the chip under test C of the present invention is a quad flat noleads (QFN) chip.

[0050] The chip testing method of this invention eliminates the need for the cumbersome wire bonding step of known technologies because the electrical testing heads of the testing carrier directly contact the electrical contacts of the chip under test. Furthermore, the tested chip can be easily removed and reused. Additionally, the testing carrier and the chip under test can be fed together into an optical testing device for optical testing, thus simplifying the testing process and improving testing efficiency.

[0051] Although the present invention has been described above with reference to specific preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A chip detection method, characterized in that, include: A testing carrier is provided, wherein the testing carrier includes a carrier body, a plurality of electrical testing heads and a testing unit, a groove is formed on the carrier body, the plurality of electrical testing heads are coupled to the testing unit, the plurality of electrical testing heads are located in the groove, and the testing unit is disposed on the carrier body; A chip under test is provided, wherein the chip under test includes a first surface, a second surface and a plurality of electrical contacts, the first surface being opposite to the second surface, and the plurality of electrical contacts being distributed on the edge of the chip under test; The chip under test is placed in the groove, and the plurality of electrical detection heads directly abut against the plurality of electrical contacts. The detection unit detects the chip through the plurality of electrical detection heads. The plurality of electrical detection heads and the plurality of electrical contacts are not connected by wire bonding. The first surface is opposite to the second surface. At least part of each electrical contact is located on the second surface. When the chip under test is placed in the groove, the first surface faces the groove. Before placing the chip under test into the recess, a portion of the structure on the second surface of the chip is removed to expose the back side of the chip under test; and An optical inspection device is provided to perform optical inspection on the second surface of the chip when the chip under test is placed in the groove.

2. The chip detection method as described in claim 1, characterized in that, The chip under test includes multiple chip sidewalls, and each electrical contact is located at least partially on one of the chip sidewalls. The multiple electrical detection heads extend toward the multiple chip sidewalls and directly abut against the multiple electrical contacts.

3. The chip detection method as described in claim 1, characterized in that, The plurality of electrical detection heads include spring pin connectors or gold finger springs.

4. The chip detection method as described in claim 1, characterized in that, The chip under test has a metal ground layer located on the second surface; in the step of removing part of the structure on the second surface of the chip, the metal ground layer is completely or partially removed.

5. The chip detection method as described in claim 1, characterized in that, The carrier body includes a body surface, and when the chip under test is placed in the groove, the height of the second surface of the chip under test is equal to or lower than the height of the body surface.

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