Control circuit and control method

Abstract

A control circuit and control method are disclosed. The control circuit includes an orthogonal decoding circuit, a counting circuit, and a truncation circuit. The orthogonal decoding circuit generates a first edge signal and a first direction signal based on a first external signal and a second external signal. The counting circuit performs a counting operation based on the first edge signal and the first direction signal. When a timing signal is enabled, the truncation circuit blocks the first edge signal and the first direction signal from entering the counting circuit and provides a second edge signal and a second direction signal to the counting circuit, causing the counting circuit to perform a counting operation based on the second edge signal and the second direction signal.

Description

Technical Field

[0001] The present invention relates to a control circuit and a control method, and more particularly to a control circuit and a control method with an orthogonal mode and a timing mode. Background Art

[0002] With technological advancements, microcontroller units (MCUs) are becoming increasingly versatile. For example, a MCU may include a quadrature decoder to decode signals from a quadrature encoder interface (QEI). However, when the MCU does not receive signals from the QEI, some components within the MCU become idle. Summary of the Invention

[0003] One embodiment of the present invention provides a control circuit comprising an orthogonal decoding circuit, a counting circuit, and a truncation circuit. The orthogonal decoding circuit generates a first edge signal and a first direction signal based on a first external signal and a second external signal. The counting circuit performs a counting operation based on the first edge signal and the first direction signal. When a timing signal is enabled, the truncation circuit blocks the first edge signal and the first direction signal from entering the counting circuit and provides a second edge signal and a second direction signal to the counting circuit, causing the counting circuit to perform a counting operation based on the second edge signal and the second direction signal.

[0004] The present invention further provides a control method, comprising processing a first external signal and a second external signal to generate an edge signal and a direction signal; determining whether a timing signal is enabled; when the timing signal is not enabled, performing a counting operation according to the edge signal and the direction signal; and when the timing signal is enabled, performing a counting operation according to a system clock.

[0005] The control method of the present invention can be implemented via the control circuit of the present invention, which is hardware or software capable of performing specific functions. Alternatively, the control method can be implemented via program code stored on a recording medium and combined with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes the control circuit for implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Schematic diagram of the control system of the present invention.

[0007] Figure 2 FIG. 2 is another schematic diagram of the control system of the present invention.

[0008] Figure 3FIG. 4 is a schematic diagram of an orthogonal decoding circuit according to the present invention.

[0009] Figure 4 FIG. 4 is another schematic diagram of the orthogonal decoding circuit of the present invention.

[0010] Figure 5 FIG. 4 is another schematic diagram of the orthogonal decoding circuit of the present invention.

[0011] Figure 6A FIG. 1 is a schematic diagram illustrating the operation of the control circuit 110 in the quadrature mode.

[0012] Figure 6B FIG. 1 is a schematic diagram illustrating the operation of the control circuit 110 in the timing mode.

[0013] Figure 7 Schematic diagram of the control method of the present invention.

[0014] Figure Number:

[0015] 100, 200: control system

[0016] 110, 210: Control circuit

[0017] 120, 220: CPU

[0018] CLK: system clock

[0019] CV: count value

[0020] FL: Interrupt signal

[0021] 111, 211, 300: Orthogonal decoding circuit

[0022] 112, 114, 212, 450, 550: Cut-off circuit

[0023] 113, 213: Counting circuit

[0024] QA, QB: external signals

[0025] S E1 、S E2 : Edge signal

[0026] S D1 、S D2 : Direction signal

[0027] S T : Timing signal

[0028] ORA, ORB: OR gate

[0029] 230: Clock generator

[0030] 240: Input and output interface

[0031] MT: Motor

[0032] 250: Sensing circuit

[0033] 310, 410, 510: Processing circuit

[0034] 320, 420, 520: Quadrature mode circuits

[0035] 330, 430, 530: edge detectors

[0036] 340, 440, 540: Direction detector

[0037] SC1, SC2: control signals

[0038] CHA, CHB: output signal

[0039] IVA, IVB, INS: Inverted signals

[0040] 311, 312: Inverter

[0041] 313, 314: Multiplexer

[0042] OA, OB, CHA, CHB, MA1, MA2, MB1, MB2: output signals

[0043] 451: Inverter

[0044] 452, 453: AND gate

[0045] S711~S714: Steps DETAILED DESCRIPTION

[0046] To make the objectives, features, and advantages of the present invention more readily apparent, the following examples are presented and described in detail with reference to the accompanying drawings. This specification provides various examples to illustrate the technical features of various embodiments of the present invention. The configurations of the various components in the examples are for illustrative purposes only and are not intended to limit the present invention. Furthermore, some duplication of figure numerals in the examples is for simplification and does not imply a correlation between the different examples.

[0047] Figure 1 Schematic diagram of the control system of the present invention. Figure 1As shown, control system 100 includes a control circuit 110 and a central processing unit (CPU) 120. Control circuit 110 and CPU 120 receive a system clock CLK. CPU 120 operates based on system clock CLK. In one embodiment, system clock CLK is generated by a clock generator (not shown) within control system 100. The present invention is not limited to the type of control system 100. In one embodiment, control system 100 is a microcontroller unit (MCU).

[0048] In this embodiment, the control circuit 110 may operate in a quadrature mode or a timer mode. In the quadrature mode, the control circuit 110 counts the transitions of the external signal QA and the external signal QB to adjust a count value CV. The external signal QA and the external signal QB may be provided by a sensing device. The sensing device may generate the external signal QA and the external signal QB based on the speed and direction of a motor. In the quadrature mode, the central processing unit 120 obtains the operating status (such as the speed and direction) of the external device (such as the motor) based on the count value CV. In other embodiments, when the control circuit 110 sends an interrupt signal FL, the central processing unit 120 may read the count value CV to determine whether an abnormality has occurred in the external device (not shown). In one possible embodiment, when the external device is abnormal, the central processing unit 120 may turn off the external device.

[0049] In a timing mode, the control circuit 110 performs a counting operation based on the system clock CLK. In this mode, the control circuit 110 functions as a timer. When the duration of the counting operation performed by the control circuit 110 reaches a target value, the control circuit 110 issues an interrupt signal FL to interrupt the operation of the central processing unit 120. The present invention is not limited to the architecture of the control circuit 110. In one embodiment, the control circuit 110 includes a quadrature encoder circuit 111, a truncation circuit 112, and a counting circuit 113.

[0050] The orthogonal decoding circuit 111 generates an edge signal S according to the external signal QA and the external signal QB. E1 and a direction signal S D1 In one embodiment, the external signal QA and the external signal QB are provided by an external device (located outside the control system 100). The present invention does not limit the architecture of the orthogonal decoding circuit 111. Figure 3A possible implementation of the orthogonal decoding circuit 111 is described. In this embodiment, when the control circuit 110 enters an orthogonal mode, the orthogonal decoding circuit 111 operates normally. When the control circuit 110 enters a timing mode, the orthogonal decoding circuit 111 may continue to operate or stop operating.

[0051] The cutoff circuit 112 is based on the edge signal S E1 , direction signal S D1 and a timing signal S T , generating an edge signal S E2 and a direction signal S D2 For example, when the timing signal S T When it is not enabled, it means that the timer function is not enabled. Therefore, the cutoff circuit 112 turns the edge signal S E1 and direction signal S D1 Directly as edge signal S E2 and direction signal S D2 When the timing signal S T When enabled, the timer function is turned on. Therefore, the cutoff circuit 112 ignores the edge signal S E1 and direction signal S D1 In one embodiment, the cutoff circuit 112 sets the edge signal S E2 and direction signal S D2 = is equal to a preset level, such as a high level. In other embodiments, the timing signal S T When enabled, the cutoff circuit 112 turns the timing signal S T As the edge signal S E2 and direction signal S D2 .

[0052] The present invention does not limit the structure of the cutoff circuit 112. In one embodiment, the cutoff circuit 112 is a multiplexer (not shown). T When not enabled, the cutoff circuit 112 turns the edge signal S E1 and direction signal S D1 As the edge signal S E2 and direction signal S D2 When the timing signal S T When enabled, the cutoff circuit 112 turns the timing signal S T As the edge signal S E2 and direction signal S D2 .

[0053] In this embodiment, the cutoff circuit 112 includes OR gates ORA and ORB. The OR gate ORA generates an edge signal S E1 and timing signal S T , generating edge signal SE2 For example, when the timing signal S T When enabled, the timing signal S T Therefore, the OR gate ORA turns the timing signal S T As the edge signal S E2 When the timing signal S T When not enabled, the timing signal S T Therefore, the OR gate ORA turns the edge signal S E1 As the edge signal S E2 The OR gate ORB is based on the direction signal S D1 and timing signal S T , generating direction signal S D2 For example, when the timing signal S T When enabled, the timing signal S T Therefore, the OR gate ORB turns the timing signal S T As direction signal S D2 When the timing signal S T When not enabled, the timing signal S T Therefore, the OR gate ORB turns the direction signal S D1 As direction signal S D2 .

[0054] The counting circuit 113 is based on the edge signal S E2 and direction signal S D2 , performs a counting operation to adjust the count value CV. In this embodiment, when the timing signal S T When not enabled, the cutoff circuit 112 converts the edge signal S E1 and direction signal S D1 As the edge signal S E2 and direction signal S D2 Therefore, the counting circuit 113 is based on the edge signal S E1 and direction signal S D1 In one embodiment, the counting circuit 113 adjusts the count value CV according to the edge signal S E1 Change the count value CV and adjust the direction signal S D1 Increase or decrease the count value CV.

[0055] For example, when the edge signal S E1 and direction signal S D1 When the level of the edge signal S is equal to a specific level (such as a high level), the counting circuit 113 increases the count value CV. E1 Equal to a specific level and direction signal S D1When the level of the edge signal S is not equal to the specific level, the counting circuit 113 decreases the count value CV. E1 When it is not equal to a specific level, regardless of the direction signal S D1 The counting circuit 113 stops adjusting the count value CV depending on whether the level of CV is equal to a specific level.

[0056] In other embodiments, when the timing signal S T When enabled, the cutoff circuit 112 sets the edge signal S E2 and direction signal S D2 is a fixed level. Therefore, the counting circuit 113 adjusts the count value CV according to the system clock CLK. When the count value CV reaches a target value, the counting circuit 113 issues an interrupt signal FL to interrupt the operation of the CPU 120. In one embodiment, the target value is stored in a compared value register.

[0057] In some embodiments, the control circuit 110 further includes a cutoff circuit 114. The cutoff circuit 114 receives the external signal QA and the external signal QB. T When not enabled, the cutoff circuit 114 transmits the external signal QA and the external signal QB to the orthogonal decoding circuit 111. The timing signal S T When enabled, the cutoff circuit 114 blocks the external signal QA and the external signal QB from entering the orthogonal decoding circuit 111. At this time, the orthogonal decoding circuit 111 may set the edge signal S E1 and direction signal S D1 is a fixed level, such as a high level. In this example, the edge signal S E1 and direction signal S D1 Directly as edge signal S E2 and direction signal S D2 , so the cutoff circuit 112 can be omitted.

[0058] Figure 2 This is another schematic diagram of a control system according to the present invention. In this embodiment, control system 200 is used to control the operation of motor MT. Motor MT has a built-in sensing circuit 250. Sensing circuit 250 detects the operation of motor MT and performs a quadrature encoding operation on the detection results to provide external signals QA and QB. In one embodiment, sensing circuit 250 has a quadrature encoder interface (QEI) for outputting external signals QA and QB.

[0059] The control system 200 includes a control circuit 210, a central processing unit 220, a clock generator 230, and an input / output interface 240. Figure 1 The characteristics of the control circuit 110 and the CPU 120 are similar, so they are not described in detail.

[0060] The clock generator 230 is used to generate the system clock CLK to the counting circuit 213 and the CPU 220. In other embodiments, the orthogonal decoding circuit 211 also receives the system clock CLK. In this embodiment, the input / output interface 240 is used to receive the external signal QA, the external signal QB and the timing signal S T In one embodiment, the input / output interface 240 includes a plurality of general-purpose input / output (GPIO) pins.

[0061] When the timing signal S T When disabled, the control circuit 210 enters a quadrature mode. The CPU 220 determines the operating status of the motor MT based on the count value CV. At this point, if the control circuit 210 issues an interrupt signal FL, it indicates that an abnormality has occurred in the motor MT. Therefore, the CPU 220 may instruct an external power supply (not shown) to stop supplying power to the motor MT.

[0062] When the timing signal S T When enabled, control circuit 210 enters a timing mode. In this mode, control circuit 210 ignores external signals QA and QB. Control circuit 210 performs a counting operation based on system clock CLK. In this mode, control circuit 210 functions as a timer. Transitions in external signals QA and QB do not affect count value CV.

[0063] Figure 3 This is a schematic diagram of an orthogonal decoding circuit according to the present invention. As shown, orthogonal decoding circuit 300 includes a processing circuit 310, a quadrature mode circuit 320, an edge detector 330, and a direction detector 340. The present invention is not limited to the architecture of orthogonal decoding circuit 300. Any circuit capable of counting transitions of external signals QA and QB can serve as orthogonal decoding circuit 300.

[0064] The processing circuit 310 receives external signals QA and QB and generates output signals CHA and CHB based on a control signal SC1. For example, when the control signal SC1 is at a low level, the processing circuit 310 directly uses the external signals QA and QB as the output signals CHA and CHB. When the control signal SC1 is at a high level, the processing circuit 310 inverts the external signals QA and QB to generate inverted signals IVA and IVB, which are then used as the output signals CHA and CHB.

[0065] In this embodiment, the processing circuit 310 includes inverters 311 and 312 and multiplexers 313 and 314. The inverter 311 inverts the external signal QA to generate an inverted signal IVA. The inverter 312 inverts the external signal QB to generate an inverted signal IVB. The multiplexer 313 receives the external signal QA and the inverted signal IVA and, based on a control signal SC1, outputs the external signal QA or the inverted signal IVA as an output signal CHA. The multiplexer 314 receives the external signal QB and the inverted signal IVB and, based on a control signal SC1, outputs the external signal QB or the inverted signal IVB as an output signal CHB.

[0066] Quadrature-mode circuit 320 receives output signals CHA and CHB and generates output signals OA and OB based on a control signal SC2. For example, when control signal SC2 is disabled (e.g., at a low level), quadrature-mode circuit 320 generates output signals CHA and CHB as output signals OA and OB. When control signal SC2 is enabled (e.g., at a high level), quadrature-mode circuit 320 generates output signals CHA and CHB as output signals OB and OA. In some embodiments, quadrature-mode circuit 320 can be referred to as a switching circuit.

[0067] The edge detector 330 detects the edges of the output signals OA and OB to generate an edge signal S E1 The present invention does not limit the circuit architecture of the edge detector 330 . Any circuit capable of detecting a signal edge can be used as the edge detector 330 .

[0068] The direction detector 340 generates a direction signal S according to the output signals OA and OB. D1 In one embodiment, when the output signal OA leads the output signal OB, the direction signal S D1 When the output signal OA lags behind the output signal OB, the direction signal S D1The present invention does not limit the circuit architecture of the direction detector 340 . Any circuit that can determine whether the output signal OA leads the output signal OB based on the output signal OA and the output signal OB can be used as the direction detector 340 .

[0069] Figure 4 FIG. 4 is another schematic diagram of the orthogonal decoding circuit of the present invention. Figure 4 resemblance Figure 3 , the difference is that the orthogonal decoding circuit 400 further includes a truncation circuit 450. Figure 4 The characteristics of the processing circuit 410, the orthogonal mode circuit 420, the edge detector 430 and the direction detector 440 are similar to those of Figure 3 The characteristics of the processing circuit 310, the orthogonal mode circuit 320, the edge detector 330 and the direction detector 340 are not described in detail.

[0070] The cutoff circuit 450 is coupled between the processing circuit 410 and the quadrature mode circuit 420 to block the output signals MA1 and MB1 of the processing circuit 410 from entering the quadrature mode circuit 420. For example, when the timing signal S T When not enabled (eg, at a low level), the cutoff circuit 450 uses the output signals MA1 and MB1 as the output signals CHA and CHB. T When enabled (eg, a high level), the cutoff circuit 450 sets the output signal CHA and the output signal CHB to a predetermined level (eg, a low level).

[0071] The present invention does not limit the structure of the cutoff circuit 450. Any circuit that can block the output signal MA1 and the output signal MB1 from entering the orthogonal mode circuit 420 can be used as the cutoff circuit 450. In this embodiment, the cutoff circuit 450 includes an inverter 451 and AND gates 452 and 453. The inverter 451 inverts the timing signal S T , for generating an inverting signal INS.

[0072] AND gate 452 receives output signal MA1 and inverted signal INS. T When the AND gate 452 is not enabled, the output signal MA1 is used as the output signal CHA. T When enabled, the AND gate 452 outputs the inverted signal INS as the output signal CHA. The AND gate 453 receives the output signal MB1 and the inverted signal INS. T When the AND gate 453 is not enabled, the output signal MB1 is used as the output signal CHB. T When enabled, the AND gate 453 outputs the inverted signal INS as the output signal CHB.

[0073] In some embodiments, quadrature mode circuit 420, edge detector 430, and direction detector 440 operate based on a system clock CLK. For example, quadrature mode circuit 420 generates output signals OA and OB based on the system clock CLK. Edge detector 430 detects edges in output signals OA and OB based on the system clock CLK. Direction detector 440 determines whether output signal OA leads output signal OB based on the system clock CLK.

[0074] Figure 5 FIG. 4 is another schematic diagram of the orthogonal decoding circuit of the present invention. Figure 5 resemblance Figure 3 , the difference is that the orthogonal decoding circuit 500 further includes a truncation circuit 550. Figure 5 The characteristics of the processing circuit 510, the orthogonal mode circuit 520, the edge detector 530 and the direction detector 540 are similar to those of Figure 3 The characteristics of the processing circuit 310, the orthogonal mode circuit 320, the edge detector 330 and the direction detector 340 are not described in detail.

[0075] The cutoff circuit 550 is coupled to the processing circuit 510 and is used to block the external signal QA and the external signal QB from entering the processing circuit 510. The present invention is not limited to the structure of the cutoff circuit 550. Any circuit that can block the external signal QA and the external signal QB from entering the processing circuit 510 can be used as the cutoff circuit 550. In this embodiment, the cutoff circuit 550 includes an inverter 551, an AND gate 552, and an AND gate 553. The inverter 551 inverts the timing signal S T , used to generate an inverting signal INS.

[0076] AND gate 552 receives external signal QA and inverted signal INS. T When not enabled, the AND gate 552 takes the external signal QA as the output signal MA2. T When enabled, the AND gate 552 outputs the inverted signal INS as the output signal MA2. The AND gate 553 receives the external signal QB and the inverted signal INS. T When not enabled, the AND gate 553 uses the external signal QB as the output signal MB2. T When enabled, the AND gate 553 outputs the inverted signal INS as the output signal MB2 .

[0077] Figure 6A This is a schematic diagram of the operation of the control circuit 110 in the quadrature mode. TWhen not enabled, the control circuit 110 enters the quadrature mode. In the quadrature mode, the control circuit 110 adjusts the count value CV according to the external signal QA and the external signal QB. Figure 1 For example, the orthogonal decoding circuit 111 generates an edge signal S according to the external signal QA and the external signal QB. E1 With direction signal S D1 The cutoff circuit 112 converts the edge signal S E1 With direction signal S D1 As the edge signal S E2 With direction signal S D2 The counting circuit 113 counts according to the edge signal S E2 With direction signal S D2 , adjust the count value CV.

[0078] At time T1, the level of the system clock CLK changes from a low level to a high level. At this time, the edge signal S E2 With direction signal S D2 Therefore, the counting circuit 113 increases the value CV from 0 to 1. At time T2, the level of the system clock CLK changes from low level to high level again. At this time, the edge signal S E2 is low, and the direction signal S D2 = is high. Therefore, the counting circuit 113 does not adjust the count value CV. At this time, the count value CV is maintained at 1.

[0079] At time T3, the level of the system clock CLK changes from low level to high level. At this time, the edge signal S E2 With direction signal S D2 Therefore, the counting circuit 113 increases the value CV from 1 to 2. At time T4, the level of the system clock CLK changes from low level to high level again. At this time, the edge signal S E2 is low, and the direction signal S D2 = is high. Therefore, the counting circuit 113 does not adjust the count value CV. At this time, the count value CV is maintained at 2.

[0080] At time T5, the level of the system clock CLK changes from low level to high level. At this time, the edge signal S E2 With direction signal S D2 Therefore, the counting circuit 113 increases the value CV from 2 to 3. At time T6, the level of the system clock CLK changes from low level to high level again. At this time, the edge signal S E2 is low, and the direction signal S D2 = is high. Therefore, the counting circuit 113 does not adjust the count value CV. At this time, the count value CV is maintained at 3.

[0081] At time T7 and T8, the level of the system clock CLK changes from low level to high level again. E2 and direction signal S D2 Therefore, the counting circuit 113 does not adjust the count value CV. At this time, the count value CV is maintained at a value of 3.

[0082] At time T9, the level of the system clock CLK changes from low level to high level. At this time, the edge signal S E2 is high, and the direction signal S D2 Therefore, the counting circuit 113 reduces the value CV, such as from 3 to 2. At time T 10 , the level of the system clock CLK changes from low level to high level again. At this time, the edge signal S E2 and direction signal S D2 Therefore, the counting circuit 113 does not adjust the count value CV. At this time, the count value CV is maintained at a value of 2.

[0083] At time T 11 , the level of the system clock CLK changes from low level to high level. At this time, the edge signal S E2 is high, and the direction signal S D2 Therefore, the counting circuit 113 reduces the value CV, such as from 2 to 1. At time T 12 , the level of the system clock CLK changes from low level to high level again. At this time, the edge signal S E2 and direction signal S D2 Therefore, the counting circuit 113 does not adjust the count value CV. At this time, the count value CV remains at 1. 13 , the level of the system clock CLK changes from low level to high level. At this time, the edge signal S E2 is high, and the direction signal S D2 Therefore, the counting circuit 113 decreases the value CV, for example, from the value 1 to the value 0.

[0084] Figure 6B This is a schematic diagram of the operation of the control circuit 110 in the timing mode. T When enabled, the control circuit 110 enters the timing mode. In the timing mode, the control circuit 110 adjusts the count value CV according to the system clock CLK. Figure 1 For example, the cutoff circuit 112 blocks the edge signal S E1 With direction signal S D1 Enter the counting circuit 113. In one embodiment, the cut-off circuit 112 sets the edge signal SE1 With direction signal S D1 In this example, whenever the system clock CLK changes from a low level to a high level, the counting circuit 113 adjusts the count value CV. When the count value CV reaches a target value (eg, 14), the counting circuit 113 may issue an interrupt signal FL.

[0085] Figure 7 is a flow chart of the control method of the present invention. The control method of the present invention is applicable to a microcontroller unit. First, a first external signal and a second external signal are processed to generate an edge signal and a direction signal (step S711). In one possible embodiment, if the external device providing the first external signal and the second external signal defines a level differently from the microcontroller unit's definition of a level, step S711 inverts the levels of the first external signal and the second external signal. For example, assume that the external device defines 3.3V as a high level and 0V as a low level, but the microcontroller unit defines 0V as a high level and 3.3V as a low level. In this example, step S711 inverts the first external signal and the second external signal.

[0086] In other embodiments, if the first external signal provided by the external device is an edge signal and the second external signal is a direction signal, step S711 uses the first external signal as the edge signal and the second external signal as the direction signal. However, if the first external signal provided by the external device is a direction signal and the second external signal is an edge signal, step S711 uses the second external signal as the edge signal and the first external signal as the direction signal.

[0087] Next, a determination is made as to whether a timing signal is enabled (step S712). In one embodiment, step S712 detects the level of an input / output pin of the microcontroller unit. When the level of the input / output pin is equal to a specific level (e.g., a high level), it indicates that the timing signal is enabled. When the level of the input / output pin is not equal to the specific level, it indicates that the timing signal is not enabled.

[0088] When the timing signal is enabled, a counting operation is performed according to a system clock (step S713). For example, when the system clock changes from a first level to a second level, step S713 gradually increases a count value. In one possible embodiment, step S713 may gradually decrease the count value. In other embodiments, when the system clock changes from the second level to the first level, step S713 also adjusts the count value. When the count value reaches a target value, step S713 also sends an interrupt signal to interrupt the operation of a central processing unit. In some embodiments, when the timing signal is enabled, step S713 sets the levels of the edge signal and the direction signal to be equal to the level of the timing signal.

[0089] When the timing signal is not enabled, a counting operation is performed based on the edge signal and the direction signal (step S714). For example, when the levels of the edge signal and the direction signal are both equal to a specific level (e.g., a high level), step S714 increments the count value. When the edge signal is equal to the specific level and the level of the direction signal is not equal to the specific level, step S714 decrements the count value. When the levels of the edge signal and the direction signal are not equal to the specific level, step S714 stops adjusting the count value.

[0090] Since the MCU can not only adjust the count value according to external signals (such as external signal QA and external signal QB), but also ignore the external signals and adjust the count value only according to the system clock, it can provide flexibility in the use of the MCU and increase the efficiency of the MCU.

[0091] It should be understood that when an element or layer is referred to as being “coupled” to another element or layer, it can be directly coupled or connected to the other element or layer, or there can be other elements or layers intervening therebetween. Conversely, when an element or layer is “connected” to another element or layer, there can be no other elements or layers intervening therebetween.

[0092] The control method of the present invention, or a specific form or portion thereof, can exist in the form of program code. The program code can be stored on a physical medium, such as a floppy disk, a CD, a hard disk, or any other machine-readable (e.g., computer-readable) storage medium, or a computer program product in an external form, wherein when the program code is loaded and executed by a machine, such as a computer, the machine becomes configured to participate in the control circuit and control system of the present invention. The program code can also be transmitted via some transmission medium, such as a wire or cable, an optical fiber, or any other transmission mode, wherein when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes configured to participate in the control circuit and control system of the present invention. When implemented on a general-purpose processing unit, the program code, in combination with the processing unit, provides a unique device that operates similarly to an application-specific logic circuit.

[0093] Unless otherwise defined, all terms used herein (including technical and scientific terms) are those generally understood by those skilled in the art. Furthermore, unless otherwise expressly stated, dictionary definitions of terms should be interpreted as consistent with their meanings in articles in the relevant technical field and should not be interpreted as idealized or overly formal. While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another.

[0094] While the present invention has been disclosed above with reference to preferred embodiments, these are not intended to limit the present invention. Any skilled artisan may make modifications and variations without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented in hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

Claims

1. A control circuit, characterized in that: include: an orthogonal decoding circuit, generating a first edge signal and a first direction signal according to a first external signal and a second external signal; a counting circuit, performing a counting operation according to a second edge signal and a second direction signal; and a first cutoff circuit, configured to set the second edge signal and the second direction signal according to a timing signal; in, When the timing signal is not enabled, The first truncation circuit uses the first edge signal and the first direction signal as the second edge signal and the second direction signal, respectively, or the orthogonal decoding circuit uses the first edge signal and the first direction signal as the second edge signal and the second direction signal, respectively; The counting circuit adjusts a counting value according to the second edge signal and the second direction signal; When the timing signal is enabled, The first cutoff circuit sets the second edge signal and the second direction signal to a fixed level, or blocks the first external signal and the second external signal from entering the orthogonal decoding circuit, so that the orthogonal decoding circuit sets the first edge signal and the first direction signal to the fixed level; The counting circuit adjusts the counting value according to a system clock.

2. The control circuit according to claim 1, wherein: The first truncation circuit is coupled between the orthogonal decoding circuit and the counting circuit. When the timing signal is not enabled, the first truncation circuit provides the first edge signal and the first direction signal to the counting circuit, so that the counting circuit performs the counting operation according to the first edge signal and the first direction signal.

3. The control circuit according to claim 1, wherein: When the timing signal is enabled, the second edge signal is the same as the second direction signal.

4. The control circuit according to claim 3, characterized in that: When the timing signal is enabled, the first cutoff circuit uses the timing signal as the second edge signal and the second direction signal.

5. The control circuit according to claim 1, wherein: When the timing signal is not enabled, the counting circuit determines the levels of the first edge signal and the first direction signal; When the levels of the first edge signal and the first direction signal are both equal to a set level, the counting circuit increases the count value; When the first edge signal is equal to the set level and the level of the first direction signal is not equal to the set level, the counting circuit decreases the count value; When the levels of the first edge signal and the first direction signal are not equal to the set level, the counting circuit stops adjusting the count value.

6. The control circuit according to claim 1, wherein: The first cutoff circuit includes: a first OR gate receiving the first edge signal and the timing signal, wherein when the timing signal is enabled, the first OR gate uses the timing signal as the second edge signal; and A second OR gate receives the first direction signal and the timing signal. When the timing signal is enabled, the second OR gate uses the timing signal as the second direction signal.

7. The control circuit according to claim 1, wherein: The orthogonal decoding circuit comprises: a processing circuit that processes the first external signal and the second external signal as a first output signal and a second output signal, or inverts the first external signal and the second external signal to generate a first inverted signal and a second inverted signal, and processes the first inverted signal and the second inverted signal as the first output signal and the second output signal; a switching circuit that converts the first output signal and the second output signal into a third output signal and a fourth output signal, or converts the first output signal and the second output signal into the fourth output signal and the third output signal; an edge detector for detecting edges of the third output signal and the fourth output signal to generate the first edge signal; and A direction detector generates the first direction signal according to the third output signal and the fourth output signal.

8. A control method, applied to the control circuit according to claim 1, characterized in that: include: Processing a first external signal and a second external signal to generate an edge signal and a direction signal; determining whether a timing signal is enabled; When the timing signal is not enabled, performing a counting operation according to the edge signal and the direction signal; as well as When the timing signal is enabled, the counting operation is performed according to a system clock.

9. The control method according to claim 8, characterized in that: When the timing signal is enabled, the steps of performing the counting operation according to the system clock include: setting the levels of the edge signal and the direction signal to be equal to the level of the timing signal; and The number of pulses of the system clock is counted to adjust a count value.

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