Current receiving circuit and method for determining input current thereof

Abstract

The application discloses a current receiving circuit and a method for determining input current of the current receiving circuit. The current receiving circuit comprises a current sampling circuit, a voltage switching circuit, an integration circuit, a comparison circuit and a reference voltage circuit. The current sampling circuit, the voltage switching circuit, the integration circuit and the comparison circuit are connected in series, and the output of the comparison circuit is fed back to the voltage switching circuit. The reference voltage circuit provides a bias voltage end and a negative constant voltage end. The bias voltage end is connected to the current sampling circuit and the integration circuit, and the negative constant voltage end is connected to the voltage switching circuit. The duty cycle is formed by the high and low levels output by the comparison circuit, and the input current of the current receiving circuit is directly converted according to the duty cycle. Any parameter characteristics of the optocoupler do not need to be considered, so that the temperature drift coefficient and the linearity of the optocoupler do not affect the current transmission accuracy of the circuit, and the whole circuit does not need to be calibrated before leaving the factory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a current receiving circuit and a method for determining input current of the current receiving circuit. BACKGROUND

[0002] In the range of analog signal transmission, a current receiving circuit with 4-20mA is generally used for transmission. At present, the current receiving circuit with 4-20mA adopts IV conversion, that is, a special chip or an operational amplifier is used to convert current into voltage.

[0003] In the industrial application scene, various types of EMC (electromagnetic compatibility) interference exist due to complex electric field conditions, so the current receiving circuit and the main control circuit need to be isolated. At present, an optical coupler is used as an isolation signal transmission medium.

[0004] The optical coupler is a semiconductor analog device, and the linearity, temperature drift coefficient and consistency of the current transfer ratio (CTR) of the optical coupler are poor. Therefore, the optical coupler needs to be calibrated before leaving the factory. For mass production, such a calibration process will reduce the production capacity. Even if the calibration is performed before leaving the factory, only the accuracy of the thousandth level can be achieved under specific temperature and voltage conditions. With the change of temperature and voltage, the current transmission accuracy of the current receiving circuit deviates greatly. SUMMARY

[0005] The present application aims at the deficiencies of the prior art and provides a current receiving circuit without calibration and a method for determining input current of the current receiving circuit. The purpose is achieved by the following technical scheme.

[0006] The first aspect of the present application provides a current receiving circuit, which comprises a current sampling circuit, a voltage switching circuit, an integration circuit, a comparison circuit and a reference voltage circuit.

[0007] The current sampling circuit, the voltage switching circuit, the integration circuit and the comparison circuit are connected in series, and the output end of the comparison circuit is fed back to the voltage switching circuit.

[0008] The reference voltage circuit provides a bias voltage end and a negative constant voltage end. The bias voltage end is connected to the current sampling circuit and the integration circuit, and the negative constant voltage end is connected to the voltage switching circuit.

[0009] In some embodiments of the present application, the current sampling circuit comprises a current input end, a voltage output end, a transient diode, a first diode, a second diode, and a first resistor; wherein the current input end is connected to one end of the transient diode, the positive electrode of the first diode, the negative electrode of the second diode, one end of the first resistor, and the voltage output end through a fuse line respectively; the other end of the transient diode, the negative electrode of the first diode, the positive electrode of the second diode, and the other end of the first resistor are all connected to the bias voltage end.

[0010] In some embodiments of the present application, the voltage switching circuit comprises an analog switch; the first channel input end of the analog switch is connected to the negative constant voltage end; the second channel input end of the analog switch is connected to the voltage output end of the current sampling circuit; the control end of the analog switch is connected to the output end of the comparison circuit; the output end of the analog switch is connected to the integration circuit.

[0011] In some embodiments of the present application, the voltage switching circuit comprises a controlled switch and a second resistor; the control end of the controlled switch is connected to the output end of the comparison circuit; the output end of the controlled switch is connected to one end of the second resistor; the other end of the second resistor is connected to the integration circuit.

[0012] In some embodiments of the present application, the controlled switch is any one of a field effect transistor, a triode, or an analog switch.

[0013] In some embodiments of the present application, the integration circuit comprises a first operational amplifier, a third resistor, and a first capacitor;

[0014] The first input end of the first operational amplifier is connected to the output end of the first operational amplifier through the first capacitor; the first input end of the first operational amplifier is also connected to the voltage switching circuit through the third resistor; the second input end of the first operational amplifier is connected to the bias voltage end.

[0015] In some embodiments of the present application, the comparison circuit comprises a second operational amplifier, a fourth resistor, a fifth resistor, and a sixth resistor; the first input end of the second operational amplifier is connected to the integration circuit; the second input end of the second operational amplifier is connected to the output end of the second operational amplifier through the fourth resistor; the second input end of the second operational amplifier is also connected to ground through the fifth resistor, and to the power supply end provided by the current receiving circuit through the sixth resistor.

[0016] In some embodiments of the present application, the comparison circuit comprises a comparator, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; a first input terminal of the comparator is connected to the integration circuit; a second input terminal of the comparator is connected to an output terminal of the comparator through the fourth resistor; the second input terminal of the comparator is grounded through the fifth resistor, and is also connected to a power supply terminal provided by the current receiving circuit through the sixth resistor; the output terminal of the comparator is connected to the power supply terminal provided by the current receiving circuit through the seventh resistor.

[0017] In some embodiments of the present application, the reference voltage circuit comprises a bias voltage circuit and a negative constant voltage circuit; a bias voltage provided by the bias voltage circuit is input to the negative constant voltage circuit through the bias voltage terminal; a negative constant voltage provided by the negative constant voltage circuit is input to the voltage switching circuit through the negative constant voltage terminal.

[0018] In some embodiments of the present application, the bias voltage circuit comprises a first voltage follower, an eighth resistor, and a ninth resistor; the first voltage follower outputs the bias voltage; an input terminal of the first voltage follower is grounded through the eighth resistor, and is also connected to a power supply terminal provided by the current receiving circuit through the ninth resistor.

[0019] In some embodiments of the present application, the bias voltage circuit comprises a first reference source; an input terminal of the first reference source is connected to a power supply terminal provided by the current receiving circuit; an output terminal of the first reference source serves as the bias voltage terminal, and the output terminal of the first reference source is grounded through a second capacitor.

[0020] In some embodiments of the present application, the negative constant voltage circuit comprises a second voltage follower and a second reference source; the second voltage follower outputs the negative constant voltage; an input terminal of the second voltage follower is connected to the second reference source through voltage dividing resistors connected in parallel; two terminals of the second reference source are connected in series with a tenth resistor and the bias voltage terminal to provide an initial negative voltage, and one end of the tenth resistor away from the second reference source is grounded.

[0021] The second aspect of the present application provides a method for determining an input current of a current receiving circuit, the method comprising:

[0022] obtaining a high level output time of an output terminal of the comparison circuit, and obtaining a low level output time of the output terminal of the comparison circuit;

[0023] determining an output duty cycle of the current receiving circuit by using the high level output time and the low level output time;

[0024] determining the input current according to the duty cycle.

[0025] Based on the current receiving circuit and the method for determining input current according to the first aspect and the second aspect, the present application has the following advantages:

[0026] The current receiving circuit is composed of a current sampling circuit, a voltage switching circuit, an integration circuit, a comparison circuit and a reference voltage circuit. The duty cycle is composed of high and low levels output by the comparison circuit. The input current of the current receiving circuit is directly converted according to the duty cycle. Therefore, the temperature drift coefficient and the linearity of the optocoupler do not affect the current transmission accuracy of the circuit. Therefore, the circuit does not need to be calibrated before leaving the factory, and the production capacity of batch production can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application. Those skilled in the art can obtain other drawings according to the structures shown in these drawings without creative labor.

[0028] Figure 1 The structure diagram of a current receiving circuit according to an exemplary embodiment of the present application is shown.

[0029] Figure 2 The specific circuit structure diagram of a current receiving circuit according to an exemplary embodiment of the present application is shown.

[0030] Figure 3 The specific circuit structure diagram of another current receiving circuit according to an exemplary embodiment of the present application is shown.

[0031] Figure 4 The specific circuit structure diagram of another current receiving circuit according to an exemplary embodiment of the present application is shown.

[0032] Figure 5 The specific circuit structure diagram of another current receiving circuit according to an exemplary embodiment of the present application is shown.

[0033] Figure 6 The specific circuit structure diagram of another current receiving circuit according to an exemplary embodiment of the present application is shown.

[0034] Figure 7 The specific circuit structure diagram of another current receiving circuit according to an exemplary embodiment of the present application is shown.

[0035] Figure 8An embodiment flow chart of a method for determining input current of a current receiving circuit according to an exemplary embodiment of the present application is shown.

[0036] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort fall within the protection scope of the present application.

[0038] It should be noted that all the directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the accompanying drawings), and if the certain posture changes, the directionality indications also change accordingly.

[0039] In addition, the descriptions such as “first”, “second” and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first”, “second” can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of “plurality” is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0040] In the present application, unless otherwise specifically defined and limited, the terms “connection”, “fixation” and the like should be understood in a broad sense, for example, “fixation” can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through an intermediate medium; can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise specifically limited. For a person of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0041] In addition, the technical solutions of each embodiment of the present application can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor is it within the protection scope required by the present application.

[0042] The prior art uses an optocoupler as a medium for isolated signal transmission, and the current transfer ratio of the optocoupler is poor in linearity. Even if a feedback type is used in the linear optocoupler, only another optical path with the same current transfer ratio is used for compensation. Because the current transfer ratio is the current ratio of the input and output of the optocoupler, both the input and the output are directly related to the corresponding power supply, so in addition to the temperature drift coefficient of the optocoupler affecting the transmission accuracy, the power supply voltage fluctuation also affects the transmission accuracy.

[0043] To this end, the present application provides the following embodiments to solve or improve the problems existing in the prior art. In order to enable personnel skilled in the art to better understand the present application scheme, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0044] Embodiment one:

[0045] Figure 1 A structure diagram of a current receiving circuit according to an exemplary embodiment of the present application is shown in FIG. 1, which includes a current sampling circuit 10, a voltage switching circuit 20, an integration circuit 30, a comparison circuit 40, and a reference voltage circuit 50. Figure 1

[0046] The current sampling circuit 10, the voltage switching circuit 20, the integration circuit 30, and the comparison circuit 40 are connected in series, and the output end DUTY_CYCLE of the comparison circuit 40 is fed back to the voltage switching circuit 20. Further, the reference voltage circuit 50 provides a bias voltage end Vref and a negative constant voltage end Vi-, the bias voltage end Vref is connected to the current sampling circuit 10 and the integration circuit 30, and the negative constant voltage end Vi- is connected to the voltage switching circuit 20.

[0047] The transmission principle of the current receiving circuit is that when there is current input in the current sampling circuit 10, the characteristics of the integration circuit 30 are used, i.e. the integration circuit 30 will generate a capacitor charging time and a capacitor discharging time, so that the comparison circuit 40 outputs high level in the charging time and outputs low level in the discharging time, forming a duty cycle of high and low levels, so that after the output end of the comparison circuit 40 is connected to the master control chip, the master control chip can directly convert the size of the input current according to the duty cycle.

[0048] ​Based on the above description, the whole current receiving circuit is formed by designing the current sampling circuit, the voltage switching circuit, the integration circuit, the comparison circuit and the reference voltage circuit, and the duty cycle is formed by the high and low levels output by the comparison circuit, and the input current of the current receiving circuit can be directly converted according to the duty cycle, without considering any parameter characteristics of the optocoupler, so that the temperature drift coefficient and the linearity of the optocoupler will not affect the current transmission accuracy of the circuit, and the circuit does not need to be calibrated before being shipped, so that the production capacity of batch production can be improved. Moreover, the influence of the voltage fluctuation of the power supply on the transmission accuracy can be excluded by using the proportional relationship of the high and low levels output by the circuit.

[0049] The specific circuit structure of the current receiving circuit proposed in the application will be described in detail below.

[0050] In a possible implementation manner, as shown in Figure 2 The current sampling circuit 10 includes a current input end AI1+, a voltage output end Vi+, a transient diode D1, a first diode D2, a second diode D3 and a first resistor R2. The current input end AI1+ is connected to one end of the transient diode D1, the anode of the first diode D2, the cathode of the second diode D3, one end of the first resistor R2 and the voltage output end Vi+ (high voltage end) through a fuse F1 respectively. The other end of the transient diode D1, the cathode of the first diode D2, the anode of the second diode D3 and the other end of the first resistor R2 are all connected to a bias voltage end Vref.

[0051] The fuse F1 plays a current limiting role, and the transient diode D1 (TVS, Transient Voltage Suppressor) prevents the EMC interference from affecting the subsequent circuit. The first diode D2 is connected in series in the circuit in the forward direction, and the second diode D3 is connected in series in the circuit in the reverse direction. By connecting one diode in series in the forward direction and one diode in series in the reverse direction, the input voltage is limited, so as to protect the subsequent devices. The first resistor R2 serves as a sampling resistor. After the current input end AI1+ has current input, a voltage difference (Vi+-Vref) is generated across the first resistor R2.

[0052] In a possible implementation manner, as shown in Figure 2 The voltage switching circuit 20 includes an analog switch U1. The first channel input end B1 of the analog switch U1 is connected to a negative constant voltage end Vi-. The second channel input end B2 of the analog switch U1 is connected to the voltage output end Vi+ of the current sampling circuit 10. The control end S of the analog switch U1 is connected to the output end DUTY_CYCLE of the comparison circuit 40. The output end A of the analog switch is connected to the integration circuit 30.

[0053] Among them, the control terminal S of the analog switch U1 controls the switching of the channel. When the control terminal S is low, the output terminal A outputs the voltage of the first channel input terminal B1. When the control terminal S is high, the output terminal A outputs the voltage of the second channel input terminal B2.

[0054] In another possible implementation, such as Figure 3 As shown, the voltage switching circuit 20 includes a controlled switch Q1 and a second resistor R12. The control terminal of the controlled switch Q1 is connected to the output terminal DUTY_CYCLE of the comparator circuit 30, the output terminal of the controlled switch Q1 is connected to one end of the second resistor R12, and the other end of the second resistor R12 is connected to the integrator circuit 30.

[0055] Specifically, the other end of the second resistor R12 is connected to the first input terminal (- terminal) of the first operational amplifier U2 in the integrator circuit 30, and is also connected to the third resistor R1 in the integrator circuit 30.

[0056] In this circuit, the second resistor R12 serves as a discharge resistor. Utilizing the characteristic that the discharge current is greater than the input current, the controlled switch Q1 is turned on during the discharge time of the first capacitor C1 in the integrator circuit 30. The current consumed during this turn-on is also the current i flowing through the second resistor R12. 放 =i 输入 +i C1 i 输入 The current input to the current input terminal AI1+, i C1 The current is that of the first capacitor C1.

[0057] It should be added that, by Figure 3 As can be seen, the second resistor R12 is connected in series with the controlled switch Q1 to form a voltage divider switching circuit. The circuit structure is simple and easy to implement, and does not require a negative reference power supply.

[0058] For example, the controlled switch Q1, in addition to employing Figure 3 In addition to the field-effect transistor shown, transistors or analog switches can also be used.

[0059] In one possible implementation, such as Figure 2 As shown, the integrating circuit 30 includes a first operational amplifier U2, a third resistor R1, and a first capacitor C1. The first input terminal (- terminal) of the first operational amplifier U2 is connected to the output terminal of the first operational amplifier through the first capacitor C1. The first input terminal of the first operational amplifier U2 is also connected to the output terminal A of the voltage switching circuit through the third resistor R1. The second input terminal (+ terminal) of the first operational amplifier U2 is connected to the bias voltage terminal Vref.

[0060] Wherein, the third resistor R1 is used as a current-limiting resistor, which is used to control the charging and discharging time of the first capacitor C1. The first operational amplifier U2 has a virtual short feature, i.e. the input voltage of the first input terminal is always equal to the input voltage of the second input terminal. At this time, if the input voltage of the third resistor R1 is greater than the input voltage of the second input terminal, i.e. the voltage of the bias voltage terminal Vref, then the current flows into the first capacitor C1 to charge it, so that the output voltage of the first operational amplifier U2 rises; on the contrary, if the input voltage of the third resistor R1 is less than the input voltage of the second input terminal, then the first capacitor C1 begins to discharge, so that the output voltage of the first operational amplifier U2 decreases.

[0061] In a possible implementation manner, as shown in Figure 2 the comparison circuit 40 includes the second operational amplifier U3, the fourth resistor R4, the fifth resistor R7, and the sixth resistor R3. The first input terminal (as the - terminal) of the second operational amplifier U3 is connected to the output terminal VC of the integration circuit, the second input terminal (as the + terminal) of the second operational amplifier U3 is connected to the output terminal DUTY_CYCLE (i.e. the output terminal of the comparison circuit 40) of the second operational amplifier U3 through the fourth resistor R4, the second input terminal of the second operational amplifier U3 is also connected to the ground through the fifth resistor R7, and is connected to the power supply terminal VCC provided by the current receiving circuit through the sixth resistor R3.

[0062] Wherein, the comparison circuit 40 composed of the second operational amplifier U3, the fourth resistor R4, the fifth resistor R7, and the sixth resistor R3 belongs to a hysteresis comparison circuit, wherein the second operational amplifier U3 is used as a comparator, i.e. when the voltage of the - terminal of the second operational amplifier U3 is greater than the voltage of the + terminal, the output terminal outputs a low level; when the voltage of the - terminal of the second operational amplifier U3 is less than the voltage of the + terminal, the output terminal outputs a high level.

[0063] However, because the fourth resistor R4 exists, the comparison conditions for the second operational amplifier U3 to output high and low levels change, i.e. when the voltage of the - terminal of the second operational amplifier U3 is greater than VCC*R7 / (R3||R4+R7), the output terminal DUTY_CYCLE outputs a low level; when the voltage of the - terminal of the second operational amplifier U3 is less than VCC*(R4||R7) / (R3+R4||R7), the output terminal DUTY_CYCLE outputs a high level.

[0064] It should be noted that, as shown in Figure 4 if the channels of the analog switch U1 in the voltage switching circuit 20 are switched, then the + terminal and the - terminal in the comparison circuit 40 also need to be switched, i.e. the first input terminal is the + terminal and the second input terminal is the - terminal.

[0065] In another possible implementation manner, the above Figure 2The second operational amplifier U3 shown is replaced by a comparator, the response speed of the comparator output is faster than that of the operational amplifier, the edge switching time is shorter, and the time error of the current sampling circuit caused by the edge change is smaller.

[0066] As shown in Figure 5 The comparison circuit 40 includes a comparator U8, a fourth resistor R4, a fifth resistor R7, a sixth resistor R3, and a seventh resistor R13. The first input terminal of the comparator U8 is connected to the integration circuit, the second input terminal of the comparator U8 is connected to the output terminal of the comparator U8 through the fourth resistor R4, the second input terminal of the comparator U8 is grounded through the fifth resistor R7, and is also connected to the power supply end VCC provided by the current receiving circuit through the sixth resistor R3, and the output terminal of the comparator U8 is connected to the power supply end VCC provided by the current receiving circuit through the seventh resistor R13.

[0067] The output terminal of the comparator U8 uses the seventh resistor R13 as a pull-up resistor to provide a high-level output.

[0068] In a possible implementation, as shown in Figure 2 The reference voltage circuit 50 includes a bias voltage circuit 501 and a negative constant voltage circuit 502.

[0069] The bias voltage provided by the bias voltage circuit 501 is input to the negative constant voltage circuit 502 through the bias voltage end Vref, and the negative constant voltage provided by the negative constant voltage circuit 502 is input to the first input channel B1 of the voltage switching circuit through the negative constant voltage end Vi-.

[0070] For the composition of the bias voltage circuit, in one example, as shown in Figure 2 The bias voltage circuit 501 includes a first voltage follower U5, an eighth resistor R8, and a ninth resistor R5. The first voltage follower U5 outputs the bias voltage, the input terminal (i.e., the + terminal) of the first voltage follower U5 is grounded through the eighth resistor R8, and is also connected to the power supply end VCC provided by the current receiving circuit through the ninth resistor R5. Since the bias voltage is composed of resistors that are in a proportional relationship with the power supply voltage, the fluctuation of the power supply voltage does not affect the proportion among the voltages.

[0071] The power supply end VCC is divided by the eighth resistor R8 and the ninth resistor R5 in series, and then the bias voltage is output by the first voltage follower U5, which can stabilize the voltage output and improve the load capacity.

[0072] In another example, a reference voltage chip can also be used to directly provide the bias voltage for the circuit, the circuit structure is simple and easy to implement, and the number of voltage dividing resistors can be reduced. As shown in Figure 6As shown, the bias voltage circuit 501 comprises a first reference source U9, an input end IN of the first reference source U9 is connected to the power supply end VCC provided by the current receiving circuit, an output end OUT of the first reference source U9 serves as the bias voltage end Vref, and the output end OUT of the first reference source U9 is grounded through a second capacitor C5.

[0073] In yet another example, the bias voltage circuit can also provide the bias voltage with the same reference power supply as the negative constant voltage circuit, so as to reduce the voltage dividing resistor. As shown in FIG. 4, the bias voltage circuit 401 comprises a first voltage follower U5 and an eleventh resistor R14. An input end of the first voltage follower U5 is connected to the power supply end VCC provided by the current receiving circuit through the eleventh resistor R14, and the input end of the first voltage follower U5 is also connected to a second reference source U4 in the negative constant voltage circuit. An output end of the first voltage follower U5 serves as the bias voltage end Vref. Figure 7

[0074] In a possible implementation, as shown in FIG. 4, the bias voltage circuit 401 comprises a first voltage follower U5 and an eleventh resistor R14. An input end of the first voltage follower U5 is connected to the power supply end VCC provided by the current receiving circuit through the eleventh resistor R14, and the input end of the first voltage follower U5 is also connected to a second reference source U4 in the negative constant voltage circuit. An output end of the first voltage follower U5 serves as the bias voltage end Vref. Figure 2 As shown in FIG. 4, the negative constant voltage circuit comprises a second voltage follower U6 and the second reference source U4. The second voltage follower U6 outputs a negative constant voltage Vi-. An input end (+ end) of the second voltage follower U6 is connected to the second reference source U4 through voltage dividing resistors R6 and R9 connected in parallel. Two ends of the second reference source U4 are connected to a tenth resistor R10 and the bias voltage end Vref in series, respectively, and an initial negative voltage is provided by the second reference source U4. A far end of the tenth resistor R10 is grounded.

[0075] wherein the negative reference voltage = -Vu4*R9 / (R6+R9). Since the negative reference voltage is formed by voltage dividing the power supply voltage with the resistor pair, the fluctuation of the power supply voltage does not affect the proportion among the voltages.

[0076] The following takes the current transmission circuit structure shown in FIG. 4 as an example to introduce the overall flow of current transmission. Figure 2 As shown in FIG. 4, the current transmission circuit structure comprises a current receiving circuit 10, a bias voltage circuit 401, a negative constant voltage circuit 402, a voltage switching circuit 20, an integral circuit 30, a comparison circuit 40, and a current output circuit 50.

[0077] In the initial state, the output end of the integral circuit 30 is in a floating state without voltage. Since the voltage at the - end of the comparison circuit 40 is less than the voltage at the + end, the output end DUTY_CYCLE of the comparison circuit outputs a high level, so that the second channel of the analog switch U1 in the voltage switching circuit 20 is turned on.

[0078] When the current input end AI1+ has a current i + ​When entering, the first resistor R2 generates a voltage Vi+ which is input to the second channel input terminal B2, so that the output terminal A of the analog switch U1 outputs the voltage Vi+ generated by the first resistor R2. At this time, the voltage of the third resistor R1 in the integration circuit 30 is greater than the voltage of the + terminal of the first operational amplifier U2 (bias voltage), and the voltage difference is i*R2. The first capacitor C1 starts to charge, so that the voltage of the output terminal of the first operational amplifier U2 rises. When the voltage of the output terminal of the first operational amplifier U2 is greater than VCC*R7 / (R3||R4+R7), the second operational amplifier U3 outputs a low level. At this time, the analog switch U1 switches the channel, and the first channel is turned on, so that the output terminal A of the analog switch U1 outputs a negative reference voltage, so that the voltage of the third resistor R1 is less than the voltage of the + terminal of the first operational amplifier U2 (bias voltage), and the first capacitor C1 starts to discharge, so that the voltage of the output terminal of the first operational amplifier U2 decreases. When the voltage of the output terminal of the first operational amplifier U2 is less than VCC*(R4||R7) / (R3+R4||R7), the second operational amplifier U3 outputs a high level again, so that the second channel of the analog switch U1 in the voltage switching circuit 20 is turned on, so that the output terminal A of the analog switch U1 outputs the voltage Vi+ generated by the first resistor R2, and the above process is repeated continuously.

[0079] Based on the above process, the third resistor R1 and the first capacitor C1 in the integration circuit 30 are constant values. According to the principle of charge quantity Q=i*t=C*U, it can be deduced that t=C*U / i.

[0080] Wherein, U=the voltage difference of the flip Umax-Umin, the charging voltage of the first capacitor C1 is U + (that is, the voltage provided by the input current), and the discharging voltage of the first capacitor C1 is U - (that is, the negative constant voltage provided by the reference voltage circuit), so that the charging time Δt1=C1*(Umax-Umin) / (U + / R1), and the discharging time Δt2=C1*(Umax-Umin) / (U - / R1); since the high level output time of the output terminal of the comparison circuit can be represented by the charging time Δt1, and the low level output time of the output terminal can be represented by the discharging time Δt2, the output duty cycle of the comparison circuit is Δt1 / (Δt1+Δt2).

[0081] Further, U + =i + *R2, U - =i - *R2, and the two formulas of U + and U - are substituted into the duty cycle formula, which can be deduced as

[0082] In the above formula, i _is a constant current, i _ The negative constant voltage U - is obtained by the first resistance R2, i + is the input current of the current receiving circuit.

[0083] It should be noted that the present application utilizes the characteristics of the integration circuit 30, during the charging period, the comparison circuit 40 outputs high level, during the discharging period, the comparison circuit 40 outputs low level, therefore the charging and discharging time duty cycle of the first capacitor C1 determines the duty cycle of the high and low level output by the comparison circuit 40, therefore according to the ratio between the charging voltage and the discharging voltage of the first capacitor C1, the input current of the current input end can be converted.

[0084] Based on the above description, by converting the charging and discharging time of the capacitor into duty cycle, the temperature drift of the capacitor is avoided to affect the measurement accuracy, and the cycle automatic switching of the charging and discharging circuit is realized.

[0085] Figure 8 is an embodiment flow chart of the input current determination method of the current receiving circuit according to an exemplary embodiment of the present application, based on the above Figures 1 to 7 Based on the current receiving circuit shown in the above Figure 8 , the output end of the comparison circuit in the current receiving circuit is connected to the single-chip microcomputer as the execution main body, the input current of the current receiving circuit is detected, and the input current determination method includes the following steps:

[0086] Step 801: obtaining the high level output time of the output end of the comparison circuit, and obtaining the low level output time of the output end of the comparison circuit.

[0087] The high level output time is Δt1 in the above embodiment, and the low level output time is Δt2.

[0088] Step 802: determining the output duty cycle of the current receiving circuit by using the high level output time and the low level output time.

[0089] The calculation formula of the duty cycle a is as follows:

[0090]

[0091] Step 803: determining the input current according to the duty cycle.

[0092] The calculation formula of the input current i + is as follows:

[0093]

[0094] The duty cycle a and the negative constant voltage U- , the first resistance R2 are all known parameters.

[0095] From the above embodiment description, the duty cycle of the capacitor charging and discharging time is constituted by the high and low level time output by the comparison circuit, and the input current of the current receiving circuit is directly converted according to the duty cycle, without considering any parameter characteristics of the optocoupler. Therefore, the temperature drift coefficient and the linearity of the optocoupler do not affect the current transmission accuracy of the circuit, so that the circuit does not need to be calibrated before leaving the factory, and the production capacity of batch production can be improved.

[0096] The above only describes the preferred embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation, direct / indirect application in other related technical fields, or direct / indirect application in other related technical fields within the concept of the present application, using the contents of the present application specification and drawings, are included in the patent protection scope of the present application.

Claims

1. A current receiving circuit, characterized in that, It includes a current sampling circuit, a voltage switching circuit, an integrating circuit, a comparator circuit, and a reference voltage circuit; The current sampling circuit, voltage switching circuit, integration circuit, and comparison circuit are connected in series, and the output of the comparison circuit is fed back to the voltage switching circuit. The reference voltage circuit provides a bias voltage terminal and a negative fixed voltage terminal. The bias voltage terminal is connected to the current sampling circuit and the integration circuit, respectively, and the negative fixed voltage terminal is connected to the voltage switching circuit. The current sampling circuit includes a current input terminal, a voltage output terminal, a transient diode, a first diode, a second diode, and a first resistor; The current input terminal is connected to one end of the transient diode, the positive terminal of the first diode, the negative terminal of the second diode, one end of the first resistor, and the voltage output terminal via a fuse wire. The other end of the transient diode, the negative terminal of the first diode, the positive terminal of the second diode, and the other end of the first resistor are all connected to the bias voltage terminal; The comparator circuit includes a second operational amplifier, a fourth resistor, a fifth resistor, and a sixth resistor; the first input terminal of the second operational amplifier is connected to the integrating circuit; the second input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier through the fourth resistor; the second input terminal of the second operational amplifier is also grounded through the fifth resistor, and connected to the power supply provided by the current receiving circuit through the sixth resistor; or, The comparator circuit includes a comparator, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; the first input terminal of the comparator is connected to the integrator circuit; the second input terminal of the comparator is connected to the output terminal of the comparator through the fourth resistor; the second input terminal of the comparator is grounded through the fifth resistor and is also connected to the power supply terminal provided by the current receiving circuit through the sixth resistor; the output terminal of the comparator is connected to the power supply terminal provided by the current receiving circuit through the seventh resistor.

2. The current receiving circuit as described in claim 1, characterized in that, The voltage switching circuit includes an analog switch; The first channel input terminal of the analog switch is connected to the negative fixed voltage terminal; The second channel input terminal of the analog switch is connected to the voltage output terminal of the current sampling circuit; The control terminal of the analog switch is connected to the output terminal of the comparator circuit; The output of the analog switch is connected to the integrating circuit.

3. The current receiving circuit as described in claim 1, characterized in that, The voltage switching circuit includes a controlled switch and a second resistor; The control terminal of the controlled switch is connected to the output terminal of the comparator circuit; The output terminal of the controlled switch is connected to one end of the second resistor; The other end of the second resistor is connected to the integrating circuit.

4. The current receiving circuit as described in claim 1, characterized in that, The integrating circuit includes a first operational amplifier, a third resistor, and a first capacitor; The first input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier through the first capacitor; The first input terminal of the first operational amplifier is also connected to the voltage switching circuit through the third resistor; The second input terminal of the first operational amplifier is connected to the bias voltage terminal.

5. The current receiving circuit as described in claim 1, characterized in that, The reference voltage circuit includes a bias voltage circuit and a negative fixed voltage circuit; The bias voltage provided by the bias voltage circuit is input to the negative fixed voltage circuit through the bias voltage terminal; The negative set voltage provided by the negative set voltage circuit is input to the voltage switching circuit through the negative set voltage terminal.

6. The current receiving circuit as described in claim 5, characterized in that, The bias voltage circuit includes a first voltage follower, an eighth resistor, and a ninth resistor; the first voltage follower outputs the bias voltage; the input terminal of the first voltage follower is grounded through the eighth resistor, and is also connected to the power supply terminal provided by the current receiving circuit through the ninth resistor; or, The bias voltage circuit includes a first reference source; the input terminal of the first reference source is connected to the power supply terminal provided by the current receiving circuit; the output terminal of the first reference source serves as the bias voltage terminal, and the output terminal of the first reference source is grounded through a second capacitor.

7. The current receiving circuit as described in claim 5, characterized in that, The negative fixed voltage circuit includes a second voltage follower and a second reference source; The second voltage follower outputs the negative fixed voltage; The input of the second voltage follower is connected to the second reference source through a voltage divider resistor connected in parallel; The two ends of the second reference source are connected in series with the tenth resistor and the bias voltage terminal to provide an initial negative voltage, and the end of the tenth resistor away from the second reference source is grounded.

8. A method for determining the input current of a current receiving circuit as described in any one of claims 1 to 7, characterized in that, The method includes: Obtain the high-level output time of the comparator circuit and the low-level output time of the comparator circuit. The output duty cycle of the current receiving circuit is determined using the high-level output time and the low-level output time. The input current is determined based on the duty cycle.

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