interface circuit
By introducing a combinational logic circuit of control and enable signals into the interface circuit, the problem of unstable output signals caused by process fluctuations is solved, ensuring that the interface circuit can transmit signals correctly under abnormal conditions and improving the reliability of the interface circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2022-05-09
- Publication Date
- 2026-06-23
AI Technical Summary
Existing interface circuits may fail to properly identify output signals due to process fluctuations, leading to functional failure.
By introducing a first transistor, a second transistor, a first switch, a first logic circuit, and a second logic circuit into the interface circuit, and utilizing a combination of control signals and enable signals, the output signal can be transmitted correctly under both normal and abnormal conditions.
It achieves stability and reliability of output signals under process fluctuations, ensuring that external electronic devices can correctly identify the output signals of the interface circuit.
Smart Images
Figure CN116436454B_ABST
Abstract
Description
Technical Field
[0001] This invention generally relates to an interface circuit, and more specifically, to an interface circuit with a weak pull-up structure. Background Technology
[0002] Please refer to Figure 1A , Figure 1A This is a circuit diagram of an interface circuit in the prior art. Interface circuit 100 includes transistor MP1 and transistor MN1. Transistor MP1 and transistor MN1 are connected in series between a power supply terminal and a reference ground terminal, and are controlled by control signals CT1 and CT2, respectively. The power supply terminal provides a power supply voltage VDD, and the reference ground terminal provides a reference ground voltage VSS. The output terminal of interface circuit 100 is coupled to pad PD, and a capacitor load is coupled between pad PD and the reference ground terminal. Transistor MP1 has a weaker driving capability than transistor MN1. When both transistors MP1 and MN2 are turned on according to control signals CT1 and CT2, interface circuit 100 generates an output signal ALTN with a low voltage.
[0003] Please refer to Figure 1B and Figure 1C , Figure 1B and Figure 1C yes Figure 1A Waveforms of the interface circuit under different operating conditions. Under normal conditions, refer to... Figure 1B During time period T1, the output signal ALTN can be pulled down from the supply voltage VDD with amplitude H1 during time period T2, and remains at the reference ground voltage VSS during time period T3. After time period T3, the output signal ALTN can be pulled up towards the supply voltage VDD during time period T4. In application specifications, the lengths of time periods T1 to T4 are defined. Generally, the total length of time periods T2 to T4 cannot exceed the length of time period T1.
[0004] Under abnormal conditions, refer to Figure 1C The driving capability of at least one of transistors MP1 and MN1 is variable. In this case, due to process variations, the driving capability of transistor MP1 may be stronger, or the driving capability of transistor MN1 may be weaker, or both transistor MP1 and MN1 may have stronger and weaker driving capabilities. The pulled-down amplitude is less than the amplitude H1, and during time period T2, the output signal ALTN cannot be pulled to the reference ground voltage VSS. As a result, time period T3 is missed. Therefore, the output signal ALTN cannot be recognized by external electronic devices, and the interface circuit 100 fails to function. Summary of the Invention
[0005] The present invention provides an interface circuit that can overcome process fluctuations and provide correct output signals.
[0006] The interface circuit includes a first transistor, a second transistor, a first switch, a first logic circuit, and a second logic circuit. The first transistor receives a power supply voltage at its first terminal and is controlled by an enable signal. The second transistor is coupled between the output terminal of the interface circuit and a reference ground terminal and is controlled by a first control signal. The first switch is coupled between the second terminal of the first transistor and the output terminal of the interface circuit, wherein the first switch is controlled by a second control signal. The first logic circuit is coupled to the second transistor and generates a first control signal based on the enable signal and at least one indication signal. The second logic circuit is coupled to the first logic circuit and the first switch, wherein the second logic circuit generates a second control signal based on the first control signal and the enable signal.
[0007] Therefore, when the second transistor is turned on, the interface circuit provides a first switch to disconnect the connection path between the first transistor and the output of the interface circuit. In this way, when the interface circuit generates a low-voltage output signal, the second transistor does not need to interfere with the first transistor. The waveform of the output signal is unaffected by process variations, and the interface circuit can provide an output signal of good quality.
[0008] It should be understood that the general description above and the detailed description below are exemplary and intended to provide further explanation of the invention claimed in the claims. Attached Figure Description
[0009] This specification includes accompanying drawings to provide a further understanding of the invention, and the drawings are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with this description, serve to explain the principles of the invention.
[0010] Figure 1A This is a circuit diagram of an interface circuit in the prior art;
[0011] Figure 1B and Figure 1C yes Figure 1A Waveforms of the interface circuit under different operating conditions;
[0012] Figure 2 A schematic diagram of an interface circuit according to an embodiment of the present disclosure is shown;
[0013] Figure 3 This disclosure shows Figure 2 Waveform diagram of interface circuit 200 shown;
[0014] Figure 4A and Figure 4B These are schematic diagrams of interface circuits according to different embodiments of the present disclosure;
[0015] Figure 5A and Figure 5B These are schematic diagrams of interface circuits according to different embodiments of the present disclosure;
[0016] Figure 6A and Figure 6B This is a schematic diagram of an interface circuit according to different embodiments of the present disclosure.
[0017] Explanation of icon numbers
[0018] 100, 200, 401, 402, 501, 502, 601, 602: Interface circuits
[0019] 210, 410, 440, 510, 540, 610, 640: Switches
[0020] 220, 230, 420, 430, 520, 530, 620, 630: Logic circuits
[0021] 450, 550, 650: Electrostatic Discharge (ESD) Protection Circuit
[0022] 460: External Circuit
[0023] A1, AM: Indicator signals
[0024] AD1: AND gate / AND logic gate
[0025] AD2: AND logic gate
[0026] ALTN: Output signal
[0027] CL: Load capacitor
[0028] CT1, CT2, CTA, CTB: Control Signals
[0029] EN: Enable signal
[0030] ENB: Reverse Enable Signal
[0031] H1: Amplitude
[0032] IV1: Inverter
[0033] MN1, MN2, MP1, MP2: Transistors
[0034] MUX1: Multiplexer
[0035] OA1: Calculation result
[0036] OR1, OR2: OR logic gates
[0037] PD: solder pads
[0038] RN1, RP1: Resistors
[0039] SW1: Output switch
[0040] T1, T2, T3, T4: Time Periods
[0041] tA: Time point
[0042] Td1, Td2: Delay time
[0043] VDD: Power supply voltage
[0044] VSS: Reference ground voltage Detailed Implementation
[0045] Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. The same reference numerals are used wherever possible in the drawings and description to refer to the same or similar parts.
[0046] Please refer to Figure 2 , Figure 2 A schematic diagram of an interface circuit according to an embodiment of the present disclosure is shown. Interface circuit 200 includes transistors MP1 and MN1, a switch 210, and logic circuits 220 and 230. A first terminal of transistor MP1 is coupled to a power supply terminal to receive a power supply voltage VDD, a second terminal of transistor MP1 is coupled to switch 210, and a control terminal of transistor MP1 receives an inverting enable signal ENB. Switch 210 is formed by transistor MP2. Transistor MP2 is coupled between transistor MP1 and the output terminal of interface circuit 200, and a control terminal of transistor MP2 is coupled to logic circuit 220 to receive a control signal CTB. Transistor MN1 is coupled between the output terminal of interface circuit 200 and a reference ground terminal. The reference ground terminal is used to provide a reference ground voltage VSS. The control terminal of transistor MN1 is coupled to logic circuit 230 to receive a control signal CTA. In this embodiment, both transistors MP1 and MP2 are P-type transistors, and transistor MN1 is an N-type transistor. Transistor MP1 has a weaker driving capability than transistor MN1. In this embodiment, since transistor MP1 is used in TTL logic, transistor MP1 can have a weaker drive capability. For example, the channel of transistor MP1 can have a small width-to-length ratio, or transistor MP1 can have fewer fingers than transistor MN1.
[0047] In this embodiment, the inverted enable signal ENB is generated by inverter IV1. Inverter IV1 receives the enable signal EN and generates and transmits the inverted enable signal to the control terminal of transistor MP1. The enable signal EN is used to indicate whether the interface circuit 200 is in input mode or output mode. Here, when the enable signal EN is at logic 1, the interface circuit 200 is in output mode, and when the enable signal EN is at logic 0, the interface circuit 200 is in input mode.
[0048] The logic circuit 230 includes an OR gate OR1 and an AND gate AD2. The OR gate OR1 may have multiple inputs to receive multiple indication signals A1 to AM, and the OR gate OR1 generates an operation result OA1 by performing a logical OR operation on the indication signals A1 to AM. The AND gate AD2 receives the operation result OA1 and an enable signal EN, and generates a control signal CTA by performing an AND logic operation on the operation result OA1 and the enable signal EN.
[0049] Logic circuit 220 is used to perform an AND logic operation on the enable signal EN and the control signal CTA. In this embodiment, logic circuit 220 includes an AND gate AD1. The AND gate AD1 receives the enable signal EN and the control signal CTA, and generates a control signal CTB based on the enable signal EN and the control signal CTA.
[0050] Regarding the detailed operation of interface circuit 200, when interface circuit 200 is in output mode, the enable signal is set to logic 1, and transistor MP1 is turned on. At this time, if at least one of the indicator signals A1 to AM is at logic 1, AND gate AD1 can generate a control signal CTA that is also at logic 1. Therefore, transistor MN1 can be turned on.
[0051] It should be noted here that since the control signal CTA is at logic 1, logic circuit 220 can generate a control signal CTB of logic 1. This causes switch 210 to open, and the connection path between transistor MP1 and the output of interface circuit 200 is correspondingly broken. This allows the output signal ALTN to be successfully pulled to the reference ground voltage VSS by transistor MN1 without conflicting with transistor MP1. Because transistor MN1 pulls down the output signal ALTN without conflicting with transistor MP1, fluctuations in the driving capabilities of transistors MP1 and MN1 have little impact on the output signal ALTN.
[0052] Please refer to this together. Figure 3 and Figure 2 ,in Figure 3 This disclosure shows Figure 2The waveform diagram of interface circuit 200 is shown. During time period T1, at time point tA, logic circuit 230 can set the enable signal EN to logic 1 and pull up the control signal CTA to logic 1. After a delay time Td1, logic circuit 220 pulls up the control signal CTB to logic 1. The delay time Td1 can be the gate delay of AND gate AD1 in logic circuit 220. When the control signal CTB is pulled up to logic 1, switch 210 is turned off, and the output signal ALTN is pulled down by the conducting transistor MN1 during time period T2. Since transistor MN1 does not need to conflict with transistor MP1, the output signal ALTN can be successfully pulled up to the reference ground voltage VSS during time period T2. The output signal ALTN can remain at the reference ground voltage VSS until time period T3.
[0053] Furthermore, after all indicator signals A1 to AM have returned to logic 0, logic circuit 230 can set control signal CTA to logic 0. Transistor MN1 can be turned off according to the control signal CTA being logic 0. After a delay time Td2, logic circuit 220 can set control signal CTB to logic 0. When control signal CTB is at logic 0, switch 210 can be turned on, and output signal ALTN can be pulled up towards the power supply voltage VDD during time period T4.
[0054] Please refer to this again. Figure 2 The output of interface circuit 200 can be coupled to the pad PD of the integrated circuit. The load capacitor CL can be coupled between the pad PD and the reference ground.
[0055] In this embodiment, the indicator signals A1 to AM can be alarm signals for the integrated circuit. According to this embodiment, the interface circuit 200 can provide an output signal ALTN with a correct definition. In this way, external electronic circuitry coupled to the pad PD can successfully identify the output signal ALTN.
[0056] Please refer to Figure 4A and Figure 4B , Figure 4A and Figure 4B These are schematic diagrams of interface circuits according to different embodiments of this disclosure. Figure 4A In the interface circuit 401, transistors MP1 and MN1, switches 410 and 440, logic circuits 420 and 430, and electrostatic discharge (ESD) protection circuit 450 are included. This differs from... Figure 2The interface circuit 200 and interface circuit 401 further include a switch 440. Switch 440 is coupled between the output of interface circuit 401 and transistor MN1. Switch 440 is controlled to be on or off by a control signal CTB. Switch 440 is formed by transistor MN2, wherein transistor MN2 has the same conductivity type as transistor MN1. In this embodiment, both transistor MN1 and transistor MN2 are N-type transistors.
[0057] On the other hand, since transistors MN2 and MP2 in switch 410 have different conductivity types and are controlled by the same control signal CTB, their on / off states are different. In output mode, transistor MP2 can be turned off according to the control signal CTB, and transistor MN2 can be turned on according to the control signal CTB.
[0058] ESD protection circuit 450 is coupled to pad PD, which is coupled to the output of interface circuit 401. ESD protection circuit 450 can be implemented using any ESD protection circuit structure known to those skilled in the art. Furthermore, in this embodiment, switches 410 and 440 can be arranged adjacent to pad PD, and transistors MP2 and MN2 can be auxiliary ESD protection circuits. This simplifies the circuit structure of ESD protection circuit 450, thereby reducing the circuit size of interface circuit 401.
[0059] In this embodiment, the interface circuit 401 further includes an output switch SW1 coupled between the pad PD and the external circuit 460. The output switch SW1 can be controlled by an enable signal EN, and if the enable signal EN indicates that the interface circuit 401 is in output mode, the output switch SW1 can be turned off. Conversely, if the enable signal EN indicates that the interface circuit 401 is in input mode, the output switch SW1 can be turned on. In output mode, the enable signal EN can be at logic 1, and in input mode, the enable signal EN can be at logic 0. It should be noted that in input mode, transistors MP1, MP2, MN2, and MN1 can be turned off according to the enable signal EN. The pad PD can be in a floating state.
[0060] The detailed operation of interface circuit 401 is similar to that of interface circuit 200, and will not be repeated here.
[0061] exist Figure 4B In the interface circuit 402, transistors MP1 and MN1, switches 410 and 440, logic circuits 420 and 430, resistors RP1 and RN1, and ESD protection circuit 450 are included. Figure 4AUnlike interface circuit 401, interface circuit 402 also includes resistors RP1 and RN1. Resistor RP1 is coupled between the output terminal of interface circuit 402 and switch 410. Resistor RN1 is coupled between the output terminal of interface circuit 402 and switch 440. Resistors RP1 and RN1 are used to enhance the ESD protection capability of interface circuit 402. In this embodiment, the circuit structure of ESD protection circuit 450 can be further simplified to save the circuit size of interface circuit 402.
[0062] Please refer to Figure 5A and Figure 5B , Figure 5A and Figure 5B These are schematic diagrams of interface circuits according to different embodiments of this disclosure. Figure 5A In the interface circuit 501, transistors MP1 and MN1, switches 510 and 540, logic circuits 520 and 530, and electrostatic discharge (ESD) protection circuit 550 are included. Figure 4A Compared to the interface circuit 401 in the middle, Figure 5AThe logic circuit 520 is formed by a multiplexer MUX1. Multiplexer MUX1 receives an enable signal EN, an inverted enable signal ENB, and a control signal CTA. The control signal CTA is generated by logic circuit 530, and the inverted enable signal ENB is generated by inverter IV1. Multiplexer MUX1 selects either the enable signal EN or the inverted enable signal ENB as the control signal CTB based on the control signal CTA. Specifically, if the control signal CTA is at logic 0, multiplexer MUX1 selects the inverted enable signal ENB as the control signal CTB; and if the control signal CTA is at logic 1, multiplexer MUX1 selects the enable signal EN as the control signal CTB. When interface circuit 501 is in output mode, the enable signal EN can be at logic 1, and when the control signal CTA is at logic 1, multiplexer MUX1 can generate a logic 1 control signal CTB. In this way, switch 510 can be opened. At this time, both the control signal CTB and the inverted enable signal ENB can be equal to logic 0. Transistors MP1 and MP2 can be turned on simultaneously, and transistors MN1 and MN2 can be turned off simultaneously. The signal on pad PD can be weakly pulled high, and a logic 1 is output accordingly. This is the triggering behavior of an alarm event in output mode when the control signal CTA is at logic 1. An alarm event can pull the signal on the pad to logic 0 to notify an external device. In addition, when the interface circuit 501 is in input mode, the enable signal EN is at logic 0, and the inverted enable signal ENB can be at logic 1. Logic circuit 530 can generate a control signal CTA at logic 0, and multiplexer MUX1 can generate a control signal CTB at logic 1 based on the control signal CTA. In addition, switch 510 can be turned off as a result. That is to say, multiplexer MUX1 can perform the same function as AND gate AD1 in logic circuit 420.
[0063] The detailed operation of interface circuit 501 is the same as that of interface circuit 401, and will not be repeated here.
[0064] exist Figure 5B In the interface circuit 502, transistors MP1 and MN1, switches 510 and 540, logic circuits 520 and 530, resistors RP1 and RN1, and ESD protection circuit 550 are included. Figure 5AUnlike interface circuit 501, interface circuit 502 also includes resistors RP1 and RN1. Resistor RP1 is coupled between the output terminal of interface circuit 501 and switch 510. Resistor RN1 is coupled between the output terminal of interface circuit 501 and switch 540. Resistors RP1 and RN1 are used to enhance the ESD protection capability of interface circuit 502. In this embodiment, the circuit structure of ESD protection circuit 550 can be further simplified to save the circuit size of interface circuit 502.
[0065] Please refer to Figure 6A and Figure 6B , Figure 6A and Figure 6B This is a schematic diagram of an interface circuit according to different embodiments of the present disclosure. Figure 6A In the interface circuit 601, transistors MP1 and MN1, switches 610 and 640, logic circuits 620 and 630, and electrostatic discharge (ESD) protection circuit 650 are included. Figure 5A Compared to the interface circuit 501 in the middle, Figure 6A The logic circuit 620 is formed by an OR gate OR2. OR gate OR2 receives the inverted enable signal ENB and the control signal CTA. The control signal CTA is generated by logic circuit 630, and the inverted enable signal ENB is generated by inverter IV1. OR gate OR2 performs an OR operation on the inverted enable signal ENB and the control signal CTA to generate the control signal CTB. Specifically, if interface circuit 601 is in output mode, the inverted enable signal is at logic 0. At this time, both control signals CTA and CTB can be equal to logic 0, transistors MP1 and MP2 can be turned on simultaneously, and transistors MN1 and MN2 can be turned off simultaneously. The signal on pad PD can be weakly pulled high, correspondingly outputting logic 1. When the control signal CTA is at logic 1, OR gate OR2 generates a logic 1 control signal CTB to disconnect switch 610. This is the triggering behavior for an alarm event in output mode when the control signal CTA is at logic 1. An alarm event can pull the signal on the pad to logic 0 to notify external devices. Furthermore, if interface circuit 601 is in input mode, the inverted enable signal ENB is at logic 1, and OR gate OR2 can generate a control signal CTB at logic 1 based on the inverted enable signal ENB to disconnect switch 610. That is, OR gate OR2 can perform the same function as multiplexer MUX1 in logic circuit 520.
[0066] The detailed operation of interface circuit 601 is the same as that of interface circuit 401, and will not be repeated here.
[0067] exist Figure 6BIn the interface circuit 602, transistors MP1 and MN1, switches 610 and 640, logic circuits 620 and 630, resistors RP1 and RN1, and ESD protection circuit 550 are included. Figure 6A Unlike interface circuit 601, interface circuit 602 also includes resistors RP1 and RN1. Resistor RP1 is coupled between the output of interface circuit 601 and switch 610. Resistor RN1 is coupled between the output of interface circuit 601 and switch 640. Resistors RP1 and RN1 are used to enhance the ESD protection capability of interface circuit 602. In this embodiment, the circuit structure of ESD protection circuit 650 can be further simplified to save the circuit size of interface circuit 602.
[0068] In summary, the interface circuit of this disclosure provides a switch coupled between the output terminal of the interface circuit and a first transistor, wherein the first transistor is used to pull up the output signal at the output terminal. When the interface circuit is in output mode and the interface circuit needs to generate an output signal with a low voltage level, a second transistor for pulling down the output signal is turned on, and the switch is therefore turned off. In this way, the second transistor does not conflict with the first transistor, and the output signal can be successfully pulled down. On the other hand, in output mode, during normal operation, the second transistor is turned off and the first transistor is turned on to weakly pull up the signal on the pad. During an alarm event, the first transistor can be turned off and the second transistor is turned on to pull down the signal on the pad. By alternately pulling up and pulling down the signal on the pad, an alarm signal with pulses transitioning between logic 1 and logic 0 can be transmitted to an external device. Since the first transistor and the output terminal can be isolated by the switch in output mode, the impact of process variations on the output signal can be minimized. The output signal can be identified by external circuitry, and the performance of the interface circuit can be enhanced.
[0069] It will be apparent to those skilled in the art that various modifications and alterations can be made to the structure of the present invention without departing from its scope or spirit. In view of the foregoing, the present invention is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.
Claims
1. An interface circuit, comprising: A first transistor, wherein a first terminal of the first transistor receives a power supply voltage, and the first transistor is controlled by an enable signal; The second transistor is coupled between the output terminal of the interface circuit and the reference ground terminal, and is controlled by the first control signal; A first switch is coupled between the second terminal of the first transistor and the output terminal of the interface circuit, wherein the first switch is controlled by a second control signal; A first logic circuit, coupled to the second transistor, generates the first control signal according to the enable signal and at least one indication signal; as well as A second logic circuit is coupled to the first logic circuit and the first switch, wherein the second logic circuit generates the second control signal based on the first control signal and the enable signal. When the first transistor is turned on according to the enable signal, the second transistor is turned on according to the first control signal, and the first switch is turned off according to the second control signal.
2. The interface circuit according to claim 1, wherein the driving capability of the first transistor is weaker than that of the second transistor.
3. The interface circuit according to claim 1 further includes: The inverter has an input for receiving the enable signal and an output coupled to the control terminal of the first transistor.
4. The interface circuit according to claim 1, wherein the second logic circuit performs an AND logic operation on the enable signal and the first control signal.
5. The interface circuit according to claim 1, wherein the first logic circuit comprises: An OR gate performs an OR logic operation on the at least one indication signal to produce a result. as well as An AND gate is used to perform an AND logic operation on the computation result and the enable signal to generate the first control signal.
6. The interface circuit according to claim 1 further includes: A second switch is coupled between the output terminal of the interface circuit and the second transistor, wherein the second switch is controlled by the second control signal.
7. The interface circuit of claim 6, wherein the first switch is formed by a third transistor and the second switch is formed by a fourth transistor, and the first transistor has the same conductivity type as the third transistor, the second transistor has the same conductivity type as the fourth transistor, and the first transistor has a different conductivity type from the second transistor.
8. The interface circuit according to claim 6 further includes: A first resistor is connected in series between the output terminal of the interface circuit and the first switch; as well as The second resistor is connected in series between the output terminal of the interface circuit and the second switch.
9. The interface circuit according to claim 1, wherein the second logic circuit is a multiplexer, wherein the multiplexer selects one of the enable signal and the reverse enable signal as the second control signal according to the first control signal.
10. The interface circuit according to claim 1, wherein the second logic circuit performs an OR logic operation on the inverted enable signal and the first control signal.
11. The interface circuit according to claim 1, wherein the output terminal of the interface circuit is coupled to the pads of the integrated circuit.
12. The interface circuit according to claim 11, further comprising: An electrostatic discharge protection circuit is coupled to the pad.
13. The interface circuit according to claim 1, wherein the interface circuit is in input mode when the first transistor is off, and in output mode when the first transistor is on.
14. The interface circuit according to claim 1, further comprising: An output switch is coupled between the output terminal of the interface circuit and an external circuit, and is controlled by the enable signal.