Power measurement chip for low-voltage power distribution networks

Abstract

This application relates to the field of chip technology, providing a power measurement chip for low-voltage distribution networks. The chip includes: an analog sampling module, a sampling distribution module, a power measurement module, and a control module. The analog sampling module includes multiple analog-to-digital converters for acquiring three-phase AC voltage analog signals, three-phase AC current analog signals, and neutral line AC current analog signals, respectively, and outputting digital sampling signal groups. The sampling distribution module samples the digital sampling signal groups output by the analog sampling module, outputting multiple signal groups with different update rates, wherein the sampling rate of the first signal group is synchronized with the AC voltage frequency of the power grid. The power measurement module includes a power quality module, which calculates power quality data based on the first signal group output by the sampling distribution module. This chip can achieve sampling rate synchronization with the AC voltage frequency of the power grid, accurately calculate various power quality data, and is suitable for low-voltage distribution networks.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more specifically to an energy measurement chip for low-voltage power distribution networks. Background Technology

[0002] In the construction of the distribution Internet of Things (IoT), intelligent fusion terminals need to be installed on the outgoing side of low-voltage distribution transformers. The outgoing side of low-voltage distribution transformers is generally a 3-phase 4-wire system (three-phase lines A / B / C and neutral line N), including A / B / C phase voltage, A / B / C phase current, and N phase current. The intelligent fusion terminal is mainly used to collect the A / B / C phase AC voltage signals, A / B / C phase AC current signals, and neutral line AC current signals on the outgoing side of the low-voltage distribution transformer in real time, measure real-time quantities (effective values ​​of voltage / current, power, power factor, harmonics, etc.), and count electrical energy (active energy, reactive energy, etc.). These data are used to calculate line losses, perform load analysis, and monitor overvoltage / overcurrent events.

[0003] Current intelligent fusion terminals use dedicated power metering chips to collect AC voltage and current signals for measurement and metering functions. Examples of dedicated power metering chips include the ATT7022 from Shanghai Juquan and the RN8302 from Shenzhen Ruineng Microelectronics. However, these dedicated power metering chips use a fixed sampling rate, which cannot meet the synchronous sampling requirements of the power quality standard QGDW10650 (the sampling rate is adjusted according to the AC voltage frequency of the power grid, which usually fluctuates around 50Hz). Therefore, they cannot provide accurate power quality indicator data, such as 10-cycle basic data (RMS voltage, RMS current, power, harmonics), voltage fluctuations, voltage flicker, voltage and current transients, and trigger waveform recording.

[0004] Marketing data for low-voltage distribution networks comes from the secondary current of the current transformer on the outgoing side of the low-voltage distribution transformer. This secondary current is more than 100 times smaller than the actual current, thus requiring precise measuring equipment to avoid large errors at low currents. However, existing dedicated energy metering chips cannot meet the requirements for accurate metering and are not suitable for low-voltage distribution networks. Summary of the Invention

[0005] This application provides an energy measurement chip for low-voltage distribution networks, which can be applied to the outgoing line side of low-voltage distribution transformers to provide high-precision energy metering data and energy quality data.

[0006] This application provides an energy measurement chip for low-voltage distribution networks, comprising: an analog sampling module, a sampling distribution module, an energy measurement module, and a control module;

[0007] The analog sampling module includes multiple analog-to-digital converters, which are used to acquire three-phase AC voltage analog signals, three-phase AC current analog signals and neutral line AC current analog signals respectively, and output digital sampling signal groups.

[0008] The sampling allocation module is used to sample the digital sampling signal group output by the analog sampling module and output multiple signal groups with different update rates, wherein the sampling rate of the first signal group is synchronized with the AC voltage frequency of the power grid.

[0009] The power measurement module includes a power quality module, which is used to calculate power quality data based on the first signal group output by the sampling and distribution module.

[0010] In this embodiment of the application, the sampling allocation module includes: a frequency tracking module, a downsampling module, and multiple signal extraction modules;

[0011] The frequency tracking module is used to calculate the frequency value of the voltage signal in the digital sampling signal group output by the analog sampling module;

[0012] The downsampling module is used to downsample the digital sampling signal group output by the analog sampling module at an adjustable sampling interval, output a first signal group with a sampling rate synchronized with the AC voltage frequency of the power grid and a signal value close to the original signal, and adjust the sampling interval according to the frequency value output by the frequency tracking module.

[0013] Each signal extraction module is used to extract and output signals from the digital sampling signal group output by the analog sampling module at a fixed extraction interval. Multiple signal extraction modules have different extraction intervals and output multiple signal groups with different update rates.

[0014] In this embodiment of the application, the frequency tracking module includes:

[0015] A low-pass filter is used to reduce voltage signals and voltage fluctuations exceeding a preset frequency in the digital sampling signal group;

[0016] DC cancellation filters are used to reduce the DC component and voltage fluctuations in the output signal of low-pass filters;

[0017] Zero-crossing detection circuit is used to detect zero-crossing points in the signal output by the DC cancellation filter;

[0018] The frequency calculation circuit is used to calculate the duration between consecutive zero crossings and to calculate the frequency value based on the duration between two crossing zero crossings.

[0019] The phase selector is used to calculate the maximum phase of the effective value of the voltage signal and select the frequency value of that maximum phase for output.

[0020] In this embodiment of the application, the low-pass filter is a 64th-order FIR digital filter; the low-pass filter obtains the filtered value and outputs it by weighting 64 consecutive voltage signal values ​​in the buffer with coefficients.

[0021] In this embodiment of the application, the DC cancellation filter calculates the average value of the voltage signal cached within the corresponding time period based on the filter value output by the low-pass filter, which is 1.5 times the latest frequency value, and subtracts the average value from the frequency value output by the phase selector to obtain the DC cancellation filter value.

[0022] In this embodiment, the zero-crossing detection circuit numbers the DC-canceling filter values ​​in natural number order, compares the current DC-canceling filter value with the previous DC-canceling filter value, and if the two change positively or negatively, the current DC-canceling filter value and its number and the previous DC-canceling filter value and its number are input to the frequency calculation circuit.

[0023] In this embodiment of the application, the frequency calculation circuit buffers 4 pairs of signal values, which correspond to 4 consecutive zero-crossing points. The time interval between the 1st and 3rd zero-crossing points is calculated to obtain the first frequency value, and the time interval between the 2nd and 4th zero-crossing points is calculated to obtain the second frequency value. The average of the first and second frequency values ​​is output to the phase selector as the average frequency value.

[0024] In this embodiment of the application, the phase selector buffers the average frequency value, calculates the effective value of the three-phase voltage signal using the duration corresponding to the previous average frequency value, and outputs the largest effective value among the effective values ​​of the three-phase voltage signal as the final frequency value.

[0025] In this embodiment, the downsampling module uses the sinc interpolation method to sample the digital sampling signal group output by the analog sampling module at a reduced frequency and an increased sampling interval.

[0026] In this embodiment of the application, the downsampling module buffers digital sampled signal groups and their corresponding time values. When the downsampling time value T... j Sampling and calculation are performed between the 64th and 65th time values ​​to obtain a downsampled signal. The downsampled time value T is then used. j Increase T1 as the next downsampling time value.

[0027] In this embodiment of the application, the power quality module includes: a power quality steady-state module and a power quality transient module; the power quality steady-state module is used to calculate the effective values, harmonic values ​​and power values ​​of the three-phase voltage signal, the three-phase current signal and the N-phase current signal based on the first signal group output by the sampling and distribution module; the power quality transient module is used to determine short-term changes in voltage or current based on the effective values ​​obtained by the power quality steady-state module.

[0028] In this embodiment of the application, the power quality steady-state module includes: an RMS value calculation circuit, a harmonic calculation circuit, and a power calculation circuit.

[0029] In this embodiment of the application, the effective value calculation circuit counts the synchronous sampling signals in the first input signal group, outputs an instantaneous effective value based on the 256 buffered data values, outputs a half-wave effective value when the count reaches 128, outputs a full-wave effective value when the count reaches 256, calculates a 10-cycle effective value based on the 10 buffered full-cycle effective values, and calculates a 150-cycle effective value based on the 15 buffered 10-cycle effective values.

[0030] In this embodiment of the application, the harmonic calculation circuit performs a fast Fourier transform on 256 consecutive synchronously sampled signals in the first input signal group to obtain 50 harmonic values, performs effective value aggregation on 10 consecutive non-overlapping harmonic values ​​to obtain 10-cycle harmonic values, and performs effective value aggregation on 15 consecutive non-overlapping 10-cycle harmonic values ​​to obtain 150-cycle harmonic values.

[0031] In this embodiment of the application, the power calculation circuit includes: a power calculation circuit, a powerless calculation circuit, and an apparent power calculation circuit.

[0032] In this embodiment, the power calculation circuit multiplies the voltage signal and current signal in the first input signal group to obtain the instantaneous fluctuation power value, obtains the physical unit power value based on the instantaneous fluctuation power value, inputs the physical unit power value into a low-pass filter to obtain the power value of this cycle; sums 10 consecutive non-overlapping power values ​​of this cycle to obtain a 10-cycle power value, and sums 15 consecutive non-overlapping 10-cycle power values ​​to obtain a 150-cycle power value.

[0033] In this embodiment, the power-free calculation circuit uses a phase shifter to perform Hilbert transformation on the voltage signal in the first input signal group, shifting each harmonic of the voltage signal by 90 degrees. The phase-shifted voltage signal is multiplied by the current signal to obtain the instantaneous fluctuating power-free value. The physical unit power value is obtained based on the instantaneous fluctuating power-free value. The physical unit power value is input into a low-pass filter to obtain the current-cycle power-free value. Ten consecutive non-overlapping current-cycle power-free values ​​are summed to obtain a 10-cycle power-free value. Fifteen consecutive non-overlapping 10-cycle power-free values ​​are summed to obtain a 150-cycle power-free value.

[0034] In this embodiment of the application, the apparent power calculation circuit is used to calculate the apparent power based on the power calculation results and the no-power calculation results.

[0035] In this embodiment, the power quality transient module is equipped with a voltage swell threshold register, a voltage swell delay register, a voltage droop threshold register, a voltage droop delay register, a flag register, and a timer. When the instantaneous effective value is greater than the voltage swell threshold register value, the timer starts counting. When the timer value is greater than the voltage swell delay register value, the flag register is set and the current time value is recorded. When the instantaneous effective value is less than the voltage swell threshold register value, the timer and the flag register are cleared.

[0036] In this embodiment of the application, the power quality module further includes: a voltage fluctuation module;

[0037] The voltage fluctuation module is used to detect voltage fluctuations per unit time based on the effective value obtained from the power quality steady-state module.

[0038] In this embodiment of the application, the voltage fluctuation module calculates the absolute value of the difference between two consecutive voltage half-wave effective values, compares the absolute value with a preset voltage fluctuation limit, and obtains the voltage fluctuation value.

[0039] In this embodiment of the application, the power quality module further includes: a power distribution service module;

[0040] The power distribution service module is used to calculate power distribution service data per unit time based on the effective value obtained from the power quality steady-state module.

[0041] In this embodiment of the application, the multiple signal groups with different update rates output by the sampling allocation module also include a second signal group, a third signal group, and a fourth signal group;

[0042] The power measurement module further includes: a power module and a voltage flicker module; the power module is used to measure power according to the second signal group output by the sampling and distribution module; the voltage flicker module is used to detect the short-time flicker and long-time flicker of the voltage signal in the third signal group output by the sampling and distribution module.

[0043] In this embodiment of the application, the electrical energy module includes:

[0044] An active energy calculation circuit is used to calculate the active energy of the three-phase voltage / current based on the second signal group.

[0045] The reactive energy calculation circuit is used to calculate the reactive energy of the three-phase voltage / current based on the second signal group.

[0046] Apparent energy calculation circuit, used to calculate the apparent energy of three-phase voltage / current based on the calculated active and reactive energy.

[0047] In this embodiment of the application, the voltage flicker module includes: a level matching module, a square detection module, a bandpass weighting module, a square smoothing module, and a hierarchical statistics module;

[0048] The level matching module filters the half-wave RMS value of the voltage signal in the third signal group, divides the voltage signal value by the half-wave RMS value, and outputs it to the square detection module. After passing through the bandpass weighting module and the square smoothing module, it is output to the hierarchical statistics module. The hierarchical statistics module performs hierarchical calculations to obtain the short-time flicker value.

[0049] In this embodiment of the application, the electrical energy measurement module further includes a waveform recording module; the waveform recording module is used to buffer the fourth signal group output by the sampling allocation module at a configured sampling frequency.

[0050] In this embodiment of the application, a timing module is also included; the timing module is used to provide time accurate to microseconds for the power quality module, the power energy module, the voltage flicker module and the waveform recording module.

[0051] In this embodiment of the application, the timing module includes: a second counter, a microsecond counter, a timer, and a time format conversion module; the timer is used to count the number of clock pulses during a second pulse period, output uniformly spaced microsecond pulses, and dynamically adjust the interval of the microsecond pulses according to the number of clock pulses during a second pulse period, so as to reduce the error between the value of the microsecond counter and the microsecond value of the actual time.

[0052] In this embodiment of the application, the formula for dynamically adjusting the interval of the microsecond pulse is:

[0053]

[0054] Where x, n, and k are integers, 10M = 10,000,000, and 10M represents the number of 10 10M pulses corresponding to each microsecond pulse; Calculated as a floating-point number, it represents the number of 10M pulses corresponding to each idealized microsecond pulse; P0 is the number of 10M pulses corresponding to the first microsecond pulse, P... n P is the number of clock pulses corresponding to the nth microsecond pulse. k It is the number of clock pulses corresponding to the (n-1)th microsecond pulse.

[0055] In this embodiment of the application, it further includes: a dual voltage reference module; the dual voltage reference module is used to provide two voltage references for the analog sampling module.

[0056] In this embodiment, the control module is a RISC-V instruction set architecture MCU that accesses the ADC module and the power measurement module via the Modbus protocol.

[0057] In this embodiment of the application, the MCU's code memory is provided with a permanently stored boot loading area.

[0058] The power measurement chip provided in this application outputs multiple sets of signals with different update rates through a sampling and distribution module, and ensures that the sampling rate of one set of signals is synchronized with the AC voltage frequency of the power grid. The power quality module can accurately calculate various power quality data based on the sampling signal synchronized with the AC voltage frequency of the power grid, so it can be applied to low-voltage distribution networks. Moreover, the multiple sets of signals with different update rates output by the sampling and distribution module can provide data support for the power measurement module to realize various measurement functions. Attached Figure Description

[0059] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0060] Figure 1 This is an architectural diagram of the power measurement chip provided in an embodiment of this application;

[0061] Figure 2 This is a schematic diagram of the signal and data flow of the power measurement chip provided in the embodiments of this application;

[0062] Figure 3 This is a structural diagram of the frequency tracking module provided in an embodiment of this application;

[0063] Figure 4 A structural diagram of the active energy calculation circuit of the energy data calculation module provided in this application embodiment;

[0064] Figure 5 A structural diagram of the reactive power calculation circuit of the power energy data calculation module provided in this application embodiment;

[0065] Figure 6 A structural diagram of the power quality steady-state data RMS value calculation circuit provided in the embodiments of this application;

[0066] Figure 7 A structural diagram of the power quality steady-state data harmonic calculation circuit provided in the embodiments of this application;

[0067] Figure 8 A structural diagram of a power calculation circuit is provided for the power quality steady-state data in the embodiments of this application;

[0068] Figure 9 This is a structural diagram of the power quality steady-state data power calculation circuit provided in the embodiments of this application;

[0069] Figure 10This is a structural diagram of the power quality steady-state data interharmonic calculation circuit provided in an embodiment of this application;

[0070] Figure 11 This is a structural diagram of the voltage flicker module provided in the embodiments of this application;

[0071] Figure 12 A structural diagram of the timing module provided in an embodiment of this application;

[0072] Figure 13 This is a structural diagram of the dual voltage reference circuit module provided in the embodiments of this application;

[0073] Figure 14 An architecture diagram of the MCU provided in the embodiments of this application;

[0074] Figure 15 This is an application connection diagram of the power measurement chip provided in the embodiments of this application;

[0075] Figure 16 This is a schematic diagram of the signal values ​​before and after the zero crossing and the sampling interval provided in the embodiments of this application. Detailed Implementation

[0076] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0077] As described in the background section, existing power metering chips use a fixed sampling rate, which cannot meet the synchronous sampling requirements of power quality specifications, thus failing to provide accurate power quality indicator data. Marketing data for low-voltage distribution networks comes from the secondary current of the current transformer on the outgoing side of the low-voltage distribution transformer, which is more than 100 times smaller than the actual current. Therefore, precise measuring equipment with a specific range is needed to avoid large errors at low currents. However, existing dedicated power metering chips cannot meet the requirements for accurate metering and are not suitable for low-voltage distribution networks.

[0078] To address the aforementioned issues, this application provides a power measurement chip for low-voltage distribution networks, comprising an analog sampling module, a sampling distribution module, a power measurement module, and a control module. The analog sampling module includes multiple analog-to-digital converters (ADCs) for acquiring three-phase AC voltage analog signals, three-phase AC current analog signals, and neutral line AC current analog signals, respectively, and outputting digital sampling signal groups. The sampling distribution module samples the digital sampling signal groups output by the analog sampling module, outputting multiple signal groups with different update rates, wherein the sampling rate of the first signal group is synchronized with the AC voltage frequency of the power grid. The power measurement module includes a power quality module, which calculates power quality data based on the first signal group output by the sampling distribution module. This power measurement chip, through the sampling distribution module outputting multiple signal groups with different update rates and ensuring that the sampling rate of one signal group is synchronized with the AC voltage frequency of the power grid, allows the power quality module to accurately calculate various power quality data based on the sampling signal synchronized with the AC voltage frequency of the power grid. Therefore, it can be applied to low-voltage distribution networks. Furthermore, the multiple signal groups with different update rates output by the sampling distribution module provide data support for the power measurement module to perform various measurement functions. The above plan will be explained in detail below.

[0079] Figure 1 This is an architectural diagram of the power measurement chip provided in an embodiment of this application. Figure 1As shown in the embodiment of this application, the power measurement chip includes an analog sampling module, a sampling distribution module, a power measurement module, a control module, a dual voltage reference module, and a timing module. The analog sampling module includes a 7-channel Σ-Δ analog-to-digital converter (Sigma-Delta ADC), used to acquire three-phase (A / B / C phase) AC voltage signals, three-phase (A / B / C phase) AC current signals, and neutral (N phase) AC current signals, respectively, and output a set of digitized high-speed sampling signals. The dual voltage reference module provides two voltage references for the analog sampling module; when one voltage reference fails, the other can be used. The timing module provides timing accurate to microseconds for all measurement data. The sampling distribution module samples the digital sampling signal group output by the analog sampling module, outputting multiple signal groups with different update rates, wherein the sampling rate of the first signal group is synchronized with the AC voltage frequency of the power grid. The power measurement module includes a power quality module, a power module, a voltage flicker module, and a waveform recording module. The power quality module calculates power quality data based on the first signal group output by the sampling distribution module. The power metering module is used to measure power based on the second signal group output by the sampling and distribution module. The voltage flicker module is used to detect short-time and long-time flicker of the voltage signal in the third signal group output by the sampling and distribution module. The waveform recording module is used to buffer the fourth signal group output by the sampling and distribution module. The timing module is used to provide microsecond-accurate timing for the power quality module, power metering module, voltage flicker module, and waveform recording module. The control module adopts a RISC-V instruction set architecture MCU (Microcontroller Unit), which has the advantages of security and easy expansion due to its open-source instruction set architecture. The power metering chip provided in this application embodiment uses a RISC-V instruction set-based MCU as its core and employs dedicated circuit modules to implement real-time, standardized computing functions to improve performance and reliability, simplify usage, and reduce power consumption. Each dedicated circuit module has its own registers, mapped to the MCU's SRAM address. The MCU uses these registers to configure and control each dedicated module and read the data output by these modules.

[0080] The sampling allocation module includes a frequency tracking module, a downsampling module, and multiple signal decimation modules. The frequency tracking module calculates the frequency value of the voltage signal in the digital sampled signal group output by the analog sampling module. The downsampling module downsamples the digital sampled signal group output by the analog sampling module at an adjustable sampling interval, outputting a first signal group with a sampling rate synchronized with the AC voltage frequency of the power grid and approximating the original analog signal, and adjusts the sampling interval according to the frequency value output by the frequency tracking module. Each signal decimation module extracts a signal from the digital sampled signal group output by the analog sampling module at a fixed decimation interval and outputs it. The multiple signal decimation modules have different decimation intervals, and the multiple signal decimation modules output multiple signal groups with different update rates.

[0081] The power quality module includes a steady-state power quality module, a transient power quality module, a voltage fluctuation module, and a distribution service module. The steady-state power quality module calculates the effective values, harmonic values, and power values ​​of the three-phase voltage signals, three-phase current signals, and N-phase current signals based on the first signal group output by the sampling and distribution module. The transient power quality module identifies short-term voltage or current fluctuations based on the effective values ​​obtained from the steady-state power quality module. The voltage fluctuation module detects voltage fluctuations per unit time based on the effective values ​​obtained from the steady-state power quality module. The distribution service module calculates distribution service data per unit time based on the effective values ​​obtained from the steady-state power quality module.

[0082] Reference Figure 2In one embodiment, the analog sampling module employs seven 24-bit coded second-order (SigmaDelta) ΣΔ type ADCs to acquire the voltage signals of phases A / B / C and the current signals of phases A / B / C / N, respectively. Registers include voltage phase compensation registers phCompA / phCompB / phCompC for phases A / B / C, used to compensate for the phase difference between the voltage and current signals of each phase. This embodiment uses SigmaDelta type ADCs to output 24-bit coded values, providing high-precision sampling data for subsequent power quality data calculations. The analog sampling module outputs a set of high-speed sampling signals (s102k4 signal group) to the sampling distribution module, with an update rate of 50*256*8Hz, including the A / B / C phase voltage sampling signals vA102k4 / vB102k4 / vC102k4 and the A / B / C / N phase current sampling signals iA102k4 / iB102k4 / iC102k4 / iN102k4. The sampling allocation module includes a frequency tracking module, a first downsampling module, a second downsampling module, a first signal extraction module, and a second signal extraction module. The frequency tracking module measures the voltage frequency value in real time. The first downsampling module samples the s102k4 signal group at adjustable sampling intervals using an interpolation method, obtaining a signal group s256 with a sampling rate synchronized with the AC voltage frequency of the power grid and signal values ​​approximating the original analog signal. The second downsampling module samples the s102k4 signal group to obtain the s80 signal group. The first signal extraction module extracts signals from the s102k4 signal at integer intervals of 8, outputting the s12k8 signal group, including the A / B / C phase voltage sampling signals vA12k8 / vB12k8 / vC12k8 and the A / B / C / N phase current sampling signals iA12k8 / iB12k8 / iC12k8 / iN12k8. The second signal extraction module extracts signals from the s102k4 signal at integer intervals of 32, outputting the s3k2 signal group, which includes the A / B / C phase voltage sampling signals vA3k2 / vB3k2 / v3k2 and the A / B / C / N phase current sampling signals iA3k2 / i3k2 / iC3k2 / iN3k2. The sampling and distribution module outputs four signal groups: s256, s12k8, s3k2, and s80. The first signal group (s256, synchronized with the AC voltage frequency of the power grid) is output to the power quality steady-state module for calculating the effective value, harmonic value, and power value; the effective value calculated by the power quality steady-state module is output to the power quality transient module, voltage fluctuation module, and distribution business module. The second signal group (s12k8) is output to the energy module for calculating active energy, reactive energy, and apparent energy. The third signal group (S3K2 signal group) is output to the voltage flicker module to detect short-term and long-term flicker of the voltage signal. The fourth signal group (S80 signal group) is output to the waveform recording module for buffering.The timing module provides timing accurate to microseconds for the power quality steady-state module, power quality transient module, voltage fluctuation module, power distribution business module, power energy module, voltage flicker module, and waveform recording module.

[0083] In this embodiment, the frequency of the voltage signal is measured in real time by a frequency tracking module, and a synchronous sampling signal that approximates the original analog signal is obtained by a downsampling module. Based on the synchronous sampling signal, various power quality data can be accurately calculated.

[0084] Reference Figure 3 In one embodiment, the frequency tracking module receives three voltage acquisition signals vA102k4 / vB102k4 / vC102k4 as input signals, updates at a frequency of 25600Hz, and outputs the frequency value FRQ of the voltage signal, which is stored in a frequency register. The frequency tracking module includes sub-circuits such as a low-pass filter, a DC-canceling filter, a zero-crossing detection circuit, a frequency calculation circuit, and a phase selector. The low-pass filter is used to reduce voltage signals and voltage fluctuations above a preset frequency in the digital sampling signal group; the DC-canceling filter is used to reduce the DC component and voltage fluctuations in the low-pass filter output signal; the zero-crossing detection circuit is used to detect zero-crossings in the signal output by the DC-canceling filter; the frequency calculation circuit is used to calculate the duration between consecutive zero-crossings and calculate the frequency value based on the duration between two intersecting zero-crossings; the phase selector is used to calculate the maximum phase of the effective value of the voltage signal and selects the frequency value of that maximum phase for output. The low-pass filter for each phase is used to attenuate components above 60Hz in the voltage signal. The low-pass filter uses a 64th-order FIR digital filter, which has a fixed and stable delay. Frequency measurement only considers the duration between zero-crossing points of the signal and is insensitive to signal amplitude. The optimal filter coefficients, obtained from MATLAB library functions, are fir2(63, [0,0.001,0.005,0.008,1],[0,0.8,1,0,0]); when the sampling rate is 25600, the corresponding cutoff frequencies are 51.2Hz and 75Hz.

[0085] The DC-canceling filter calculates the average of the voltage signal values ​​buffered within the corresponding time period, which is 1.5 times the reciprocal of the latest frequency value, based on the filter value output by the low-pass filter. This average value is then subtracted from the frequency value output by the phase selector to obtain the DC-canceling filter value. The DC-canceling filter eliminates the DC component of the low-pass filter output signal and outputs it to the zero-crossing detection circuit. Eliminating the DC component makes the zero-crossing point closer to the signal's true zero-crossing point, thus improving frequency measurement accuracy. The zero-crossing detection circuit numbers the DC-canceling filter values ​​in natural number order and compares the current DC-canceling filter value with the previous one. If a positive-negative or negative-positive change occurs, the current DC-canceling filter value and its number, along with the previous DC-canceling filter value and its number, are input to the frequency calculation circuit. The frequency calculation circuit buffers four pairs of signal values, each corresponding to one of four consecutive zero-crossing points. The time interval between the first and third zero-crossing points is calculated to obtain the first frequency value, and the time interval between the second and fourth zero-crossing points is calculated to obtain the second frequency value. The average of the first and second frequency values ​​is then output to the phase selector as the frequency average. The phase selector buffers the average frequency value, calculates the effective value of the three-phase voltage signal using the duration corresponding to the previous average frequency value, and outputs the largest effective value among the effective values ​​of the three-phase voltage signals as the final frequency value FRQ.

[0086] Taking phase A as an example, the frequency tracking module's workflow is as follows: Whenever the vA102k4 signal is updated, the low-pass filter first buffers the signal, then performs a weighted operation on the latest 64 consecutive vA102k4 signal values ​​using filter coefficients, and sends the calculated filtered value vA102k4L to the DC cancellation filter; the DC cancellation filter first checks vA102k4L, then calculates the average value of the latest buffered vA102k4L within a duration of 1.5 / FRQ (time T = the reciprocal of frequency F) based on the current FRQ value, subtracts this average value from the newly entered vA102k4L to obtain vA102k4H, and sends it to the zero-crossing detection circuit; the zero-crossing detection circuit numbers the filtered value in natural number order and compares the filtered value with the previous filtered value. If a sign change occurs, i.e., from positive to negative or from negative to positive, the two filtered values ​​and their numbers are sent to the frequency calculation circuit. The frequency calculation circuit buffers the newly input signal, buffering a total of four pairs of signal values, corresponding to four consecutive zero-crossing points. It calculates the time interval between the first and third zero-crossing points to obtain the frequency value FRQ1, and calculates the time interval between the second and fourth zero-crossing points to obtain the frequency value FRQ2. The average of FRQ1 and FRQ2, FRQA, is output to the phase selector. The phase selector buffers the input voltage signal, calculates the effective value of the three-phase voltage signal using the duration corresponding to the previous frequency value, determines which phase has the largest effective value, and outputs the frequency value FRQ of that phase to the frequency register. Therefore, the correct frequency value can be obtained after 1.5 cycles.

[0087] The principle of calculating the time between zero crossings is that the phase value and sine value of a sine wave near the zero crossing are close to zero and approximately linearly related. Therefore, the time point when the zero signal value occurs can be derived from the signal value before and after the zero crossing and the sampling interval.

[0088] Let the sampling interval be Ts, and let the sampled values ​​before and after a certain zero crossing be v1 and v2, and the sampling times be t1 and t2, where t1 - t2 = Ts. Then the time when the signal value becomes zero is:

[0089]

[0090] Mark the signal values ​​before and after the four zero-crossing points as v11, v12, v21, v22, v31, v32, v41, v42, and the signal value indices as j11, j12, j21, j22, j31, j32, j41, j42. Then the frequency values ​​FRQ1 and FRQ2 are represented as:

[0091]

[0092]

[0093] The mean values ​​of FRQ1 and FRQ2 are:

[0094]

[0095] Simulation tests were conducted using a simulator. The modulation method and harmonic superposition method of the input simulation waveform were based on the national standard GBT17626.30, resulting in voltage fluctuations, and frequency tracking simulation results were obtained. According to the simulation results of the frequency tracker, when the modulation frequency FreqMod changed from 3.5Hz to 33.3Hz, the fundamental frequency Frq changed from 47.5Hz to 52.5Hz, and the harmonic order changed from the 2nd to the 50th, a 0.01Hz error could be measured even when four harmonics were superimposed. This shows that the frequency measurement method in this embodiment can overcome the interference of voltage fluctuations. However, most existing methods for measuring power grid frequency use the fundamental phase method, performing FFT calculations after each data point sampling. This method is not only computationally intensive, but also suffers from severe spectral leakage in the FFT calculation results when voltage fluctuations occur, leading to excessive deviations in the frequency measurement results and failing to overcome the interference of voltage fluctuations.

[0096] In summary, the frequency tracking module in this embodiment uses a unique filter structure, filter parameters, and cross-zero point method to measure voltage frequency, overcoming harmonic interference and voltage fluctuation interference, thus ensuring stability while improving measurement accuracy and measurement time.

[0097] Most current downsampling methods employ linear interpolation, which is ineffective when dealing with higher harmonics, resulting in large errors and inflated effective values ​​for these harmonics. This application's embodiment uses a sinc interpolation method to sample the digital sampling signal group output by the analog sampling module at a lower frequency and with a larger sampling interval, thus reducing sampling errors. The first downsampling module samples a smooth, variable-rate signal group from the s102k4 signal group with a fixed update rate, using a lower frequency and a larger sampling interval to achieve synchronous sampling. During downsampling, the downsampling interval T1 is adjusted in a timely manner based on the frequency value FRQ output by the frequency tracking module, ensuring 256 points are sampled within one AC voltage cycle of the power grid. The downsampling module outputs A / B / C phase voltage signals vA256 / vA256 / vA256 and A / B / C / N phase current signals iA256 / iB256 / iC256 / iN256. Taking the A-phase voltage signal as an example, the downsampling process is explained as follows: Whenever vA102k4 enters, the signal value and the current timing module's time value are buffered, totaling 128 values, stored sequentially in a first-in, first-out manner. When the downsampling time value T... j A downsampled signal is obtained by sampling between the 64th and 65th time values, and the output is vA256. T is then... j Increase T1. The initial downsampling time value T. j The midpoint between the 64th and 65th signals is taken. The downsampling calculation principle is based on the sinc function principle. The prototype of the sinc function is sinc(x) = sin(π*x) / (π*x), sinc(0) = 1. According to digital signal theory, for signals with finite bandwidth, when the sampling rate satisfies the Nyquist sampling theorem, the original signal can be reconstructed from the sampled signal. One reconstruction method is to use the sinc function to perform a weighted calculation on the sampled values, with the following formula:

[0098]

[0099] Where x(n*Ts) is the nth sampled value, and the function h() has the form h(t)=sin(π*Fs*t) / (π*Fs*t), that is, the signal value at time t is calculated using multiple sampled values ​​before and after time t. Due to the limited bandwidth of the power grid signal, this embodiment uses the downsampling time T. jThere are 64 sampled values ​​before and after the sine function. Since directly calculating the sine function is complex and time-consuming, this embodiment uses the characteristics of the sinc function to simplify its calculation. The derivation process is as follows: In the above formula, since the parameter of the h() function is only the time difference, let the time value of n=0 be 0, n take values ​​from -63 to 64, t take values ​​greater than or equal to 0 and less than Ts, denoted as dt, which is between the time of sampled value 0 and sampled value 1, dt = a * Ts, where a is greater than or equal to 0 and less than 1 and is a floating-point number. When n = 0, sin(π*Fs*(dt-0*Ts)) = sin(π*a); when n = 1, sin(π*Fs*(dt-Ts)) = sin(π*a-π) = -sin(π*a); when n = 2, sin(π*Fs*(dt-2*Ts)) = sin(π*a-2*π) = sin(π*a)... Therefore, performing one downsampling calculation only requires one positive function calculation, which greatly reduces the complexity of the hardware circuit implementation. Furthermore, from the symmetry of the sine waveform, it can be seen that if the sine value between 0 radians and π / 2 radians is known, then the sine value between π / 2 radians and π radians can be obtained directly. The sine value between 0 radians and π / 2 radians is obtained by looking up a table. The 0 to π / 2 radians range is divided into 180 points, and the sine values ​​are arranged in natural order as an array and stored in the ROM array, labeled as sinTbl. The sine values ​​are sin(0) = 0, sin(1*π / 360) = 0.0087265355, sin(2*π / 360) = 0.017452406, ..., sin(179*π / 360) = 0.9999619, and sin(180*π / 360) = 1.0. After calculating a, let b = a * 360.0. When b is greater than or equal to 180, b = b - 180. Let the integer part of b be bi. Then sin(π * a) = sinTbl[bi] + (b - bi) * (sinTbl[bi + 1] - sinTbl[bi]). Through MATLAB simulation experiments, it can be verified that the error of the 50th harmonic measured by this method is less than 1 / 1000, while it is greater than 3% when using the sampling linear interpolation method. The experimental signal contains multiple harmonics and voltage fluctuations.

[0100] In summary, the first downsampling module uses the sinc interpolation method to overcome the spectral leakage of linear interpolation, ensuring the accuracy of power quality indicators. By utilizing the characteristics of the sinc function, only one sine calculation is performed for each downsampling calculation. Furthermore, by utilizing the symmetry of the sine function, a lookup table method is used to calculate the sine value, which greatly reduces the amount of computation and facilitates hardware circuit implementation.

[0101] The principle of the second downsampling module is similar to that of the first downsampling module. The difference is that the sampling interval of the second downsampling module comes from its configuration register, which is set by the control module.

[0102] In one embodiment, the electrical energy module is used to statistically analyze various types of electrical energy and is designed with various registers: a pulse threshold register pulConst, used to control the output speed of the electrical energy pulse; three-phase active power correction registers GPA, GPB, and GPC, used to correct active power pulse errors; three-phase reactive power correction registers GQA, GQB, and GQC, used to correct reactive power pulse errors; three-phase active power offset registers OSPA, OSPB, and OSPC, used to correct active power pulse errors under low current conditions; and three-phase reactive power offset registers OSQA, OSQB, and OS... QC is used to correct reactive pulse errors under low current conditions; three-phase forward / reverse active energy pulse count registers pulA1 / pulA2, pulB1 / pulB2, pulC1 / pulC2; three-phase forward / reverse reactive energy pulse count registers QpulA1 / QpulA2, QpulB1 / QpulB2, QpulC1 / pulC2; three-phase forward / reverse apparent energy pulse count registers SpulA1 / SpulA2, SpulB1 / SpulB2, SpulC1 / SpulC12.

[0103] The electrical energy module includes active energy calculation circuits, reactive energy calculation circuits, and apparent energy calculation circuits. Each type of calculation circuit includes signal processing circuits for phases A, B, and C. The active energy calculation circuit, reactive energy calculation circuit, and apparent energy calculation circuit calculate active energy, reactive energy, and apparent energy in parallel. Taking the phase A signal processing circuit as an example (the data acquisition process for phases B and C is similar), each time vA12k8 and iA12K8 are updated, the active energy calculation circuit is triggered to run once, updating the various energy values ​​for phase A.

[0104] Reference Figure 4 The active power calculation circuit includes a squarer, an adder, a multiplier, an accumulator, and a comparator. Step 1: Multiply vA12k8 and iA12k8. Step 2: Add OSPA to the product. Step 3: Multiply by GPA to obtain the instantaneous active power PA1. Step 4: Accumulate PA1 into register PA2. Step 5: If the absolute value of PA2 is greater than pulConst, PA2 is positive and pulA1 is increased; otherwise, pulA2 is increased.

[0105] Reference Figure 5The reactive power calculation circuit includes a phase shifter, a squarer, an adder, a multiplier, an accumulator, and a comparator. The calculation of reactive power and active power in phase A is started simultaneously. The first step is to perform a Hilbert transform on vA12k8 to obtain vA12k8H, so that each harmonic component in the voltage signal is phase-shifted by 90 degrees. The second step is to multiply vA12k8H and iA12K8. The third step is to accumulate the product into OSQA. The fourth step is to multiply it by GQA to obtain the instantaneous reactive power QA1. The fifth step is to accumulate QA1 into register QA2. The sixth step is to increase QpulA1 if QA2 is positive when its absolute value is greater than pulConst, otherwise increase QpulA2.

[0106] Regarding the apparent electrical energy of phase A, the first step is to obtain the instantaneous apparent power SA1 by using the root mean square function sqrt(PA1*PA1+QA1*QA1) after updating QA1. The second step is to accumulate SA1 into the register SA2. The third step is to increase SpulA1 if PA2 is positive when SA2 is greater than pulConst, otherwise increase SpulA2. The function sqrt() performs the square root operation.

[0107] The power quality steady-state module is designed with various registers: a register updating at 12.8kHz for one cycle of RMS value, registers updating every half cycle / one cycle of RMS value, registers updating every 10 cycles (including RMS values ​​of voltage / current for each phase, power availability / absence for each phase, power factor for each phase, RMS values ​​of harmonics / interharmonics of voltage / current for each phase, RMS value / power coefficient register, and RMS value / power offset register), and registers updating every 150 cycles (similar to the 10-cycle registers). Sub-circuit modules include buffers, counter circuits, RMS value calculation circuits, FFT calculation circuits, multiplication circuits, etc.

[0108] The power quality steady-state module includes an RMS calculation circuit, a harmonic calculation circuit, a power calculation circuit, and an interharmonic calculation circuit, which are used to calculate steady-state data such as RMS values, harmonic values, power values, and interharmonics.

[0109] Regarding the calculation of RMS values, the calculation methods for the RMS values ​​of phase A, B, and C voltages are similar and performed in parallel. The calculation methods for the RMS values ​​of phase A, B, C, and N currents are similar. (Refer to...) Figure 6Taking the calculation of the effective value of phase A voltage as an example, the effective value calculation is triggered every time the vA256 signal is updated. Step 1: Use a counter to count the number of input vA256 signals. Step 2: The "256-point RMS module" outputs an instantaneous RMS value VrmsA256 using the latest 256 vA256 values ​​in the buffer. Step 3: When the counter value reaches 128, it outputs a half-wave RMS value VrmsA05. Step 4: When the counter value reaches 256, it outputs a full-wave RMS value VrmsA1 and clears the counter. Step 5: Buffer VrmsA1. When the buffer size is 10, these 10 full-wave RMS values ​​are aggregated to calculate a 10-wave RMS value VrmsA10, and the buffer is cleared. Step 6: Buffer VrmsA10. When the buffer size is 15, these 15 10-wave RMS values ​​are aggregated to calculate a 150-wave RMS value VrmsA150, and the buffer is cleared. Each time an RMS value is calculated, the time value TIM from the timing module is assigned to that RMS value. The above-mentioned effective value aggregation calculation refers to performing operations such as squaring, summing, averaging, and square rooting on numerical values.

[0110] Regarding harmonic value calculation, the calculation methods for phase A, B, and C voltage harmonics are similar and performed in parallel; the calculation methods for phase A, B, C, and N current harmonics are similar. (Refer to...) Figure 7 Taking the calculation of the effective value of phase A voltage as an example, a harmonic calculation is triggered every time the VA256 signal is updated. The 256-point FFT calculation module performs a 256-point FFT (fast Fourier transform) calculation on 256 consecutive sampled values ​​(non-overlapping, window mode) to obtain 50 harmonic values ​​HVrmsA1_1…HVrmsA1_50. The 10-point effective value calculation module performs an effective value aggregation operation on 10 consecutive harmonic values ​​(non-overlapping, window mode) to obtain 10-cycle harmonic values ​​VrmsA10_1…HVrmsA10_50. The 15-point effective value calculation module performs an effective value operation on 15 consecutive 10-cycle harmonic values ​​(non-overlapping, window mode) to obtain 150-cycle harmonic values ​​VrmsA15_1…HVrmsA15_50. Whenever a harmonic value is calculated, the time value TIM of the timing module is assigned to that harmonic value.

[0111] The power calculation circuit includes: a power calculation circuit, a no-power calculation circuit, and an apparent power calculation circuit, which calculate the power, no-power, and apparent power respectively.

[0112] For power calculations, please refer to... Figure 8Taking phase A signal as an example, signals vA256 and iA256 are multiplied by a squarer to obtain the instantaneous fluctuation power. An adder adds a correction value osPA to this product to eliminate parasitic small signals in the circuit. A multiplier then multiplies this sum by gPA to obtain the actual power value in physical units. This product is then fed into a low-pass filter (LPF) to eliminate fluctuations and obtain the power value pwrA for this cycle. The arithmetic sum of 10 consecutive (non-overlapping, windowed) pwrA values ​​yields the power value pA10 for the 10th cycle. The arithmetic sum of 15 consecutive (non-overlapping, windowed) pA10 values ​​yields the power value pA15 for the 150th cycle.

[0113] Regarding power-free calculations, refer to... Figure 9 Taking the A-phase signal as an example, the vA256 signal is transformed by a phase shifter to obtain vA256H so that each harmonic of the voltage signal is phase-shifted by 90 degrees. The vA256H and iA256 are multiplied by a squarer to obtain the instantaneous ripple power. The product is then added to a correction value osQA to eliminate parasitic small signals in the circuit. The sum is multiplied by gQA to obtain the power value in the real physical unit. This product is then sent to a low-pass filter LPF to eliminate ripples and obtain the power value qpwrA of this cycle. The arithmetic sum of 10 consecutive (non-overlapping, windowed) qpwrA is obtained to obtain the power value qA10 of the 10-cycle. The arithmetic sum of 15 consecutive (non-overlapping, windowed) qA10 is obtained to obtain the power value qA15 of the 150-cycle.

[0114] Based on the results of the power calculations and power-free calculations above, the apparent power can be calculated. Specifically, the apparent power at 10 Hz is sA10 = sqr(pA10*pA10 + qA10*qA0); the apparent power at 150 Hz is sA15 = sqrt(pA15*pA15 + qA15*qA15).

[0115] The interharmonic calculation circuit is used to calculate the interharmonic data of three-phase voltage / current based on the first set of signals output by the sampling and distribution module and the 10-cycle RMS values ​​obtained by the RMS value calculation circuit. The interharmonic calculation circuit is equipped with voltage interharmonic RMS value registers IHVrmsA10_1..IHVrmsA10_500, IHVrmsB10_1..IHVrmsB10_500, IHVrmsC10_1..IHVrmsC10_500, and current interharmonic RMS value registers IHIrmsA10_1..IHIrmsA10_500, IHIrmsB10_1..IHIrmsB10_500, IHIrmsC10_1..IHIrmsC10_500, ranging from order 1 to 500. The sub-circuits of the interharmonic calculation circuit include a 1024-point FFT calculation module, a buffer vAbuf, and a counter.

[0116] In one embodiment, refer to Figure 10 Taking the interharmonics of phase A voltage as an example, the interharmonic calculation method is as follows: the interharmonic calculation circuit is triggered every time the vA256 signal is updated. The buffer vAbuf stores a certain amount of vA256 signal values, and the counter vA256N is used to count the number of vA256 signal values ​​buffered in the buffer between two consecutive 10-cycle RMS values ​​VrmsA10 (output by the RMS value calculation circuit). Every time the 10-cycle RMS value is updated, the time length TJ of the buffer data is first calculated based on vA256N, and the minimum interharmonic frequency value 1.0 / TJ is calculated. Then, 1024 data points are downsampled from vAbuf (the downsampling method is the same as described above). The counter and buffer are cleared to receive the next 10-cycle vA256, and a 1024-point FFT is performed to obtain a total of 500 interharmonic data points for the 10-cycle. The calculation of current interharmonics is similar to that of voltage interharmonics.

[0117] In one embodiment, the power quality transient module is used to determine short-term voltage or current surges based on the instantaneous effective value output by the effective value calculation circuit. This includes analyzing voltage sags, swells, interruptions, and current surges based on one cycle of effective values ​​for the three-phase voltage and four-phase current, with time intervals less than half a cycle. Transient analysis refers to short-term surges in the effective values ​​of voltage or current, lasting from less than half a cycle to a few seconds. To accurately capture subtle changes in the effective values ​​of voltage or current, this embodiment uses effective values ​​updated at 12.8 kHz for transient analysis, implemented using hardware circuitry. The power quality transient module includes voltage swell threshold registers SW1 / SW2, voltage swell delay registers SW1T / SW2T, voltage swell threshold registers DIP1 / DIP2, voltage swell delay registers DIP1T / DIP2T, and flag registers SW1F / SW2F / DIP1F / DIP2F. Sub-circuits include counters, comparators, etc. Taking phase A voltage as an example, this module is triggered to run once whenever the instantaneous effective value VrmsA256 output by the effective value calculation circuit is updated. When VrmsA256 is greater than SW1, the internal timer is started. When the timer value is greater than SW1T, SW1F is set and the time TIM is recorded. When VrmsA256 is less than SW1, the timer and SW1F are cleared. Currently, commonly used metering chips analyze voltage as follows: at the zero-crossing point of the voltage waveform, the timer value is checked once every half cycle to see if it exceeds the threshold value. This method requires a relatively large threshold value; if the threshold value is not set large enough, it may miss brief changes in voltage.

[0118] The distribution service data calculation module is used to calculate the distribution service data per unit time based on the one-cycle effective value output by the power quality steady-state module. Since the distribution data is updated second by second, the one-cycle data output by the power quality steady-state module is aggregated and calculated according to the power quality standard QGDW10650 to obtain the voltage / current effective values, power, harmonic data, etc., for one second. The aggregation strategy is as follows: the end time of one cycle must be greater than the second of the current aggregation value, and the timescale of the one-cycle statistics for the current second's aggregation value must be greater than the previous second. This ensures that the timescale error of each data point for the distribution service is less than 0.01 seconds, and that each measurement value is continuous and non-overlapping, following the AC signal of the power grid, facilitating distribution service load analysis. The aggregation method here refers to performing square, sum, mean, and square root calculations when aggregating a set of continuous effective values, and performing mean calculations when aggregating a set of continuous power values.

[0119] The voltage fluctuation detection module is used to detect voltage fluctuations per unit time based on the half-wave RMS value of the voltage output by the power quality steady-state module, and to count the number of voltage changes and the maximum value of each phase voltage per unit time. The voltage fluctuation calculation method follows GBT12326-2008. Voltage fluctuation refers to the difference between two adjacent extreme values ​​on the root mean square voltage curve, used to measure the magnitude of voltage fluctuation. Voltage fluctuation frequency is the number of voltage changes per unit time, used to measure the speed of voltage fluctuation. The voltage fluctuation detection module uses the synchronously sampled half-cycle RMS value as the basis for detection. In one embodiment, a register VchgT is used to configure the statistical duration (in minutes), and four configuration registers are used to store the voltage fluctuation limits VchgL1 / VchgL2 / VchgL3 / VchgL4 for four levels. For each phase voltage, four registers are used to store the number of voltage changes VchgR1 / VchgR2 / VchgR3 / VchgR4 within the previous VchgT duration, and one register is used to store the maximum voltage change VchgDmax within the previous VchgT duration.

[0120] In one embodiment, the voltage fluctuation module calculates the absolute value of the difference between two consecutive voltage half-wave RMS values, compares this absolute value with a preset voltage fluctuation limit, and obtains the voltage fluctuation value. Voltage fluctuation detection can be implemented using software code because the voltage fluctuation analysis logic is relatively complex, and the real-time requirement is not particularly stringent as calculations are performed every 10 milliseconds. A voltage fluctuation detection calculation is triggered whenever the half-wave RMS value VArms05 is updated. The detection process is as follows: Calculate the absolute value of the difference between two consecutive VArms05 values, dif. If the absolute value dif is greater than the voltage variation limit VchgL1, increment VchgR1 by 1. If the absolute value dif is greater than the voltage variation limit VchgL2, increment VchgR2 by 1. If the absolute value dif is greater than the voltage variation limit VchgL3, increment VchgR3 by 1. If the absolute value dif is greater than the voltage variation limit VchgL4, increment VchgR4 by 1. If the absolute value dif is greater than the maximum voltage variation limit VchgDmax, assign dif to VchgDmax. When the cumulative duration of this detection exceeds the statistical duration VchgT, clear VchgL1 / VchgL2 / VchgL3 / VchgL4 and VchgDmax, and start a new round of detection.

[0121] The voltage flicker module is used to detect short-time and long-time flicker of the voltage signal in the third signal group output by the sampling and distribution module, thereby enabling the detection of flicker in the voltage signal input to the analog sampling module. Voltage flicker is a power quality indicator that measures voltage fluctuations, and is divided into short-time flicker (Pst) updated every 10 minutes and long-time flicker (Plt) updated every 2 hours. In one embodiment, each phase voltage corresponds to a flicker calculation circuit, and each calculation link is as follows: Figure 11 As shown, the system includes a level matching module, a square detection module, a bandpass weighting module, a smoothing module, and a hierarchical statistics module, corresponding to modules 1, 2, 3, 4, and 5 as specified in GB / T 12326, respectively. The calculation methods for each module also follow the provisions of GB / T 12326. The voltage flicker module is designed with an instantaneous visual sensitivity register Pinst and a short-time flicker register Plt. Taking phase A voltage as an example (phase B / C voltages are similar), the voltage flicker detection process is as follows: the level matching module processes the voltage signal vA3k2 from the third group of signals output by the sampling and distribution module to obtain vA3200, and outputs it to the square detection module to maintain the effective value of vA3200 at a constant value. The processing method is that the half-wave effective value of vA3k2 is passed through a 27.3-second IIR type first-order digital low-pass filter, and the output value of this filter is used to divide the vA3k2 signal to obtain vA3200. The vA3200 has an update rate of 3200Hz, which avoids aliasing effects of high-frequency signals. After being output to the square detector module, the output value after bandpass filtering, weighted filtering, and smoothing filtering is the real-time visual sensitivity Pinst. This value is normalized using the effective value of one cycle; that is, when the input voltage is modulated by an 8.8Hz sine wave, its value is 1. The update frequency is 1000Hz, which is more than 30 times the passband frequency of the bandpass filter (35Hz). The value is output to the dedicated register Pinst. Whenever its value is updated, the MCU (control module) reads the value and inputs it into the hierarchical statistics module. The hierarchical statistics module is implemented in MCU code and outputs the short-time flicker value Pst, which is updated every 10 minutes, with the 10-minute interval aligned with the actual 10-minute time. The implementation method of the graded statistical module is based on the cumulative probability function (CPF) method specified in Appendix A of GB / T 12326. The maximum value of Pinst is set to 10, which is 10 times the value of 1 specified in GB / T 12326, ensuring a wide measurement range. It is divided into 1000 levels, with each level differing by 0.01. According to the Pst calculation formula, at the reference detection point, sqrt(1+0.01) / sqrt(1.0) = 1.005, which is much smaller than the 5% measurement error requirement for flicker value.

[0122] The waveform recording module buffers the fourth signal group output by the sampling allocation module, caching one second of sampled values ​​from the seven ADCs according to the configured sampling frequency, for external devices to record waveforms or perform further analysis. To facilitate the use of this chip by external devices, the waveform recording module features a nearly one-second waveform buffer in a circular storage configuration. The circular buffer in the register can buffer 7*256*50 sampled values, used to buffer the waveforms output by the seven ADCs. The pointer register WAVEP indicates the current last buffer position. The waveform recording module is triggered to run once each time the S80 signal group output by the sampling allocation module is updated.

[0123] The timing module provides a time value accurate to microseconds based on the externally provided second pulse and the internal 10MHz signal (1M = 1,000,000). It is equipped with a second accumulation register (TIMS), a microsecond register (TIMUS), and a standard time format register (TM), etc. Figure 12 As shown, the timing module includes: a second counter, a microsecond counter, a timer, and a time format conversion module. The second pulse can originate from the real-time clock (RTC) within the main unit, from the BeiDou / GPS module, or from other precise time synchronization modules. The clock pulse CLK10M originates from the MCU (control module), with an ideal frequency of 10MHz. Each second pulse increments TIMS by 1 and resets TIMUS; each microsecond pulse increments TIMUS by 1. The timer counts the number of CLK10M pulses (CLK10MN) within a single second pulse. Because the crystal oscillation frequency changes with temperature, CLK10MN may be greater than or less than 10,000,000. The timer also outputs relatively uniform, nearly equal-interval microsecond pulses to ensure that the TIMUS value increases to 1,000,000 at equal intervals within a single second pulse, providing a precise time stamp for other modules. The timer dynamically adjusts the interval of the microsecond pulses based on the CLK10MN value to ensure that the error between the microsecond value of each TIMUS and the microsecond value of the actual time is less than 1 / 10M = 0.1 microseconds. The timer's microsecond pulse generator is used to generate microsecond pulses. If CLK10M is an accurate 10MHz, the microsecond pulse generator outputs one microsecond pulse for every 10 CLK10M pulses counted. If CLK10M is slightly faster, it outputs a microsecond pulse when it counts 10 or more pulses; if CLK10M is slightly slower, it outputs a microsecond pulse when it counts 10 or less pulses. Specifically, the number of CLK10M pulses to count for each microsecond pulse is derived using the following formula: assuming CLK10MN = 10M + x, where x is an integer and 1M = 1,000,000, then the number of CLK10M pulses to count for each microsecond pulse is:

[0124]

[0125] However, this value can only be an integer. If only a fixed number is used and the decimal part is ignored, the deviation between the output time and the desired occurrence time of the microsecond pulses will increase as they are continuously output. To ensure uniform microsecond pulse output, the decimal part of the value must also be considered. Therefore, the number of microsecond pulses counted by the microsecond pulse generator CLK10M should be dynamically adjusted, using the following formula:

[0126]

[0127] Where x, n, and k are integers, 10M = 10,000,000, and 10M represents the number of 10 10M pulses corresponding to each microsecond pulse; Calculated as floating-point numbers, this represents the number of CLK10M pulses corresponding to each idealized microsecond pulse; P0 is the number of CLK10M pulses corresponding to the first microsecond pulse, P1 is the number of CLK10M pulses corresponding to the second microsecond pulse, and P... n P is the number of CLK10M pulses corresponding to the nth microsecond pulse. k It is the number of clock pulses corresponding to the (n-1)th microsecond pulse.

[0128] A dual-voltage reference circuit module provides a reference voltage for the analog sampling module. It has two reference voltage circuits, and the MCU firmware can detect a fault in one reference voltage and control the switch to the other. When an ADC reference voltage failure occurs, the reference voltage (normal value is 1.25V) may drop below 1V, causing the ADC to acquire values ​​that are more than 20% higher than normal, rendering it unusable. Therefore, this application designs two reference voltage circuits to provide a reference voltage for the analog sampling module. Figure 13 As shown, when reference voltage VREF1 fails, reference voltage VREF2 can be activated via a switch. Failure monitoring and switching control are implemented through an MCU. The MCU has an internal 14-bit coded SAR-type ADC, whose reference voltage comes from an external step-down regulator LDO, ensuring stability, reliability, and low failure rate. The MCU periodically uses its internal SAR-type ADC to measure reference voltages VREF1 and VREF2, averaging and filtering the conversion values ​​vRef1 and vRef2. When the conversion values ​​differ by a certain threshold (e.g., 1%), the voltage reference closest to 1.25V is activated. To achieve high measurement accuracy, during the production phase of the complete machine using this chip, the calibration parameter groups of each functional module are calibrated separately using both references, and the calibration parameters are switched when switching voltage references. The dual-reference voltage circuit module significantly reduces the failure rate during mass production.

[0129] The power measurement chip provided in this application uses a RISC-V instruction set MCU as its control core. The MCU architecture is as follows: Figure 14As shown, this MCU uses a RISC-V core to connect various components, including: Flash, SRAM, dedicated module registers, interrupt manager, clock circuit module, reset circuit, timer, UART interface, GPIO module, SPI interface, ADC module, watchdog circuit, etc. The MCU's Flash stores the running firmware code and bootloader; SRARM is used as a firmware runtime variable and register for various peripherals. A power-on reset circuit manages the chip's power-on reset; the chip starts working when the voltage is greater than 2.6V and enters a reset state when the voltage is less than 2.5V. The watchdog circuit prevents abnormal firmware operation. The clock circuit module provides the operating clock for the MCU and various dedicated circuit modules. The timer is used for timing and counting. The UART and SPI interfaces are used for interaction between the chip and external devices. The GPIO module is a general-purpose input / output pin interface. The interrupt manager manages and configures interrupts for each module and their interaction with the MCU. The ADC module is a 14-bit multi-channel SAR ADC, with the reference voltage reference serving as the chip's operating power supply. The MCU's firmware includes a Modbus protocol module, providing external devices with interfaces to access the various modules within the chip.

[0130] The MCU communicates with the analog sampling module and power measurement module via SPI or UART interfaces, and accesses them via the Modbus protocol. Regarding register access, the MCU accesses the registers of each module via SPI or UART interfaces using the Modbus communication protocol. This chip acts as an RTU-mode slave, using binary format for data exchange, with a device address of 1. It has a built-in CRC check module that maps the registers of each functional module to various Modbus protocol registers. This functionality is implemented through the MCU's code, allowing flexible access to the registers of each functional module. The MCU's code memory space is designed with a permanent boot loading area to enable remote upgrade functionality. For example, the bootloader functional area is set in the ROM of the boot code. The bootloader runs before the operating system kernel, initializing hardware devices and establishing a memory space mapping to prepare the correct environment for the final call to the operating system kernel. The bootloader is the first piece of code executed after the embedded system is powered on. After completing the initialization of the kernel and related hardware, it loads the operating system image or the embedded application into memory, then jumps to the operating system's space to start the operating system.

[0131] Reference Figure 15The power measurement chip provided in this application requires input of phase A AC voltage, phase B AC voltage, phase C AC voltage, phase A AC current, phase B AC current, phase C AC current, and phase N AC current when used; it also requires an external power supply of 3.3V, a 20MHz crystal, a second pulse, an SPI bus (Modbus communication protocol), and an interrupt indicator.

[0132] The electrical energy measurement chip provided in this application has the following advantages:

[0133] (1) A set of sampling signals with a high update rate is output by a multi-channel Σ-Δ ADC. The sampling signals with a high update rate are resampled by the sampling distribution module to obtain a synchronous sampling signal, ensuring that the sampling rate is synchronized with the AC voltage frequency of the power grid. Based on the synchronous sampling signal, various power quality data can be accurately calculated, providing high-precision power quality data.

[0134] (2) The application-specific integrated circuit (ASIC) is used to calculate the marketing business data, power distribution business data and power quality data of low-voltage distribution transformers, realize high-precision metering of power data, and provide complete three types of business data for low-voltage distribution transformer management, power energy data (positive / reverse reactive full wave / fundamental wave / harmonic power energy), power quality index data, and real-time quantities used in power distribution business.

[0135] (3) The timing module that receives the second pulse marks each data with a precision of 1 microsecond to ensure sampling accuracy and correct the error of the high-frequency clock.

[0136] (4) Transient analysis with multiple thresholds for fine time intervals, with time intervals less than half a cycle, can detect transient changes in a timely manner. The transient analysis module with small intervals for multiple thresholds can provide fine monitoring of transient events.

[0137] (5) The dual reference voltage circuit module can identify the failed reference voltage and switch to the normal reference in time, which greatly reduces the failure rate during batch operation.

[0138] (6) It adopts a RISC-V type MCU as the core, which is open source, secure, and easy to expand; the ROM of the startup code has a bootloader function and the firmware can be upgraded.

[0139] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented using various computer languages.

[0140] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0141] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0142] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0143] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0144] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An energy measurement chip for low-voltage distribution networks, characterized in that, include: The system includes an analog sampling module, a sampling distribution module, an electrical energy measurement module, and a control module. The analog sampling module includes multiple analog-to-digital converters, which are used to acquire three-phase AC voltage analog signals, three-phase AC current analog signals and neutral line AC current analog signals respectively, and output digital sampling signal groups. The sampling allocation module is used to sample the digital sampling signal group output by the analog sampling module and output multiple signal groups with different update rates, wherein the sampling rate of the first signal group is synchronized with the AC voltage frequency of the power grid. The power measurement module includes a power quality module, which is used to calculate power quality data based on the first signal group output by the sampling and distribution module. The sampling allocation module includes: a frequency tracking module, a downsampling module, and multiple signal extraction modules; The frequency tracking module is used to calculate the frequency value of the voltage signal in the digital sampling signal group output by the analog sampling module; The downsampling module is used to use the sinc interpolation method to downsample the digital sampling signal group output by the analog sampling module at an adjustable sampling interval, outputting a first signal group with a sampling rate synchronized with the AC voltage frequency of the power grid and a signal value close to the original signal, and adjusting the sampling interval according to the frequency value output by the frequency tracking module. Each signal extraction module is used to extract and output signals from the digital sampling signal group output by the analog sampling module at a fixed extraction interval. Multiple signal extraction modules have different extraction intervals and output multiple signal groups with different update rates.

2. The power measurement chip for low-voltage distribution networks according to claim 1, characterized in that, The frequency tracking module includes: A low-pass filter is used to reduce voltage signals and voltage fluctuations exceeding a preset frequency in the digital sampling signal group; DC cancellation filters are used to reduce the DC component and voltage fluctuations in the output signal of low-pass filters; Zero-crossing detection circuit is used to detect zero-crossing points in the signal output by the DC cancellation filter; The frequency calculation circuit is used to calculate the duration between consecutive zero crossings and to calculate the frequency value based on the duration between two crossing zero crossings. The phase selector is used to calculate the maximum phase of the effective value of the voltage signal and select the frequency value of that maximum phase for output.

3. The power measurement chip for low-voltage distribution networks according to claim 2, characterized in that, The low-pass filter is a 64th-order FIR digital filter; The low-pass filter obtains and outputs a filtered value by weighting 64 consecutive voltage signal values ​​in the buffer using coefficients.

4. The power measurement chip for low-voltage distribution networks according to claim 3, characterized in that, The DC cancellation filter calculates the average value of the voltage signal cached within the corresponding time period based on the filter value output by the low-pass filter, which is 1.5 times the latest frequency value. The DC cancellation filter value is obtained by subtracting this average value from the frequency value output by the phase selector.

5. The power measurement chip for low-voltage distribution networks according to claim 4, characterized in that, The zero-crossing detection circuit numbers the DC-canceling filter values ​​in natural number order, compares the current DC-canceling filter value with the previous DC-canceling filter value, and if the two change positively or negatively, the current DC-canceling filter value and its number and the previous DC-canceling filter value and its number are input to the frequency calculation circuit.

6. The power measurement chip for low-voltage distribution networks according to claim 5, characterized in that, The frequency calculation circuit buffers four pairs of signal values, which correspond to four consecutive zero-crossing points. It calculates the time interval between the first and third zero-crossing points to obtain the first frequency value, and calculates the time interval between the second and fourth zero-crossing points to obtain the second frequency value. The average of the first and second frequency values ​​is output to the phase selector as the average frequency value.

7. The power measurement chip for low-voltage distribution networks according to claim 6, characterized in that, The phase selector buffers the average frequency value, calculates the effective value of the three-phase voltage signal using the duration corresponding to the previous average frequency value, and outputs the largest effective value among the effective values ​​of the three-phase voltage signal as the final frequency value.

8. The power measurement chip for low-voltage distribution networks according to claim 1, characterized in that, The downsampling module buffers digital sampled signal groups and their corresponding time values. When the downsampling time value T... j Sampling and calculation are performed between the 64th and 65th time values ​​to obtain a downsampled signal. The downsampled time value T is then used. j Increase T1 as the next downsampling time value.

9. The power measurement chip for low-voltage distribution networks according to claim 1, characterized in that, The power quality module includes: a power quality steady-state module and a power quality transient module; The power quality steady-state module is used to calculate the effective values, harmonic values, and power values ​​of the three-phase voltage signal, three-phase current signal, and N-phase current signal based on the first signal group output by the sampling and distribution module. The power quality transient module is used to determine short-term changes in voltage or current based on the effective value obtained from the power quality steady-state module.

10. The power measurement chip for low-voltage distribution networks according to claim 9, characterized in that, The power quality steady-state module includes: an RMS value calculation circuit, a harmonic calculation circuit, and a power calculation circuit.

11. The power measurement chip for low-voltage distribution networks according to claim 10, characterized in that, The effective value calculation circuit counts the synchronous sampling signals in the first input signal group, outputs an instantaneous effective value based on the 256 buffered data values, outputs a half-wave effective value when the count reaches 128, outputs a full-wave effective value when the count reaches 256, calculates a 10-cycle effective value based on the 10 buffered full-cycle effective values, and calculates a 150-cycle effective value based on the 15 buffered 10-cycle effective values.

12. The power measurement chip for low-voltage distribution networks according to claim 10, characterized in that, The harmonic calculation circuit performs a fast Fourier transform on 256 consecutive synchronously sampled signals in the first input signal group to obtain 50 harmonic values, performs effective value aggregation on 10 consecutive non-overlapping harmonic values ​​to obtain 10-cycle harmonic values, and performs effective value aggregation on 15 consecutive non-overlapping 10-cycle harmonic values ​​to obtain 150-cycle harmonic values.

13. The power measurement chip for low-voltage distribution networks according to claim 10, characterized in that, The power calculation circuit includes: a power calculation circuit, a powerless calculation circuit, and an apparent power calculation circuit.

14. The power measurement chip for low-voltage distribution networks according to claim 13, characterized in that, The power calculation circuit multiplies the voltage signal and current signal in the first input signal group to obtain the instantaneous fluctuation power value, obtains the physical unit power value based on the instantaneous fluctuation power value, and inputs the physical unit power value into a low-pass filter to obtain the power value of this cycle; it sums 10 consecutive non-overlapping power values ​​of this cycle to obtain the 10-cycle power value, and sums 15 consecutive non-overlapping 10-cycle power values ​​to obtain the 150-cycle power value.

15. The power measurement chip for low-voltage distribution networks according to claim 13, characterized in that, The power loss calculation circuit uses a phase shifter to perform a Hilbert transform on the voltage signal in the first input signal group, shifting each harmonic of the voltage signal by 90 degrees. The phase-shifted voltage signal is multiplied by the current signal to obtain the instantaneous fluctuating power loss value. The physical unit power value is obtained based on the instantaneous fluctuating power loss value. The physical unit power value is input into a low-pass filter to obtain the current week power loss value. Ten consecutive non-overlapping current week power loss values ​​are summed to obtain a 10-cycle power loss value. Fifteen consecutive non-overlapping 10-cycle power loss values ​​are summed to obtain a 150-cycle power loss value.

16. The power measurement chip for low-voltage distribution networks according to claim 9, characterized in that, The power quality transient module is equipped with a voltage swell threshold register, a voltage swell delay register, a voltage slump threshold register, a voltage slump delay register, a flag register, and a timer; When the instantaneous effective value is greater than the voltage spur threshold register value, the timer starts counting. When the timer value is greater than the voltage spur delay register value, the flag register is set and the time value at this moment is recorded. When the instantaneous effective value is less than the voltage spur threshold register value, the timer and flag register are cleared.

17. The power measurement chip for low-voltage distribution networks according to claim 9, characterized in that, The power quality module also includes: a voltage fluctuation module; The voltage fluctuation module is used to detect voltage fluctuations per unit time based on the effective value obtained from the power quality steady-state module.

18. The power measurement chip for low-voltage distribution networks according to claim 17, characterized in that, The voltage fluctuation module calculates the absolute value of the difference between two consecutive voltage half-wave effective values, compares this absolute value with a preset voltage fluctuation limit, and obtains the voltage fluctuation value.

19. The power measurement chip for low-voltage distribution networks according to claim 9, characterized in that, The power quality module also includes: a power distribution service module; The power distribution service module is used to calculate power distribution service data per unit time based on the effective value obtained from the power quality steady-state module.

20. The power measurement chip for low-voltage distribution networks according to claim 1, characterized in that, The sampling allocation module outputs multiple signal groups with different update rates, including a second signal group, a third signal group, and a fourth signal group. The electrical energy measurement module also includes: an electrical energy module and a voltage flicker module; The power module is used to measure power based on the second signal group output by the sampling and distribution module; The voltage flicker module is used to detect short-time flicker and long-time flicker of the voltage signal in the third signal group output by the sampling and distribution module.

21. The power measurement chip for low-voltage distribution networks according to claim 20, characterized in that, The electrical energy module includes: An active energy calculation circuit is used to calculate the active energy of the three-phase voltage / current based on the second signal group. The reactive energy calculation circuit is used to calculate the reactive energy of the three-phase voltage / current based on the second signal group. Apparent energy calculation circuit, used to calculate the apparent energy of three-phase voltage / current based on the calculated active and reactive energy.

22. The power measurement chip for low-voltage distribution networks according to claim 20, characterized in that, The voltage flicker module includes: a level matching module, a square detection module, a bandpass weighting module, a square smoothing module, and a hierarchical statistics module; The level matching module filters the half-wave RMS value of the voltage signal in the third signal group, divides the voltage signal value by the half-wave RMS value, and outputs it to the square detection module. After passing through the bandpass weighting module and the square smoothing module, it is output to the hierarchical statistics module. The hierarchical statistics module performs hierarchical calculations to obtain the short-time flicker value.

23. The power measurement chip for low-voltage distribution networks according to claim 20, characterized in that, The electrical energy measurement module also includes: a waveform recording module; The waveform recording module is used to buffer the fourth signal group output by the sampling allocation module at a configured sampling frequency.

24. The power measurement chip for low-voltage distribution networks according to claim 23, characterized in that, Also includes: Timing module; The timing module is used to provide time accurate to microseconds for the power quality module, power energy module, voltage flicker module, and waveform recording module.

25. The power measurement chip for low-voltage distribution networks according to claim 24, characterized in that, The timing module includes: a second counter, a microsecond counter, a timer, and a time format conversion module; The timer is used to count the number of clock pulses during a one-second pulse period, output uniformly spaced microsecond pulses, and dynamically adjust the interval of the microsecond pulses according to the number of clock pulses during a one-second pulse period to reduce the error between the value of the microsecond counter and the actual microsecond value.

26. The power measurement chip for low-voltage distribution networks according to claim 25, characterized in that, The formula for dynamically adjusting the interval of the microsecond pulse is: ； in, x, n, k It is an integer, 10M = 10,000,000, 10M represents the number of 10 10M pulses corresponding to each microsecond pulse; Calculated as a floating-point number, P0 represents the number of 10M pulses corresponding to each idealized microsecond pulse; P0 represents the number of 10M pulses corresponding to the first microsecond pulse. n P represents the number of clock pulses corresponding to the nth microsecond pulse. k This represents the number of clock pulses corresponding to the (n-1)th microsecond pulse.

27. The power measurement chip for low-voltage distribution networks according to claim 1, characterized in that, Also includes: Dual voltage reference module; The dual voltage reference module is used to provide two voltage references for the analog sampling module.

28. The power measurement chip for low-voltage distribution networks according to claim 1, characterized in that, The control module is a RISC-V instruction set architecture MCU that accesses the ADC module and the power measurement module via the Modbus protocol.

29. The power measurement chip for low-voltage distribution networks according to claim 28, characterized in that, The MCU's code memory includes a permanently stored boot loading area.

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