An in-vehicle chip test system and method for bus-type fault injection

Abstract

The present invention relates to the technical field of automotive chip testing, and discloses a bus-type fault injection automotive chip testing system and method, including a chip under test, which is an automotive chip to be tested. There are several pin angles on the chip under test. The automotive chip testing system further includes: a control unit, a DA digital-to-analog conversion unit, an EMC interference injection unit, a logic interlock unit, a bus, a switch selection circuit unit, and a chip status monitoring unit. The control unit is respectively connected to the DA digital-to-analog conversion unit, the EMC interference injection unit, the logic interlock unit, and the switch selection circuit unit. The DA digital-to-analog conversion unit and the EMC interference injection unit are respectively connected to the bus, and the bus is connected to the pin angles of the chip under test. Through the bus-type fault source injection method, the real simulated physical fault source is injected onto the pin angles of the chip under test, and it also provides strong support for evaluating the functions and performance of the chip under test.

Description

Technical Field

[0001] The present invention relates to the technical field of automotive-grade chip testing, and particularly to an automotive-grade chip testing system and method with bus-type fault injection. Background Art

[0002] Automotive-grade chips refer to chips whose technical standards reach the automotive grade and can be applied to automotive control. Most chip testing methods are for testing their own functions, but there is a lack of effective monitoring means for the performance of chips in complex noise environments and fault environments. Fault injection covers various existing electrical fault conditions and can implement the complete functional circuits of the chips. The external system monitors the specific functions of the chips to realize the online evaluation of the test results.

[0003] In the existing chip fault injection testing, most are software fault simulation fault injection, including fault simulations such as JTAG. This simulation method not only limits the chips themselves to having software programming functions, but also limits the chip types and chip functions. Moreover, there is a lack of existing testing methods for injecting real physical fault signals into the hardware pin angles of automotive-grade chips themselves. Summary of the Invention

[0004] In order to solve the problem that the functional performance during the fault injection testing of automotive-grade chips in the prior art is restricted by the fault injection method, the present invention provides an automotive-grade chip testing system and method with bus-type fault injection.

[0005] The technical solution of the present invention is as follows:

[0006] An automotive-grade chip testing system with bus-type fault injection includes a chip under test, where the chip under test is an automotive-grade chip to be tested, and there are several pin angles on the chip under test. The automotive-grade chip testing system further includes:

[0007] A control unit, a DA digital-to-analog conversion unit, an EMC interference injection unit, a logic interlock unit, a bus, a switch selection circuit unit, and a chip status monitoring unit. The control unit is respectively connected to the DA digital-to-analog conversion unit, the EMC interference injection unit, the logic interlock unit, and the switch selection circuit unit. The DA digital-to-analog conversion unit and the EMC interference injection unit are respectively connected to the bus. The bus is connected to the pin of the chip under test. The logic interlock unit controls the connection between the DA digital-to-analog conversion unit and the bus. The switch selection circuit unit controls the connection between the bus and the pin of the chip under test. The DA digital-to-analog conversion unit receives the control signal sent by the control unit to form a fault source, and the DA digital-to-analog conversion unit injects the fault source into the pin of the chip under test through the bus. The chip under test is connected to the chip status monitoring unit, and the chip status monitoring unit is connected to the control unit. The chip status monitoring unit collects the test results of the chip under test in the state of injecting the fault source and sends them to the control unit.

[0008] Further, the automotive chip test system further includes a chip peripheral real function load circuit unit. The chip peripheral real function load circuit unit is respectively connected to the chip under test and the chip status monitoring unit. The chip under test exports the operation condition in the state of injecting the fault source to the chip status monitoring unit through the chip peripheral real function load circuit unit, and the chip status monitoring unit obtains the test results according to the operation condition of the chip under test in the state of injecting the fault source.

[0009] Further, the automotive chip test system further includes a system power supply. The system power supply is respectively connected to the chip under test and the control unit, and the system power supply provides systematic power for the control unit and the chip under test.

[0010] Further, the fault sources formed by the DA digital-to-analog conversion unit include: 0V potential, power supply VCC, adjustable DC level, PWM pulse width modulation waveform, single pulse waveform, and arbitrary waveform.

[0011] Further, a switch is provided on the connection line between each fault source and the bus, and any one of the switches is controlled to be closed and opened through the logic interlock unit. A switch is provided on the connection line between the EMC interference injection unit and the bus, and the EMC interference injection unit controls the closing and opening of the switch on the connection line between it and the bus through the control unit.

[0012] Further, a switch is provided on the connection line between the pin of each chip under test and the bus, and any one of the switches is controlled to be closed and opened through the switch selection circuit unit.

[0013] Further, the control unit is a CPU control unit or an FPGA control unit.

[0014] Further, the EMC harassment injection unit generates one or more noise sources among load dump, conduction, and radiation.

[0015] The present invention also provides a method for testing automotive-grade chips with bus-type fault injection, which is implemented by the automotive-grade chip testing system described in any one of the above, and includes the following steps:

[0016] S1: The control unit controls the switches on the connection line of the bus to which at least one pin of the chip under test is connected through the switch selection circuit unit to be closed, so that the pin of the chip under test with the switch on the connection line closed is connected to the bus;

[0017] S2: The control unit calculates the digital signal of the physical waveform according to the test requirements, and the digital signal is converted into the actual physical fault source waveform through the DA digital-to-analog conversion unit to form a fault source;

[0018] S3: The control unit drives the logic interlock unit to close the switch on the connection line between the fault source to be simulated and the bus according to the function of the pin of the chip under test, and the fault source is injected into the pin of the chip under test in S1 through the bus;

[0019] S4: The chip status monitoring unit collects the operation status of the chip under test in the fault source injection state through the chip peripheral real function load circuit unit and obtains the test result;

[0020] S5: The chip status monitoring unit determines whether the function of the pin of the chip under test is abnormal according to the test result. If it is normal, it is transmitted to the control unit to form a record and returns to S1. If it is abnormal, a fault record and an alarm are formed and output to the control unit for recording and then return to S1;

[0021] S6: After the injection of the fault source to be tested for the chip under test is completed, the test process ends.

[0022] Further, the S5 includes:

[0023] The control unit pre-sets the correct function state of the chip under test according to the function definition of the chip under test. The chip status monitoring unit determines whether it is normal by comparing whether the pre-set correct function state of the chip under test is consistent with the test result. If they are consistent, it is normal. If they are not consistent, it is abnormal.

[0024] The beneficial effects of the present invention at least include:

[0025] (1) By means of bus - type fault source injection, a physically simulated real - fault source is injected into the pin of the chip under test, which not only greatly increases the number of pins of the chip under test and the number of fault sources connected, realizes the application of multiple fault sources to a single pin of the chip under test, and the application of the same fault source to multiple pins of the chip under test at the same time, but also provides strong support for evaluating the function and performance of the chip under test;

[0026] (2) The operation state of the chip under test is collected in real - time by the chip state monitoring unit to observe the operation of the chip under test when a fault source is applied, and by monitoring the circuits and pins that complete the functions of the chip under test itself and its own peripheral circuits, it is determined whether the function of the chip under test fails, ensuring the correctness of the test results. Description of the Drawings

[0027] Figure 1 It is a structural schematic block diagram of a vehicle - specification chip test system with bus - type fault injection provided by the present invention.

[0028] Figure 2 It is a flowchart schematic diagram of a vehicle - specification chip test method with bus - type fault injection provided by the present invention. Detailed Embodiments

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0030] Embodiment 1

[0031] Combined with Figure 1 As shown, this embodiment provides a vehicle - specification chip test system with bus - type fault injection, including a chip under test, where the chip under test is a vehicle - specification chip to be tested, and there are several pins on the chip under test. The vehicle - specification chip test system further includes:

[0032] A control unit, a DA digital-to-analog conversion unit, an EMC interference injection unit, a logic interlock unit, a bus, a switch selection circuit unit, and a chip status monitoring unit. The control unit is respectively connected to the DA digital-to-analog conversion unit, the EMC interference injection unit, the logic interlock unit, and the switch selection circuit unit. The DA digital-to-analog conversion unit and the EMC interference injection unit are respectively connected to the bus. The bus is connected to the pin of the chip under test. The logic interlock unit controls the connection between the DA digital-to-analog conversion unit and the bus. The switch selection circuit unit controls the connection between the bus and the pin of the chip under test. The DA digital-to-analog conversion unit receives the control signal sent by the control unit to form a fault source, and the DA digital-to-analog conversion unit injects the fault source into the pin of the chip under test through the bus. The chip under test is connected to the chip status monitoring unit, and the chip status monitoring unit is connected to the control unit. The chip status monitoring unit collects the test results of the chip under test in the state of injecting the fault source and sends them to the control unit.

[0033] Further, the vehicle specification chip test system further includes a chip peripheral real function load circuit unit. The chip peripheral real function load circuit unit is respectively connected to the chip under test and the chip status monitoring unit. The chip under test exports the operation condition of the chip under test in the state of injecting the fault source to the chip status monitoring unit through the chip peripheral real function load circuit unit, and the chip status monitoring unit obtains the test results according to the operation condition of the chip under test in the state of injecting the fault source.

[0034] The chip status monitoring unit is based on the faulty pin of the chip under test or the function of the chip under test itself to obtain the operation condition of the chip under test in the state of injecting the fault source, and uploads the monitoring result to the control unit. The chip status monitoring unit monitors the functional circuit of the chip under test, analyzes and conducts targeted tests on the peripheral functional circuit formed by the chip under test, and can also directly monitor the pins of the chip under test.

[0035] The chip status monitoring unit monitors the communication function, acquisition function, output function, configuration function, etc. of all the actual functions of the chip under test; and monitors the functional status, alarm status, communication status, signal quality, etc. of the chip to obtain the moment of fault injection, the real operation status of the chip, and the working status of its peripheral circuit.

[0036] For example: If the functional pin of the chip under test is for communication function, the communication function is verified by the status monitoring circuit to complete the corresponding communication function monitoring; or if the functional pin of the chip under test is for signal output, the status monitoring circuit collects the frequency and duty cycle of the PWM to evaluate the output chip; or if the functional pin angle of the chip under test is for signal input, the input signal processing result is monitored by other functional output pins that can reflect the input status.

[0037] The real functional load circuit unit around the chip is designed differently according to the different functions of the chip under test, and there is no restriction on the type of the chip under test, which is determined by the function of the chip under test itself.

[0038] The chip status monitoring unit can collect the status of the chip under test in real time to observe the operation of the chip under test when the fault source is applied. By monitoring the circuits, pins, and its own peripheral circuits of the chip under test to complete its own functions, it is determined whether the function of the chip under test fails, ensuring the correctness of the monitoring results. And in addition to testing the functions of the chip under test itself, the performance of the peripheral circuits of the chip under test in a fault environment is also verified.

[0039] Further, the vehicle specification chip test system further includes a system power supply, and the system power supply is respectively connected to the chip under test and the control unit, and the system power supply provides systematic power for the control unit and the chip under test.

[0040] The power supplies that the system power supply can provide include but are not limited to the following specifications: 48V power supply, 24V power supply, 12V power supply, 9V power supply, 5V power supply, 3.3V power supply, 3V power supply, 2.5V power supply, 1.8V power supply, 1.2 power supply, 1.1V power supply, 0.9V power supply, 0.8V power supply.

[0041] Further, the fault sources formed by the DA digital-to-analog conversion unit include: 0V potential, power supply VCC, adjustable DC level, PWM pulse width modulation waveform, single pulse waveform, and arbitrary waveform.

[0042] Further, a switch is provided on the connection line of each fault source to the bus, and any one of the switches is controlled to be closed and opened by the logic interlock unit. A switch is provided on the connection line of the EMC harassment injection unit to the bus, and the EMC harassment injection unit controls the closing and opening of the switch on the connection line between it and the bus through the control unit.

[0043] The switches on the connection lines between the fault sources and the bus are switch A, switch B, switch C, switch D, switch E, and switch F respectively. They are fault source input selection switches. The control unit transmits control signals to the DA digital-to-analog conversion unit. The DA digital-to-analog conversion unit converts the control signals into actual physical waveforms through an amplifier circuit, a filter circuit, etc. and outputs them to form corresponding fault sources. The control unit drives the switches connected to any fault source to close or open through the control logic interlock unit. When the switch is closed, the fault source is directly connected to the bus. When the switch is open, the fault source is disconnected from the bus.

[0044] The internal of the logic interlock unit has logic interlock functions and capabilities to ensure that only one type of fault source appears on the bus at the same time and prevent interference between fault sources.

[0045] Furthermore, a switch is provided on the connection line between each pin of the measured chip and the bus, and any one of the switches is controlled to close and open through the switch selection circuit unit.

[0046] The control unit selects the pin that needs to inject the fault source according to the actual functional state of the pin of the measured chip, and drives at least one of switch 1, switch 2, switch 3, ……, switch n to close or open through the switch selection circuit unit. When the switch is closed, the fault source is injected into the pin of the measured chip. When the switch is open, the injection of the fault source into the pin of the measured chip is disconnected.

[0047] The control unit can inject fault sources into the pins of all measured chips in a polling manner, or according to requirements, select to open the switch of a single pin of the measured chip to test different types of fault sources for a single pin, or open the switches of multiple pins of the measured chip to simultaneously inject the same type of fault source into multiple pins of the measured chip for testing.

[0048] Furthermore, the control unit is a CPU control unit or an FPGA control unit.

[0049] The CPU control unit or the FPGA control unit is the control unit that provides decisions for the entire test system, provides selection control for fault source injection, forms corresponding fault sources by transmitting control signals to the DA digital-to-analog conversion unit; drives through a logic interlock unit to select the fault source connected to the bus; then controls the closing of the electronic switch through the switch selection unit, that is, controls the closing of the switch on the connection line between the bus and the pin of the measured chip, and determines which pin of the measured chip to inject the fault source; finally, through the chip status monitoring unit, monitors the preset normal functional state of the measured chip itself and the operating conditions under the state of injecting the fault source, and after comparison, judges the fault situation and obtains the test result.

[0050] Further, the EMC harassment injection unit generates one or more noise sources among load dump, conduction, and radiation.

[0051] The EMC harassment injection unit is controlled by a CPU control unit or an FPGA control unit.

[0052] The chip under test is a device under test, an integrated circuit with specific functions, and a verification circuit for the functions of the chip under test is designed, that is, a real functional load circuit unit around the chip.

[0053] Embodiment 2

[0054] The present invention also provides a vehicle - specification chip testing method for bus - type fault injection, which is implemented by the vehicle - specification chip testing system described in any one of Embodiments 1, and includes the following steps:

[0055] S1: The control unit controls the switches on the connection line where at least one pin of the chip under test is connected to the bus through the switch selection circuit unit to close, so that the pin of the chip under test where the switch on the connection line is closed is connected to the bus;

[0056] S2: The control unit calculates the digital signal of the physical waveform according to the test requirements, and the digital signal is converted into the actual physical fault source waveform through the DA digital - to - analog conversion unit to form a fault source;

[0057] S3: According to the function of the pin of the chip under test, the control unit drives the logic interlock unit to close the switch on the connection line where the fault source to be simulated is connected to the bus, and the fault source is injected into the pin of the chip under test in S1 through the bus;

[0058] S4: The chip status monitoring unit collects the operation conditions of the chip under test in the state of fault source injection through the real functional load circuit unit around the chip and obtains the test result;

[0059] S5: The chip status monitoring unit determines whether the function of the pin of the chip under test is abnormal according to the test result. If it is normal, it is transmitted to the control unit to form a record and returns to S1. If it is abnormal, a fault record and an alarm are formed and output to the control unit for recording and then return to S1;

[0060] When the chip status monitoring unit detects a fault state, it will input the fault state to the CPU / FPGA control unit to form a corresponding fault record and an alarm output.

[0061] When the chip status monitoring unit does not detect a fault state, it indicates that this fault injection has no impact on the function of the chip under test. The CPU / FPGA control unit forms a record and switches to the next fault injection detection.

[0062] S6: After injecting all the fault sources to be tested in the chip under test, end the test process.

[0063] Further, S5 includes:

[0064] The control unit pre - sets the correct functional state of the chip under test according to the functional definition of the chip under test. The chip state monitoring unit determines whether it is normal by comparing whether the pre - set correct functional state of the chip under test matches the test result. If they match, it is normal; if not, it is abnormal.

[0065] The control unit pre - sets the definitions of signals such as the correct functional state and fault state of the chip under test according to the functional definition of the chip under test. When the test result feedback does not match the pre - set definition, it is determined that the function of the chip under test is abnormal in the state of injecting this fault source; otherwise, it is normal.

[0066] The bus - type fault injection mode provided by the present invention can greatly increase the number of pin angles of the chip under test and the number of fault source accesses.

[0067] The in - vehicle chip test system with bus - type fault injection provided by the present invention can apply multiple fault sources to a single pin angle of the chip under test multiple times according to requirements, or apply the same fault source to multiple pin angles at the same time.

[0068] The above are only the embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. All equivalent structural or equivalent process transformations made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are equally included in the patent protection scope of the present invention.

Claims

1. A vehicle - specification chip test system for bus - type fault injection, including a chip under test, where the chip under test is a vehicle - specification chip to be tested, and there are a number of pin - angles on the chip under test, characterized in that: The in-vehicle chip test system further includes: a control unit, a DA digital-to-analog conversion unit, an EMC interference injection unit, a logic interlock unit, a bus, a switch selection circuit unit, and a chip status monitoring unit. The control unit is respectively connected to the DA digital-to-analog conversion unit, the EMC interference injection unit, the logic interlock unit, and the switch selection circuit unit. The DA digital-to-analog conversion unit and the EMC interference injection unit are respectively connected to the bus. The bus is connected to the pin of the chip under test. The logic interlock unit controls the connection between the DA digital-to-analog conversion unit and the bus. The switch selection circuit unit controls the connection between the bus and the pin of the chip under test. The DA digital-to-analog conversion unit receives the control signal sent by the control unit to form a fault source, and the DA digital-to-analog conversion unit injects the fault source into the pin of the chip under test through the bus. The logic interlock unit has a logic interlock function and ability inside, ensuring that only one fault source appears on the bus at the same time to prevent interference between fault sources. The control unit selects the pin that needs to inject the fault source according to the actual functional state of the pin of the chip under test, and drives at least one switch to close or open through the switch selection circuit unit. When the switch is closed, the fault source is injected into the pin of the chip under test. When the switch is open, the injection of the fault source into the pin of the chip under test is disconnected. The control unit can inject the fault source into all the pins of the chips under test in a polling manner, or select to open the switch of a single pin of the chip under test to test different types of fault sources for a single pin, or open the switches of multiple pins of the chip under test to inject the same type of fault source into multiple pins of the chip under test at the same time for testing. The chip under test is connected to the chip status monitoring unit, and the chip status monitoring unit is connected to the control unit. The chip status monitoring unit collects the test results of the chip under test in the state of injecting the fault source and sends them to the control unit. The chip status monitoring unit obtains the operation situation of the chip under test in the state of injecting the fault source based on the faulty pin of the chip under test or the function of the chip under test itself, and uploads the monitoring results to the control unit. The chip status monitoring unit monitors the functional circuit of the chip under test, analyzes and conducts targeted tests on the peripheral functional circuit formed by the chip under test, or directly monitors the pins of the chip under test. The chip status monitoring unit monitors the communication function, acquisition function, output function, and configuration function of the chip under test; and monitors the functional state, alarm state, communication state, and signal quality of the chip to obtain the moment of fault injection, the true operating state of the chip, and the working state of its peripheral circuit.

2. The vehicle - specification chip test system for bus - type fault injection according to claim 1, characterized in that: The vehicle - specification chip testing system further includes a real - function load circuit unit for the chip periphery. The real - function load circuit unit for the chip periphery is respectively connected to the chip under test and the chip status monitoring unit. The chip under test exports the operation condition of the chip under test in the state of injecting a fault source to the chip status monitoring unit through the real - function load circuit unit for the chip periphery, and the chip status monitoring unit obtains the test result according to the operation condition of the chip under test in the state of injecting a fault source.

3. A vehicle specification chip test system for bus - type fault injection according to claim 1, characterized in that: The vehicle - specification chip testing system further includes a system power supply. The system power supply is respectively connected to the chip under test and the control unit, and the system power supply provides systematic power for the control unit and the chip under test.

4. A vehicle specification chip test system for bus - type fault injection according to claim 1, characterized in that: The fault sources formed by the DA digital - to - analog conversion unit include: 0V potential, power supply VCC, adjustable DC level, PWM pulse - width modulation waveform, single - pulse waveform, and arbitrary waveform.

5. A vehicle - specification chip test system for bus - type fault injection according to claim 4, characterized in that: A switch is arranged on the connection line between each fault source and the bus. Any one of the switches is controlled to be closed and opened by the logic interlock unit. A switch is arranged on the connection line between the EMC harassment injection unit and the bus, and the EMC harassment injection unit controls the closing and opening of the switch on the connection line between it and the bus through the control unit.

6. The vehicle - specification chip test system for bus - type fault injection according to claim 1, wherein: A switch is arranged on the connection line between the pin of each chip under test and the bus. Any one of the switches is controlled to be closed and opened by the switch selection circuit unit.

7. The vehicle specification chip test system for bus-type fault injection according to claim 1, characterized in that: The control unit is a CPU control unit or an FPGA control unit.

8. A vehicle specification chip test system for bus - type fault injection according to claim 1, characterized in that: The EMC harassment injection unit generates one or more noise sources of load - dump, conduction, or radiation.

9. A method for testing automotive-grade chips with bus-based fault injection, which is implemented through the automotive-grade chip testing system according to any one of the above claims 1-8, characterized in that: It includes the following steps: S1: The control unit controls the switch on the connection line where at least one pin of the chip under test is connected to the bus through the switch selection circuit unit to be closed, so that the pin of the chip under test whose switch on the connection line is closed is connected to the bus. S2: The control unit calculates the digital signal of the physical waveform according to the test requirements, and the digital signal is converted into the actual physical fault - source waveform through the DA digital - to - analog conversion unit to form a fault source. S3: The control unit drives the logic interlock unit to access the switch on the connection line between the fault source to be simulated and the bus to be closed according to the function of the pin of the chip under test, and the fault source is injected into the pin of the chip under test in S1 through the bus. S4: The chip status monitoring unit collects the operation condition of the chip under test in the state of fault - source injection through the real - function load circuit unit for the chip periphery and obtains the test result. S5: The chip status monitoring unit judges whether the function of the pin of the chip under test is abnormal according to the test result. If it is normal, it is transmitted to the control unit to form a record and returns to S1. If it is abnormal, a fault record and an alarm are output to the control unit for recording and then return to S1. S6: After injecting all the fault sources that the chip under test needs to be tested, the test process ends.

10. The vehicle - specification chip testing method for bus - type fault injection according to claim 9, wherein: The S5 includes: The control unit pre-sets the correct functional state of the chip under test according to the functional definition of the chip under test. The chip state monitoring unit determines whether it is normal by comparing whether the pre-set correct functional state of the chip under test is consistent with the test result. If they are consistent, it is normal; if not, it is abnormal.

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