A slow start circuit for LDO and LDO circuit

Abstract

The present invention provides a slow-start circuit for LDO and an LDO circuit, belonging to the field of integrated circuit technology, comprising: an energy storage element; a feedback branch connected between a bias power supply and a first node, with a control end of the feedback branch connected to the first node; a charging branch, an amplifier branch, a buffer branch, and a switch control circuit provided between the bias power supply and a ground terminal, with the control end of the charging branch connected to the first node; the control end of the buffer branch connected to the output of the amplifier branch, with the output end of the buffer branch connected to the gate of a power regulating tube; a switch control circuit comprising: a switch branch connected between a second node and the ground terminal, with the second node connected to the control end of the amplifier branch; a control branch connected between the bias power supply and the second node, with the control end of the control branch connected to the first node. Beneficial effect: The present invention can effectively solve the problem of instantaneous overshoot of the LDO voltage upon power-on while achieving rapid power-on of the LDO.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a slow-start circuit applied to an LDO and an LDO circuit. Background Art

[0002] With the continuous development of electronic technology, especially the emergence of 5G and artificial intelligence technologies, mobile phones, PDAs, automotive electronics, and other portable smart products have higher speed requirements. Power supplies play a vital role in these portable electronic products, and their performance, size, and cost are also changing and improving rapidly. As a result, power management ICs are facing higher requirements in terms of powerful functional modules, high speed, high stability, and intelligence.

[0003] A low dropout regulator (LDO) uses a transistor or field-effect transistor (FET) operating in its saturation region to subtract excess voltage from the applied input voltage to produce a regulated output voltage. LDOs are widely used in portable electronic products due to their low noise, low power consumption, and simple structure.

[0004] To meet the demands of diverse loads, existing LDOs are constantly facing new challenges. For example, to meet the response speed requirements of certain loads, LDO power supplies must power up quickly. However, during this rapid power-up, current overshoot may occur. This overshoot can affect the load's functional behavior and even cause chip failure. To address these issues, the present invention proposes a slow-start circuit and LDO circuit for LDOs to meet practical application requirements. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a slow start circuit and an LDO circuit applied to an LDO, which can not only realize fast power-on of the LDO but also avoid the overshoot problem.

[0006] The technical problem solved by the present invention can be achieved by adopting the following technical solution: A soft start circuit for LDO, comprising: a power adjustment tube, wherein the source and drain of the power adjustment tube are connected between an input terminal and an output terminal; an energy storage element, connected between a first node and a ground terminal; a feedback branch, connected between a bias power supply and the first node, wherein the control end of the feedback branch is connected to the first node to form a positive feedback loop; a charging branch is provided between the bias power supply and the ground terminal, wherein the control end of the charging branch is connected to the first node to control the charging branch to charge the energy storage element; An amplifier stage branch and a buffer stage branch, wherein the control end of the buffer stage branch is connected to the output of the amplifier stage branch, and the output end of the buffer stage branch is connected to the gate of a power adjustment tube; a switch control circuit, comprising: a switch branch connected between a second node and the ground end, the second node being connected to the control end of the amplifier stage branch for controlling the opening or closing of the amplifier stage branch; and a control branch connected between the bias power supply and the second node, the control end of the control branch being connected to the first node for controlling the on-off of the control branch according to the voltage of the first node, thereby controlling the voltage of the second node.

[0007] Preferably, the feedback branch comprises: a first PMOS transistor (PM1), wherein the source of the first PMOS transistor (PM1) is connected to the bias power supply, the gate of the first PMOS transistor (PM1) is connected to the first node, and the drain of the first PMOS transistor (PM1) is connected to the input end of a first inverter (INV1); a second PMOS transistor (PM2), wherein the source of the second PMOS transistor (PM2) is connected to the bias power supply, the gate of the second PMOS transistor (PM2) is connected to the output end of a second inverter (INV2), the input end of the second inverter (INV2) is connected to the output end of the first inverter (INV1), and the drain of the second PMOS transistor (PM2) is connected to the first node; and a current comparison circuit, for comparing a current flowing through the first PMOS transistor (PM1) with a reference current generated by a current mirror circuit, and outputting the comparison result to the input end of the first inverter (INV1).

[0008] Preferably, the current mirror circuit comprises: a first NMOS transistor (NM1), wherein the gate of the first NMOS transistor (NM1) is connected to a first bias voltage, and the drain of the first NMOS transistor (NM1) is connected to the drain of the first PMOS transistor (PM1); and a second NMOS transistor (NM2), wherein the gate of the second NMOS transistor (NM2) is connected to a second bias voltage, the drain of the second NMOS transistor (NM2) is connected to the source of the first NMOS transistor (NM1), and the source of the second NMOS transistor (NM2) is grounded.

[0009] Preferably, the charging branch comprises: a first transistor (Q1), the base of the first transistor (Q1) being connected to the first node, and the collector of the first transistor (Q1) being grounded; a third PMOS transistor (PM3), the source of the third PMOS transistor (PM3) being connected to the bias power supply, the gate of the third PMOS transistor (PM3) being connected to a third bias voltage, and the drain of the third PMOS transistor (PM3) being connected to the emitter of the first transistor (Q1).

[0010] Preferably, the third PMOS transistor (PM3) includes one or more third PMOS transistors, and the one or more third PMOS transistors can be connected between the bias power supply and the emitter of the first transistor in a switchable manner.

[0011] Preferably, the switch control circuit comprises: a third NMOS transistor (NM3), the gate of the third NMOS transistor (NM3) being connected to an enable signal, the drain of the third NMOS transistor (NM3) being connected to the second node, and the source of the third NMOS transistor (NM3) being grounded; a fifth PMOS transistor (PM5), the gate of the fifth PMOS transistor (PM5) being connected to the first node, and the drain of the fifth PMOS transistor (PM5) being connected to the second node; and a fourth PMOS transistor (PM4), the gate of the fourth PMOS transistor (PM4) being connected to a fourth bias voltage, the source of the fourth PMOS transistor (PM4) being connected to the bias power supply, and the drain of the fourth PMOS transistor (PM4) being connected to the source of the fifth PMOS transistor (PM5).

[0012] Preferably, the amplifier stage branch comprises: a fourth NMOS transistor (NM4), the gate of the fourth NMOS transistor (NM4) being respectively connected to an error amplifier output voltage EA_OUT and the drain of the fifth PMOS transistor (PM5), and the source of the fourth NMOS transistor (NM4) being grounded; and a sixth PMOS transistor (PM6), the gate of the sixth PMOS transistor (PM6) being connected to the fourth bias voltage, the source of the sixth PMOS transistor (PM6) being connected to the bias power supply, and the drain of the sixth PMOS transistor (PM6) being connected to the drain of the fourth NMOS transistor (NM4), for providing a driving current for the fourth NMOS transistor (NM4).

[0013] Preferably, the buffer stage branch comprises: a seventh PMOS tube (PM7), the gate of the seventh PMOS tube (PM7) being connected to the drain of the sixth PMOS tube (PM6), the drain of the seventh PMOS tube (PM7) being connected to the ground terminal via a first resistor, and the source of the seventh PMOS tube (PM7) being connected to the gate of the power adjustment tube; and an eighth PMOS tube (PM8), the gate of the eighth PMOS tube (PM8) being connected to a fifth bias voltage, the source of the eighth PMOS tube (PM8) being connected to the bias power supply, and the drain of the eighth PMOS tube (PM8) being connected to the source of the seventh PMOS tube (PM7).

[0014] Preferably, the energy storage element is a capacitor.

[0015] The present invention also provides an LDO circuit, comprising the above-mentioned slow start circuit.

[0016] The advantages or beneficial effects of the technical solution of the present invention are as follows: the present invention utilizes a charging branch to charge the energy storage element; before the LDO circuit is started, the first node is at a low potential, the energy storage element starts to charge, and at the same time, the soft start circuit starts to work, thereby suppressing the start of the LDO feedback loop; as the LDO slowly starts, the energy storage element is fully charged, the first node becomes at a high potential, the soft start circuit is turned off, and the control effect of the soft start circuit on the feedback loop is automatically cut off, thereby no longer affecting the normal operation of the feedback loop. While achieving rapid power-on of the LDO, the problem of instantaneous overshoot of the LDO voltage upon power-on can be effectively solved; and the circuit structure is simple, the chip occupies a small area, and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the circuit structure of a soft start circuit applied to an LDO in a preferred embodiment of the present invention;

[0018] Figure 2 FIG. 1 is a circuit diagram of an LDO circuit in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0020] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a slow start circuit and an LDO circuit applied to LDO are provided, which belong to the technical field of integrated circuits. Figure 1As shown, the circuit comprises: a power regulating tube, the source and drain of the power regulating tube are connected between an input terminal VIN and an output terminal VOUT; an energy storage element, connected between a first node A and a ground terminal; a feedback branch, connected between a bias power supply and the first node A, the control end of the feedback branch is connected to the first node A, forming a positive feedback loop for accelerating the voltage increase of the first node A; a charging branch is provided between the bias power supply and the ground terminal, the control end of the charging branch is connected to the first node A, for controlling the charging branch to charge the energy storage element; an amplifier stage branch and a buffer stage branch. The invention relates to a circuit comprising a buffer stage branch, a control end of the buffer stage branch connected to the output of the amplifier stage branch, and an output end of the buffer stage branch connected to the gate of a power adjustment tube to inhibit the power adjustment tube from turning on quickly; a switch control circuit, comprising: a switch branch connected between a second node B and a ground terminal, the second node B being connected to the control end of the amplifier stage branch for controlling the amplifier stage branch to turn on or off; and a control branch connected between a bias power supply and the second node B, the control end of the control branch being connected to the first node A for controlling the on / off of the control branch according to the voltage of the first node A, thereby controlling the voltage of the second node B.

[0021] Specifically, in this embodiment, the present invention utilizes a charging branch to charge the energy storage element. Before the LDO circuit is started, the first node A is at a low potential, the energy storage element begins to charge, and simultaneously the soft-start circuit begins to operate, thereby suppressing the startup of the LDO feedback loop. As the LDO slowly starts, the energy storage element is fully charged, the first node A becomes at a high potential, the soft-start circuit is turned off, and the control effect of the soft-start circuit on the feedback loop is automatically cut off, thereby no longer affecting the normal operation of the feedback loop. While achieving rapid power-on of the LDO, the problem of instantaneous overshoot of the LDO voltage upon power-on can be effectively resolved.

[0022] As a preferred embodiment, the feedback branch includes: a first PMOS transistor PM1, wherein the source of the first PMOS transistor PM1 is connected to the bias power supply, the gate of the first PMOS transistor PM1 is connected to the first node A, and the drain of the first PMOS transistor PM1 is connected to the input end of a first inverter INV1; a second PMOS transistor PM2, wherein the source of the second PMOS transistor PM2 is connected to the bias power supply, the gate of the second PMOS transistor PM2 is connected to the output end of a second inverter INV2, the input end of the second inverter INV2 is connected to the output end of the first inverter INV1, and the drain of the second PMOS transistor PM2 is connected to the first node A; and a current comparator circuit, configured to compare the current flowing through the first PMOS transistor PM1 with a reference current generated by a current mirror circuit, and output the comparison result to the input end of the first inverter INV1.

[0023] As a preferred embodiment, the current mirror circuit includes: a first NMOS transistor NM1, the gate of the first NMOS transistor NM1 is connected to a first bias voltage, and the drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1; a second NMOS transistor NM2, the gate of the second NMOS transistor NM2 is connected to a second bias voltage, the drain of the second NMOS transistor NM2 is connected to the source of the first NMOS transistor NM1, and the source of the second NMOS transistor NM2 is grounded.

[0024] Specifically, in this embodiment, the first NMOS transistor NM1 and the second NMOS transistor NM2 form a cascode current mirror to generate a precise current as a reference current, so as to compare the current flowing through the first PMOS transistor PM1 with the reference current, thereby determining the level of the input terminal of the first inverter INV1, and then ultimately controlling the opening and closing of the soft-start circuit through the second PMOS transistor PM2 and the fifth PMOS transistor PM5.

[0025] As a preferred embodiment, the charging branch includes: a first transistor Q1, the base of the first transistor Q1 is connected to the first node A, and the collector of the first transistor Q1 is grounded; a third PMOS transistor PM3, the source of the third PMOS transistor PM3 is connected to the bias power supply, the gate of the third PMOS transistor PM3 is connected to a third bias voltage, and the drain of the third PMOS transistor PM3 is connected to the emitter of the first transistor Q1.

[0026] As a preferred embodiment, the third PMOS transistor PM3 includes one or more third PMOS transistors, and the one or more third PMOS transistors can be connected between the bias power supply and the emitter of the first transistor in a switchable manner.

[0027] Specifically, by adjusting the number of the third PMOS transistors PM3 , the charging time of the charging branch to the energy storage element is adjusted, thereby controlling the startup time of the LDO.

[0028] In this embodiment, one or more third PMOS transistors PM3 may be provided, and the plurality of third PMOS transistors PM3 may be connected in series or in parallel. By adjusting the number of third PMOS transistors PM3, the embodiment of the present invention adjusts the charging current when the base of the first transistor Q1 charges the first capacitor C1, thereby adjusting the capacitor charging time, thereby controlling the LDO startup time to match LDO circuits with different startup times.

[0029] Furthermore, when multiple third PMOS tubes PM3 are arranged in series, the current flowing through the multiple third PMOS tubes PM3 decreases. Therefore, increasing the number of third PMOS tubes PM3 can increase the LDO startup time; reducing the number of third PMOS tubes PM3 can correspondingly reduce the LDO startup time.

[0030] Furthermore, when multiple third PMOS tubes PM3 are connected in parallel, the current flowing through the multiple third PMOS tubes PM3 increases. By increasing the number of third PMOS tubes PM3, the LDO startup time is reduced; by reducing the number of third PMOS tubes PM3, the LDO startup time is increased.

[0031] As a preferred embodiment, the switch control circuit includes: a third NMOS transistor NM3, wherein the gate of the third NMOS transistor NM3 is connected to an enable signal EN_L, the drain of the third NMOS transistor NM3 is connected to the second node B, and the source of the third NMOS transistor NM3 is grounded; a fifth PMOS transistor PM5, wherein the gate of the fifth PMOS transistor PM5 is connected to the first node A, and the drain of the fifth PMOS transistor PM5 is connected to the second node B; and a fourth PMOS transistor PM4, wherein the gate of the fourth PMOS transistor PM4 is connected to a fourth bias voltage, the source of the fourth PMOS transistor PM4 is connected to the bias power supply, and the drain of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5.

[0032] As a preferred embodiment, the amplifier stage branch includes: a fourth NMOS transistor NM4, the gate of the fourth NMOS transistor NM4 is respectively connected to an error amplifier output voltage and the drain of the fifth PMOS transistor PM5, and the source of the fourth NMOS transistor NM4 is grounded; a sixth PMOS transistor PM6, the gate of the sixth PMOS transistor PM6 is connected to a fourth bias voltage, the source of the sixth PMOS transistor PM6 is connected to a bias power supply, and the drain of the sixth PMOS transistor PM6 is connected to the drain of the fourth NMOS transistor NM4, so as to provide a driving current for the fourth NMOS transistor NM4.

[0033] As a preferred embodiment, the buffer stage branch includes: a seventh PMOS transistor PM7, the gate of the seventh PMOS transistor PM7 is connected to the drain of the sixth PMOS transistor PM6, the drain of the seventh PMOS transistor PM7 is connected to the ground terminal through a first resistor R1, and the source of the seventh PMOS transistor PM7 is connected to the gate of the power adjustment tube; an eighth PMOS transistor PM8, the gate of the eighth PMOS transistor PM8 is connected to a fifth bias voltage, the source of the eighth PMOS transistor PM8 is connected to the bias power supply, and the drain of the eighth PMOS transistor PM8 is connected to the source of the seventh PMOS transistor PM7.

[0034] Furthermore, the third PMOS transistor PM4 , the fourth PMOS transistor PM4 , the sixth PMOS transistor PM6 , and the eighth PMOS transistor PM8 serve as branch current sources to provide driving currents.

[0035] In the preferred embodiment described above, the bias power supply is an external input voltage source for providing a bias voltage VBIAS, which provides a static voltage for circuit operation. The bias voltage VBIAS varies within a certain voltage range. Furthermore, the external input voltage source generates fixed bias voltages through the bias circuit, namely, a first bias voltage VBAIS_1, a second bias voltage VBAIS_2, a third bias voltage VBAIS_3, a fourth bias voltage VBAIS_4, and a fifth bias voltage VBAIS_5. The voltage values ​​of these five bias voltages are different and fixed.

[0036] As a preferred embodiment, the energy storage element is a first capacitor C1.

[0037] In the preferred embodiment, the power adjustment tube is the fifth NMOS tube NM5 , the gate of the fifth NMOS tube NM5 is connected to the source of the seventh PMOS tube PM7 , the drain of the fifth NMOS tube NM5 is connected to the input terminal VIN, and the source of the fifth NMOS tube NM5 is connected to the output terminal VOUT.

[0038] Furthermore, the working principle of the slow start circuit of the technical solution of the present invention is as follows: first, before the LDO circuit is started, the voltages of each node are low voltages; when the LDO circuit is started, the bias voltage VBAIS is high potential, and the first bias voltage VBAIS_1, the second bias voltage VBAIS_2, the third bias voltage VBAIS_3, the fourth bias voltage VBAIS_4, and the fifth bias voltage VBAIS_5 begin to be established, and the corresponding first NMOS tube NM1, the second NMOS tube NM2, the third PMOS tube PM3, the fourth PMOS tube PM4, the sixth PMOS tube PM6, and the eighth PMOS tube PM8 are turned on.

[0039] At this time, since the base of the first transistor Q1 is at a low potential and the emitter is at a high potential, the first transistor Q1 is in an on state, and its base current begins to charge the first capacitor C1. After a period of time, the first capacitor C1 is fully charged, and the base potential of the first transistor Q1 becomes high, that is, the voltage at the first node A gradually increases from a low potential. Among them, the first PMOS transistor PM1, the first inverter INV1, the second inverter INV2, and the second PMOS transistor PM2 together form a positive feedback loop. The first PMOS transistor PM1 is also in an on state, and the input terminal of the first inverter INV1 becomes a high potential. After passing through the first inverter INV1 and the second inverter INV2, the high level is output to the gate of the second PMOS transistor PM2. The second PMOS transistor PM2 is turned off, which accelerates the increase of the base potential of the first transistor Q1.

[0040] Furthermore, when the voltage at the first node A becomes high, the fifth PMOS transistor PM5 is turned off due to the high gate potential, thereby cutting off the influence on the LDO loop control.

[0041] After the fifth PMOS transistor PM5 is turned on, it suppresses the gate potential of the fourth NMOS transistor NM4 from becoming low, thereby causing the gate potential of the fourth NMOS transistor NM4 to be pulled up, and the drain potential of the fourth NMOS transistor NM4 to become low. The voltage is then output to the gate of the fifth NMOS transistor NM5 through the buffer stage circuit. The output potential of the buffer stage also becomes low, that is, the gate potential of the fifth NMOS transistor NM5 becomes low. Therefore, VOUT becomes low, and the current flowing through the fifth NMOS transistor NM5 becomes small. As a result, the instantaneous overshoot current at the output end becomes small, thereby playing a buffering role in reducing the current and suppressing the rapid turn-on, thereby solving the problem of instantaneous overshoot of the LDO voltage when it is powered on.

[0042] After the LDO is started, the soft start circuit is in the off state.

[0043] Furthermore, when the enable signal EN_L is at a low level, the third NMOS transistor NM3 is enabled. After the third NMOS transistor NM3 is turned on, it pulls down the gate potential of the fourth NMOS transistor NM4, turning off the fourth NMOS transistor NM4. This disables the LDO circuit control loop, thereby reducing the quiescent current. The third NMOS transistor NM3 can effectively control the on and off of the amplifier NM4.

[0044] In summary, the embodiment of the present invention utilizes the base current of the first transistor Q1 to charge the first capacitor C1. Before the LDO circuit starts, the base potential is low, and the first capacitor C1 begins to charge. Simultaneously, the soft-start circuit begins operating, suppressing the startup of the LDO feedback loop. As the LDO slowly starts, the first capacitor C1 is fully charged, the base potential of the first transistor Q1 becomes high, and the soft-start circuit shuts down, automatically severing its control over the feedback loop and preventing it from affecting normal operation.

[0045] The present invention also provides an LDO circuit, comprising the above-mentioned slow start circuit.

[0046] Specifically, such as Figure 2 As shown, the LDO circuit includes 6 ports, including input, output, bias voltage, enable, feedback, and ground. The input is connected to an input voltage VIN and is connected to an input capacitor. Connect to the ground terminal; connect the enable terminal to an enable signal for enable control; connect the bias voltage terminal to a bias power supply and pass a bias capacitor Connect to the ground terminal, the bias power supply is used to provide a bias voltage VBIAS for the LDO; the ground port is grounded; the output terminal is used to output an output voltage VOUT and pass an output capacitor The feedback terminal is used to receive a feedback signal from the voltage divider circuit, which is connected between the output terminal and the ground terminal, and specifically includes a second resistor R2 and a third resistor R3. The feedback terminal is connected to the connection point of the second resistor R2 and the third resistor R3.

[0047] The above technical solution has the following advantages or beneficial effects: the present invention utilizes a charging branch to charge the energy storage element. Before the LDO circuit is started, the first node is at a low potential, the energy storage element starts to charge, and at the same time, the soft-start circuit starts to operate, thereby suppressing the start-up of the LDO feedback loop; as the LDO slowly starts, the energy storage element is fully charged, the first node becomes at a high potential, the soft-start circuit is turned off, and the control effect of the soft-start circuit on the feedback loop is automatically cut off, thereby no longer affecting the normal operation of the feedback loop. While achieving rapid power-on of the LDO, the problem of instantaneous overshoot of the LDO voltage during power-on can be effectively solved; in addition, the circuit structure is simple, the chip occupies a small area, and the cost is low.

[0048] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A slow start circuit for LDO, characterized in that: include: a power regulating tube, wherein a source and a drain of the power regulating tube are connected between an input terminal and an output terminal; an energy storage element connected between a first node and a ground terminal; a feedback branch connected between a bias power supply and the first node, wherein a control end of the feedback branch is connected to the first node to form a positive feedback loop; Between the bias power supply and the ground terminal is provided: a charging branch, wherein a control end of the charging branch is connected to the first node and is used to control the charging branch to charge the energy storage element; an amplifier stage branch and a buffer stage branch, wherein the control end of the buffer stage branch is connected to the output of the amplifier stage branch, and the output end of the buffer stage branch is connected to the gate of a power adjustment tube; A switch control circuit, comprising: a switch branch connected between a second node and the ground terminal, the second node being connected to a control terminal of the amplifier stage branch for controlling the amplifier stage branch to be turned on or off; a control branch connected between the bias power supply and the second node, the control terminal of the control branch being connected to the first node for controlling the on / off state of the control branch based on a voltage at the first node, thereby controlling the voltage at the second node; The feedback branch includes: a first PMOS transistor, wherein a source of the first PMOS transistor is connected to the bias power supply, a gate of the first PMOS transistor is connected to the first node, and a drain of the first PMOS transistor is connected to an input end of a first inverter; a second MOS transistor, one end of the second MOS transistor being connected to the bias power supply, a gate of the second MOS transistor being connected to the output end of a second inverter, an input end of the second inverter being connected to the output end of the first inverter, and the other end of the second MOS transistor being connected to the first node, to accelerate the voltage at the control end of the control branch to become higher; A current comparison circuit is used to compare the current flowing through the first PMOS transistor with a reference current generated by a current mirror circuit, and output the comparison result to the input terminal of the first inverter.

2. The slow start circuit according to claim 1, characterized in that: The current mirror circuit comprises: a first NMOS transistor, wherein a gate of the first NMOS transistor is connected to a first bias voltage, and a drain of the first NMOS transistor is connected to a drain of the first PMOS transistor; a second NMOS transistor, wherein a gate of the second NMOS transistor is connected to a second bias voltage, a drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the source of the second NMOS transistor is grounded.

3. The slow start circuit according to claim 1, characterized in that: The charging branch includes: a first transistor, wherein a base of the first transistor is connected to the first node, and a collector of the first transistor is grounded; a third PMOS transistor, wherein a source of the third PMOS transistor is connected to the bias power supply, a gate of the third PMOS transistor is connected to a third bias voltage, and a drain of the third PMOS transistor is connected to the emitter of the first transistor.

4. The slow start circuit according to claim 3, characterized in that: The third PMOS transistors include more than one, and the more than one third PMOS transistors can be connected between the bias power supply and the emitter of the first transistor in a switchable manner.

5. The slow start circuit according to claim 1, characterized in that: The switch control circuit includes: a third NMOS transistor, wherein a gate of the third NMOS transistor is connected to an enable signal, a drain of the third NMOS transistor is connected to the second node, and a source of the third NMOS transistor is grounded; a fifth PMOS transistor, wherein a gate of the fifth PMOS transistor is connected to the first node, and a drain of the fifth PMOS transistor is connected to the second node; a fourth PMOS transistor, wherein a gate of the fourth PMOS transistor is connected to a fourth bias voltage, a source of the fourth PMOS transistor is connected to the bias power supply via a current source, and a drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor.

6. The slow start circuit according to claim 5, characterized in that: The amplifying stage branch comprises: a fourth NMOS transistor, wherein a gate of the fourth NMOS transistor is respectively connected to an error amplifier output voltage and a drain of the fifth PMOS transistor, and a source of the fourth NMOS transistor is grounded; a sixth PMOS transistor, wherein a gate of the sixth PMOS transistor is connected to the fourth bias voltage, a source of the sixth PMOS transistor is connected to the bias power supply, and a drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor, for providing a driving current for the fourth NMOS transistor.

7. The slow start circuit according to claim 6, characterized in that: The buffer level branch includes: a seventh PMOS transistor, wherein a gate of the seventh PMOS transistor is connected to the drain of the sixth PMOS transistor, the drain of the seventh PMOS transistor is connected to the ground terminal via a first resistor, and a source of the seventh PMOS transistor is connected to the gate of the power adjustment transistor; an eighth PMOS transistor, wherein a gate of the eighth PMOS transistor is connected to a fifth bias voltage, a source of the eighth PMOS transistor is connected to the bias power supply, and a drain of the eighth PMOS transistor is connected to the source of the seventh PMOS transistor.

8. The slow start circuit according to claim 1, characterized in that: The energy storage element is a capacitor.

9. An LDO circuit, characterized in that: The invention comprises a soft start circuit as described in any one of claims 1 to 8.

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