A self-calibrating comparator circuit, method of operation, integrated circuit and electronic device

Abstract

The application provides a self-calibration comparator circuit, a working method, an integrated circuit and an electronic device, and relates to the technical field of integrated circuits. The self-calibration comparator circuit comprises a comparator, a buffer, a phase detector and an edge calibration circuit. The comparator differentially outputs an input signal as a first signal and a second signal. The buffer reshapes and outputs the first signal and the second signal as a third signal and a fourth signal. The phase detector detects a phase difference between the third signal and the fourth signal, and outputs a calibration signal according to the phase difference. The edge calibration circuit converts the third signal and the fourth signal into a fifth signal, and aligns a rising edge and a falling edge of the fifth signal with a falling edge of the calibration signal, respectively. According to the comparator circuit of the application, the rising delay and the falling delay can be automatically calibrated, and the rising delay and the falling delay can be kept consistent.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular, to a self-calibration comparator circuit, a working method, an integrated circuit and an electronic device. BACKGROUND

[0002] Comparators are widely used and are one of the most common circuits. In many applications, such as signal recognition, motor control, etc., the delay characteristics of the comparator are required to be relatively strict, especially the rising delay and the falling delay of the comparator, which are expected to be as consistent as possible. However, due to the influence of process deviation and other factors, the pull-up capability and the pull-down capability of the output stage of the comparator will be different, and such difference will cause the rising delay and the falling delay of the output signal to be different from the input signal.

[0003] For example, when a comparator is used to compare an input signal, the rising delay and the falling delay of the ideal comparator are consistent, and thus the high level time and the low level time of the ideal output signal will not change.

[0004] If the pull-up capability of the output stage of the comparator is stronger than the pull-down capability, the rising delay will be less than the falling delay, which will cause the high level time of the output signal to be expanded. In some applications, this phenomenon will cause problems, for example, when a comparator is used for signal recognition, if the rising delay and the falling delay of the comparator are greatly different, it is possible to cause the change of the signal occupation ratio to be large, so as to fail to meet the timing requirements of the signal. SUMMARY

[0005] The present application provides a self-calibration comparator circuit, a working method, an integrated circuit and an electronic device, which can automatically calibrate the rising delay and the falling delay of the comparator, so as to keep them consistent, and select the minimum delay between the rising delay and the falling delay as the calibration value.

[0006] According to an aspect of the present application, a self-calibration comparator circuit is provided, comprising: a comparator, which differentially outputs an input signal as a first signal and a second signal; a buffer, which shapes the first signal and the second signal and outputs them as a third signal and a fourth signal; a phase detector, which detects the phase difference between the third signal and the fourth signal and outputs a calibration signal according to the phase difference; and an edge calibration circuit, which converts the third signal and the fourth signal into a fifth signal, and aligns the rising edge or the falling edge of the fifth signal with the falling edge of the calibration signal.

[0007] According to some embodiments, the first signal and the second signal have the same amplitude and opposite phases.

[0008] According to some embodiments, the first signal and the second signal have a rising delay and a falling delay, and the rising delay and the falling delay of the first signal and the second signal are different.

[0009] According to some embodiments, the rising delay and the falling delay of the third signal and the fourth signal are the same as the rising delay and the falling delay of the first signal and the second signal, and the phase difference exists.

[0010] According to some embodiments, the high level or the low level of the calibration signal is the phase difference.

[0011] According to some embodiments, the pulse width of the calibration signal is the time difference of the rising delay and the falling delay of the first signal and the second signal.

[0012] According to some embodiments, the edge calibration circuit operates when the calibration signal is at a low level, and maintains the previous state when the calibration signal is at a high level.

[0013] According to some embodiments, the fifth signal is a single-ended signal, and the rising delay and the falling delay of the fifth signal are equal.

[0014] According to some embodiments, the rising delay and the falling delay of the fifth signal are both the larger value of the rising delay and the falling delay of the first signal and the second signal.

[0015] According to some embodiments, the comparator circuit further comprises a shifter that calibrates the period of the fifth signal and outputs as an output signal.

[0016] According to some embodiments, the shifter takes the smaller value of the rising delay and the falling delay of the first signal and the second signal as the calibration value of the output signal relative to the input signal.

[0017] According to an aspect of the present application, a method for operating a self-calibration comparator circuit is provided, comprising: outputting an input signal differentially as a first signal and a second signal; shaping the first signal and the second signal to output as a third signal and a fourth signal; detecting a phase difference of the third signal and the fourth signal, and outputting a calibration signal according to the phase difference; converting the third signal and the fourth signal to a fifth signal, and calibrating the rising delay and the falling delay of the fifth signal; adjusting the period of the fifth signal and outputting as an output signal.

[0018] According to some embodiments, adjusting the period of the fifth signal and outputting as an output signal comprises: advancing the rising edge and the falling edge of the fifth signal by a pulse width of the calibration signal to generate the output signal.

[0019] According to an aspect of the present application, there is provided an integrated circuit comprising the comparator circuit as described above.

[0020] According to an aspect of the present application, there is provided an electronic device comprising the comparator circuit as described above or the integrated circuit as described above.

[0021] According to embodiments of the present application, the rising delay and the falling delay of the comparator output can be automatically calibrated and kept consistent along the calibration circuit, and the minimum delay can be selected as the calibration value by the shifter, so that the output signal can meet the corresponding timing requirements.

[0022] It should be understood that the general description above and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application.

[0024] Figure 1 A comparison diagram showing the ideal output and the actual output of a comparator.

[0025] Figure 2 A schematic diagram of a self-calibration comparator circuit according to an example embodiment of the present application.

[0026] Figure 3 A flow chart of a working method of a self-calibration comparator circuit according to an example embodiment of the present application.

[0027] Figure 4 A signal timing diagram showing the working of a self-calibration comparator circuit according to an example embodiment of the present application.

[0028] Figure 5 A circuit diagram of a self-calibration comparator circuit according to an example embodiment of the present application.

[0029] Figure 6 A signal timing diagram showing the working of a shifter of a self-calibration comparator circuit according to an example embodiment of the present application. DETAILED DESCRIPTION

[0030] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments may, however, be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same elements will not be repeated.

[0031] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the technology can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In some instances, well-known structures, methods, devices, implementations, materials, and operations are not shown or described in detail.

[0032] The flowcharts shown in the drawings are only illustrative, and do not necessarily include all contents and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps can be further decomposed, and some operations / steps can be combined or partially combined, so the actual execution order can be changed according to actual conditions.

[0033] The terms "first", "second", and the like in the specification and claims of the present application and the above drawings are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product, or device.

[0034] The present application provides a comparator circuit, an integrated circuit, and an electronic device, which can be used to automatically calibrate the rising delay and falling delay of the comparator and keep the rising delay and falling delay consistent.

[0035] A comparator circuit according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 A comparison diagram showing the ideal output and the actual output of a comparator is shown.

[0037] As Figure 1 shown, the input signal is a square wave signal, which is compared by the comparator and output.

[0038] In an ideal state, the pull-up capability and the pull-down capability of the output stage of the comparator are consistent, so the rising delay t dr and the falling delay t df of the comparator are consistent, and the high level time t h and the low level time t l of the output signal do not change compared with the input signal, and the duty cycle of the output signal is unchanged.

[0039] In practice, the pull-up and pull-down capabilities of the comparator output stage are inconsistent, causing a difference between the output signal waveform and the input signal waveform. For example, if the comparator's pull-up capability is stronger than its pull-down capability, such as... Figure 1 As shown, this causes the rise delay t dr Less than the descent delay t df Thus, the high-level time t of the output signal h Increase the low-level time t l The reduction causes a significant change in the duty cycle of the output signal compared to the input signal.

[0040] Figure 2 A schematic diagram of a self-calibrating comparator circuit according to an example embodiment of this application is shown.

[0041] like Figure 2 As shown, the comparator system includes a comparator 101, a buffer 102, a phase detector 103, an edge calibration circuit 104, and a shifter 105.

[0042] Comparator 101 is a differential comparator used to convert the input signal V at the non-inverting input terminal into a differential comparator. IP The difference is the first signal V OP Second signal V ON .

[0043] According to some embodiments, the first signal V OP Second signal V ON The amplitudes are the same, but the phases are opposite, i.e., V ON As it rises, V OP Decrease; or V ON While V is decreasing OP rise.

[0044] Because the comparator output has different pull-up and pull-down capabilities, the first signal V output by the comparator... OP Second signal V ON The rise and fall delays differ, and V OP and V ON There is a certain phase difference between them.

[0045] Buffer 102 is used to store the first signal V output by comparator 101. OP Second signal V ON The waveform is shaped into a waveform with relatively steep rising and falling edges, and output as the third signal V. OP1 and the fourth signal V ON1 .

[0046] Obviously, the third signal V OP1 and the fourth signal V ON1 The rise delay and fall delay are the first signal V.OP and the rising delay and falling delay of the second signal V ON , and the phase difference between V OP1 and V ON1 is the phase difference between V OP and V ON .

[0047] The phase detector 103 receives the third signal V OP1 and the fourth signal V ON1 , detects the phase difference between V OP1 and V ON1 , and generates the calibration signal V OP1 according to the phase difference between V ON1 and V OF .

[0048] According to some embodiments, the high level or low level of the calibration signal V OF is the phase difference between V OP1 and V ON1 . In the example embodiments of the present application, the high level of the calibration signal V OF is the phase difference between V OP1 and V ON1 .

[0049] In addition, the pulse width of the calibration signal V OF is the difference between the rising delay time and the falling delay time of the first signal V OP and the second signal V ON .

[0050] The alignment circuit 104 receives the third signal V OP1 and the fourth signal V ON1 , as well as the calibration signal V OF , and converts the third signal V OP1 and the fourth signal V ON1 into the fifth signal V OC according to the calibration signal V OF .

[0051] According to some embodiments, the fifth signal V OC is a single-ended signal.

[0052] According to the example embodiments of the present application, the alignment circuit 104 works when the calibration signal V OF is at a low level, and when the calibration signal V OF is at a high level, it maintains the working state of the calibration signal V OF at the previous low level before the high level.

[0053] The third signal V OP1 and the fourth signal V ON1Alignment calibration signal V with rising or falling edge OF The falling edge yields the fifth signal V. OC .

[0054] According to some embodiments, the fifth signal V OC The rise delay and fall delay are equal and both are the first signal V. OP Second signal V ON The larger of the rise delay and fall delay.

[0055] Displacer 105 receives the fifth signal V OC and the fifth signal V OC The rising and falling edges of the waveform are preceded by a calibration signal V. OF The pulse width is used to obtain the output signal V. OUT The waveform.

[0056] According to some embodiments, the output signal V OUT The rise delay and fall delay are equal, and the output signal V is equal to the input signal. OUT The rise delay and fall delay are the first signal V OP Second signal V ON The smaller of the rise delay and fall delay.

[0057] Figure 3 A flowchart illustrating the operation of a self-calibrating comparator circuit according to an example embodiment of this application is shown.

[0058] like Figure 3 As shown, in S201, the input signal is differentially output as a first signal and a second signal.

[0059] According to some embodiments, the input signal is differentially divided into a first signal V by a comparator. OP Second signal V ON Furthermore, the two are in opposite phases.

[0060] In S203, the first and second signals are shaped and output as the third and fourth signals.

[0061] According to some embodiments, the buffer will receive the first signal V OP Second signal V ON The third signal V is shaped into one with steeper rising and falling edges. OP1 and the fourth signal V ON1 .

[0062] Third signal V OP1 and the fourth signal V ON1 The rise delay and fall delay are related to the first signal V OP Second signal V ONThe rising delay and falling delay of the third signal and the fourth signal are the same, and there is a phase difference.

[0063] In S205, the phase difference of the third signal and the fourth signal is detected, and a calibration signal is output according to the phase difference.

[0064] The phase difference of the third signal V OP1 and the fourth signal V ON1 is detected by a phase detector, and the phase difference is used as a high level of the calibration signal V OF .

[0065] According to some embodiments, the phase difference of the third signal V OP1 and the fourth signal V ON1 may also be used as a low level of the calibration signal V OF .

[0066] The pulse width of the calibration signal V OF is the difference between the rising delay time and the falling delay time of the first signal V OP and the second signal V ON .

[0067] In S207, the third signal and the fourth signal are converted into a fifth signal, and the rising delay and the falling delay of the fifth signal are calibrated.

[0068] According to some embodiments, the differential third signal V OP1 and the fourth signal V ON1 are converted into a single-ended fifth signal V OC along the calibration circuit, and the rising delay and the falling delay of the fifth signal V OC are equal.

[0069] In S209, the period of the fifth signal is adjusted and output as an output signal.

[0070] According to some embodiments, the shifter advances the rising edge and the falling edge of the fifth signal V OC by the pulse width of the calibration signal V OF , and obtains an output signal V OUT .

[0071] Figure 4 The signal timing diagram showing the operation of the self-calibration comparator circuit according to the example embodiments of the present application is shown.

[0072] As shown in Figure 4 , according to some embodiments, the input signal V IN of the inverting input terminal of the comparator is a reference voltage, and the input signal V IP of the non-inverting input terminal is a square wave signal.

[0073] The differential signal V OPand V ON And V OP and V ON The amplitudes are the same, but the phases are opposite.

[0074] According to some embodiments, the pull-up and pull-down capabilities of the comparator output stage differ. In the example embodiment of this application, the pull-up capability of the comparator output stage is stronger than the pull-down capability, therefore V OP and V ON rise delay time t rd Less than the descent delay time t rf .

[0075] V through the buffer OP and V ON Shaping is performed to obtain a signal V with steeper rising and falling edges. OP1 and V ON1 And V OP1 and V ON1 The amplitudes are the same, but the phases are opposite.

[0076] V OP1 and V ON1 The rise delay time is V. OP and V ON rise delay time t rd The descent delay time is V. OP and V ON descent delay time t rf .

[0077] Depend on Figure 4 It can be seen that the buffer reverses near the midpoint of the voltage swing, and the phase of V is opposite. OP1 and V ON1 A time difference t appeared between them. d That is, rise delay time t rd With descent delay time t rf The difference is the time difference t d Time difference t d =t rf -t rd .

[0078] Phase detector detects V OP1 and V ON1 The phase difference and time difference t between them d This forms a calibration signal V. OF .

[0079] According to some embodiments, the calibration signal V OF A pulse, its high level is V OP1 and V ON1 The phase difference between them, with a width equal to the time difference t d .

[0080] The calibration circuit uses the calibration signal V OF , to convert V OP1 and V ON1 into a single-ended output signal V OC .

[0081] The shifter shifts the rising edge and falling edge of the signal V OC by t d , to obtain an output signal V OUT , and an output signal V OUT is delayed by t IP relative to the input signal V rd .

[0082] Since t rd is less than t rf , in the embodiment of the present application, the minimum delay between the rising delay and the falling delay of the comparator output is selected as the calibration value.

[0083] Figure 5 A circuit diagram of a self-calibration comparator circuit according to an example embodiment of the present application is shown.

[0084] As shown in Figure 5 , the comparator system of the embodiment of the present application includes a comparator, a buffer, a phase detector, a edge calibration circuit, and a shifter.

[0085] Generally, the comparator, the buffer, and the phase detector are integrated circuit elements, which are in the same chip and have many design methods, which are not described in detail in the present application.

[0086] The edge calibration circuit is composed of M0-M3, wherein the first end of M0 is connected to ground, the second end is connected to the non-inverted output of the signal V OP1 , and the third end is connected to M1; the first end of M1 is connected to the third end of M0, the second end is connected to the inverted output of the signal V OF , and the third end is connected to M2 and the output of the signal V OC ; the first end of M2 is connected to the third end of M1 and the output of the signal V OC , the second end is connected to the non-inverted output of the signal V OF , and the third end is connected to M3; the first end of M3 is connected to the third end of M2, the second end is connected to the inverted output of the signal V ON1 , and the third end is connected to ground.

[0087] M1 is connected to the inverted output of V OF , M2 is connected to the non-inverted output of V OF , M0 is connected to the non-inverted output of V OP1 , and M3 is connected to the inverted output of V ON1 .

[0088] When calibration signal V OF When in a high-level state, i.e., V OP1 and V ON1 There is a time difference between the rising and falling edges, M1 and M2 are turned off, V OC The node forms a high impedance, V OC The voltage remains unchanged from its previous state.

[0089] When calibration signal V OF When in a low-level state, M1 and M2 are turned on, V OP1 and V ON1 The phases of the opposite and inverted outputs are the same, if V OP1 When it is at a high level, then V OC The output is high; if V OP1 When it is at a low level, then V OC The output is low.

[0090] For example, such as Figure 4 The T1 time period shown is V OP1 The phase detector detects V when the voltage level changes from low to high. OP1 There is a time difference between the rising and falling edges of the calibration signal V. OF If the output is high, then V OC Maintain the previous state and output a low level.

[0091] After a period of time t rd +t d =t rf Then, during time period T2, the calibration signal V... OF The output is low, indicating that the calibration circuit is in operation. OC Follow V OP1 The high level is also output as a high level.

[0092] Entering the T3 period, V OP1 When the voltage level changes from high to low, the phase detector detects V. OP1 There is a time difference between the rising and falling edges of the calibration signal V. OF If the output is high, then V OC Maintain the previous state and output a high level.

[0093] After a period of time t rf Then, during time period T4, the calibration signal V... OF The output is low, V OC Follow V OP1 The low level is also output as a low level.

[0094] Therefore, it can be seen that V along the calibration circuit OC The rise delay and fall delay are unified as trf V OP and V ON The rise delay t rd and descent delay t rf The maximum value in.

[0095] The displacement circuit includes a falling edge delay detection circuit and a rising edge delay detection circuit, used to detect V OC Falling edge delay V FE and rising edge delay V RE Separate them.

[0096] Among them, the falling edge delay detection circuit and the signal V output by the edge calibration circuit OC and calibration signal V OF Connect and output the falling edge delay V FE .

[0097] Rising edge delay detection circuit and calibration signal V OF Connect to the output of the falling edge delay detection circuit and output the rising edge delay V. RE .

[0098] The displacement unit also includes a rising edge displacement circuit and a falling edge displacement circuit, wherein the rising edge displacement circuit is connected to the signal V output by the calibration circuit. OC It is connected to the output of the rising edge delay detection circuit and outputs a signal V that has undergone rising edge shifting processing. OC1 .

[0099] The output terminals of the falling edge shift circuit and the falling edge delay detection circuit and the signal V OC1 Connect and output the final output signal V. OUT .

[0100] Falling edge delay V FE and rising edge delay V RE The pulse width is t d V OC The rising and falling edges are used to shift forward by t through the rising edge displacement circuit and the falling edge displacement circuit. d Obtain the output signal V OUT .

[0101] Output signal V OUT Compared to the input signal, it has only a minimal delay time t. rd ,like Figure 6 As shown.

[0102] Alternatively, the displacement can also be implemented using the following combinational logic:

[0103] V FE =V OC +V OF

[0104] V RE = V FE + V OF

[0105] V OC1 = V OC + V RE

[0106] V OUT = V OC1 + V FE

[0107] The same logic function can be achieved by changing the Boolean algebra method of combination logic.

[0108] According to some embodiments of the present application, the technical solution of the present application can automatically calibrate the rising delay and falling delay of the comparator output signal, keep the rising delay and falling delay consistent, select the minimum delay as the calibration value, and make the output signal meet the corresponding timing requirements.

[0109] The above describes the embodiments of the present application in detail, and the above embodiment descriptions are only used to help understand the method of the present application and its core idea. Meanwhile, the changes or deformations made by the skilled in the art according to the idea of the present application, based on the specific implementation and application range of the present application, all belong to the protection range of the present application. In summary, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A self-calibrating comparator circuit, characterized in that, include: The comparator differentially outputs the input signal as a first signal and a second signal. The buffer shapes the first and second signals into a third and a fourth signal; A phase detector detects the phase difference between the third signal and the fourth signal, and outputs a calibration signal based on the phase difference; Along the calibration circuit, the third signal and the fourth signal are converted into a fifth signal, and the rising edge or falling edge of the fifth signal is aligned with the falling edge of the calibration signal; The calibration circuit includes field-effect transistors M0, M1, M2, and M3. M0 and M1 are NMOS transistors, and M2 and M3 are PMOS transistors. The source of M0 is grounded, its gate is connected in phase with the third signal, and its drain is connected to M1. The source of M1 is connected to the drain of M0, its gate is connected in phase with the calibration signal, and its drain is connected to M2 and the fifth signal output terminal. The source of M2 is connected to the drain of M1 and the fifth signal output terminal, its gate is connected in phase with the calibration signal, and its drain is connected to M3. The source of M3 is connected to the drain of M2, its gate is connected in phase with the fourth signal, and its drain is grounded. M1 is connected to the inverted output of the calibration signal, M2 is connected to the non-inverted output of the calibration signal, M0 is connected to the non-inverted output of the third signal, and M3 is connected to the inverted output of the fourth signal. The pulse width of the calibration signal is the time difference between the rise delay of the first signal and the fall delay of the second signal.

2. The circuit according to claim 1, characterized in that, The first signal and the second signal have the same amplitude but opposite phase.

3. The circuit according to claim 1, characterized in that, The first signal and the second signal have rise delay and fall delay, and the rise delay and fall delay of the first signal and the second signal are different.

4. The circuit according to claim 1, characterized in that, The rise delay and fall delay of the third signal and the fourth signal are the same as the rise delay and fall delay of the first signal and the second signal, and the phase difference exists.

5. The circuit according to claim 1, characterized in that, The calibration circuit, It operates when the calibration signal is at a low level; The previous state is maintained when the calibration signal is high.

6. The circuit according to claim 1, characterized in that, The fifth signal is a single-ended signal, and the rise delay and fall delay of the fifth signal are equal.

7. The circuit according to claim 6, characterized in that, The rise delay and fall delay of the fifth signal are both the larger of the rise delay and fall delay of the first signal and the second signal.

8. The circuit according to claim 1, characterized in that, Also includes: The displacement device adjusts the period of the fifth signal and outputs it as an output signal.

9. The circuit according to claim 8, characterized in that, The displacement sensor uses the smaller of the rise delay and fall delay of the first signal and the second signal as the calibration value of the output signal relative to the input signal.

10. A method for operating a self-calibrating comparator circuit, characterized in that, include: The input signal is differentially output into a first signal and a second signal; The first and second signals are shaped and output as the third and fourth signals; The phase difference between the third signal and the fourth signal is detected, and a calibration signal is output based on the phase difference; The third and fourth signals are converted into a fifth signal along the calibration circuit, and the rise delay and fall delay of the fifth signal are calibrated according to the calibration signal. Adjust the period of the fifth signal and output it as an output signal; Wherein, the pulse width of the calibration signal is the time difference between the rise delay of the first signal and the fall delay of the second signal; The calibration circuit includes field-effect transistors M0, M1, M2, and M3. M0 and M1 are NMOS transistors, and M2 and M3 are PMOS transistors. The source of M0 is grounded, the gate of M0 is connected in phase with the third signal, and the drain of M0 is connected to M1. The source of M1 is connected to the drain of M0, the gate of M1 is connected in phase with the calibration signal, and the drain of M1 is connected to M2 and the fifth signal output terminal. The source of M2 is connected to the drain of M1 and the fifth signal output terminal, the gate of M2 is connected in phase with the calibration signal, and the drain of M2 is connected to M3. The source of M3 is connected to the drain of M2, the gate of M3 is connected in phase with the fourth signal, and the drain of M3 is grounded. M1 is connected to the inverted output of the calibration signal, M2 is connected to the non-inverted output of the calibration signal, M0 is connected to the non-inverted output of the third signal, and M3 is connected to the inverted output of the fourth signal.

11. The method according to claim 10, characterized in that, Adjusting the period of the fifth signal and outputting it as an output signal includes: The rising and falling edges of the fifth signal are advanced by the pulse width of the calibration signal to generate the output signal.

12. An integrated circuit, characterized in that, Includes the comparator circuit as described in any one of claims 1-9.

13. An electronic device, characterized in that, Includes the comparator circuit as described in any one of claims 1-9 or the integrated circuit as described in claim 12.

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