Reconfigurable logic gates based on FeFET+RRAM structure and their fabrication and application methods

Abstract

This invention discloses a reconfigurable logic gate based on a FeFET+RRAM structure, along with its fabrication and application methods. The fabrication process begins by depositing an oxide passivation layer on a FeFET sample, followed by etching to form vias. Subsequently, a metal bottom electrode, a resistive switching material such as hafnium oxide, and a top electrode metal are deposited. Finally, photolithography and etching are used to form the MIM structure on the original FeFET port, completing the integration of RRAM and FeFET. The logic function is verified by measuring the output current and voltage using a semiconductor parameter analyzer. This invention utilizes the threshold voltage differences of FeFETs under different polarization states and the resistive switching characteristics of RRAM, allowing the integrated structure to achieve reconfigurable logic functions by adjusting the RRAM resistance. This reconfigurable logic gate has a simple structure, small circuit area, low power consumption, and CMOS compatibility.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit and semiconductor technology, specifically relating to a reconfigurable logic gate based on FeFET+RRAM structure and its preparation and use method. Background Technology

[0002] With the rapid development of integrated circuit technology into the post-Moore's Law era, how to further reduce chip area while achieving the same circuit function has become an increasingly important challenge. Due to the effects of short-channel effects, reducing the channel width and length of traditional MOSFETs has gradually become impractical, thus requiring new methods to reduce the area of ​​integrated circuits.

[0003] A ferroelectric field-effect transistor (FeFET), also known as a ferroelectric gate field-effect transistor, can be considered as replacing the silicon dioxide insulating gate dielectric of a traditional transistor with a ferroelectric material. When a positive write voltage is applied to the gate, an inversion layer forms on the channel surface, creating a current path between the source and drain, corresponding to the write process of the device. When a negative erase voltage is applied to the gate, an accumulation layer forms on the channel surface, cutting off the current path between the source and drain, corresponding to the erase process of the device. When the polarization states of the gate dielectric layer of a ferroelectric transistor are inconsistent, the threshold voltage of the transistor is also inconsistent.

[0004] Resistive random access memory (RRAM), also known as memristor, is a new type of non-volatile random access memory. It has a very simple structure, is compatible with standard CMOS technology, and features low operating voltage, fast read and write speed, and low power consumption. Its storage information cells are variable resistors implemented by one or more metal oxides. Under different write voltages, RRAM exhibits two resistance states: high resistance state and low resistance state, such as 100KΩ and 10KΩ.

[0005] Chinese patent application CN107786198A proposes a reconfigurable logic circuit in which the circuit part used for storage and the circuit part used for logic operation are separate, using traditional CMOS circuits and memory structures respectively. This makes the entire reconfigurable logic gate circuit have a large area and power consumption, affecting the circuit performance.

[0006] The literature [Pan, C., Wang, CY., Liang, SJ. et al. Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions. Nat Electron 3, 383–390 (2020)] proposes a method for realizing reconfigurable logic gates using homojunction devices made of two-dimensional tungsten diselenide. These devices can exhibit different field-effect characteristics controlled by the polarity combination of gate and drain voltage inputs, thereby realizing reconfigurable logic functions. However, this method for realizing reconfigurable logic gates is incompatible with CMOS technology and is difficult to integrate with CMOS circuits and apply to the industrialization of integrated circuits. Summary of the Invention

[0007] In view of the above, the present invention provides a reconfigurable logic gate based on FeFET+RRAM structure and its preparation and use method. The reconfigurable logic gate has the advantages of simple structure, CMOS process compatibility, small circuit area, and multiple logic functions (10 types) and has broad application prospects in the field of in-memory computing integrated circuits.

[0008] A reconfigurable logic gate based on a FeFET+RRAM structure consists of two parts: a FeFET and an RRAM. The FeFET includes three sets of electrodes: an active electrode, a drain electrode, and a gate electrode. The RRAM is integrated on the drain electrode of the FeFET and consists of a bottom electrode layer, a resistive switching dielectric layer, and a top electrode layer from bottom to top.

[0009] Furthermore, the reconfigurable logic gate utilizes the ferroelectric polarization state (manifested as threshold voltage) stored in the ferroelectric layer of the FeFET as one input and the voltage applied to the gate of the FeFET as another input, thereby realizing the function of a dual-input logic gate. In addition, the reconfigurable logic gate utilizes the resistive switching characteristics of RRAM, and after adjusting the RRAM to a suitable resistance value, it serves as the pull-up resistor of the FeFET, thereby realizing different logic functions to reflect its reconfigurability.

[0010] Furthermore, the FeFET also includes a silicon substrate, an oxide layer, and a ferroelectric layer. The oxide layer material is silicon oxide, aluminum oxide, or hafnium oxide, and the ferroelectric layer material is hafnium zirconium oxide, bismuth titanate, or lead zirconate titanate.

[0011] Furthermore, the source and drain electrodes in the FeFET are electrode materials that form ohmic contacts with the silicon substrate, and the electrode materials are aluminum, nickel, gold or tungsten, and the gate material is also aluminum, nickel, gold or tungsten.

[0012] Furthermore, the electrode layer material in the RRAM is made of aluminum, tungsten, platinum, or titanium.

[0013] Furthermore, the resistive switching dielectric layer material is titanium oxide, zinc oxide, hafnium oxide, or germanium selenide.

[0014] The method for preparing the above-mentioned reconfigurable logic gate includes the following steps:

[0015] (1) An oxide passivation layer is deposited on the drain of the FeFET, and a via is etched on the passivation layer for material deposition.

[0016] (2) The bottom electrode layer, the resistive switching dielectric layer and the top electrode layer are sequentially prepared in the through hole;

[0017] (3) The top electrode layer and resistive switching dielectric layer are formed by photolithography and etching to remove the unwanted patterned parts, thereby forming a MIM (metal-dielectric layer-metal) structure, thus realizing the integration of FeFET and RRAM, and forming a reconfigurable logic gate based on the FeFET+RRAM structure.

[0018] Furthermore, in step (1), atomic layer deposition is used for deposition, and inorganic acid wet etching (hydrofluoric acid, hydrochloric acid or sulfuric acid) is used for etching.

[0019] Furthermore, in step (2), the bottom electrode layer and the top electrode layer are prepared by magnetron sputtering, electron beam evaporation or thermal evaporation, and the resistive switching dielectric layer is prepared by atomic layer deposition.

[0020] Furthermore, in step (3), plasma etching is used for etching.

[0021] The method of using the above-mentioned reconfigurable logic gate is as follows: First, apply a voltage to the top electrode layer of the RRAM and ground the bottom electrode layer to set the RRAM to a suitable resistance value state according to the logic function to be implemented; then apply a voltage pulse signal to the gate of the FeFET to set the ferroelectric polarization state of the FeFET (expressed as a threshold voltage) as one input. After setting, apply a voltage to the gate as another input, apply a constant voltage to the drain (or source), and ground the source (or drain); finally, measure the current flowing through the source and drain and the output voltage through a semiconductor parameter analyzer to verify the specified logic relationship between the input voltage and the output voltage.

[0022] Furthermore, the appropriate resistance value of the RRAM is the matching resistor required for the corresponding logic function, the voltage pulse signal applied to the gate is the voltage pulse that enables the ferroelectric material to achieve polarization reversal, the constant voltage applied to the drain (or source) is the voltage that enables the FeFET to operate in the linear region, and the output voltage is the voltage at the intermediate node connecting the RRAM and the FeFET.

[0023] Compared to traditional CMOS logic gates, the reconfigurable logic gate based on the FeFET+RRAM structure of this invention utilizes the polarization state of the ferroelectric field-effect transistor as an input, thereby achieving dual inputs for a single transistor, which greatly reduces circuit area and power consumption. The reconfigurable logic gate of this invention is fabricated by integrating FeFET and RRAM, with a simple process structure and compatibility with CMOS processes. The reconfigurable logic gate of this invention utilizes the resistive switching characteristics of RRAM to achieve its reconfigurability (different logic functions can be achieved by adjusting the RRAM resistance), and can realize a large number of logic functions, thus having a broader prospect for practical applications. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a FeFET sample structure used to fabricate reconfigurable logic gate structures.

[0025] Figure 2 (a) is a schematic diagram of growing an oxide passivation layer on a FeFET sample.

[0026] Figure 2 (b) is a schematic diagram of etching to form a via on the passivation layer.

[0027] Figure 2 (c) is a schematic diagram of the fabrication of the RRAM bottom electrode layer in the through-hole.

[0028] Figure 3 (a) is a schematic diagram of the fabrication of the RRAM resistive switching dielectric layer.

[0029] Figure 3 (b) is a schematic diagram of the fabrication of the top electrode layer of the RRAM.

[0030] Figure 3 (c) is a schematic diagram of the RRAM pattern formed by photolithography.

[0031] Figure 4 (a) is a side view of the reconfigurable logic gate test circuit structure.

[0032] Figure 4 (b) is a top view of the reconfigurable logic gate test circuit structure.

[0033] Figure 5 This is a schematic diagram for testing the electrical input-output characteristics of a reconfigurable logic gate.

[0034] In the figure: 10—Oxide passivation layer, 11—Bottom electrode layer, 20—Resistive switching dielectric layer, 21—Top electrode layer, 22—FeFET source, 31—FeFET gate. Detailed Implementation

[0035] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] This invention relates to a reconfigurable logic gate based on a FeFET+RRAM structure, comprising two parts: a FeFET and an RRAM. The FeFET includes a silicon substrate, an oxide layer, a ferroelectric layer, a source electrode, a drain electrode, and a gate layer. The RRAM includes a top electrode layer, a resistive switching dielectric layer, and a bottom electrode layer. The RRAM is integrated above the drain electrode of the FeFET. Figure 3 (c) It should be noted that the oxide layer material includes, but is not limited to, silicon oxide, aluminum oxide or hafnium oxide; the ferroelectric layer material includes, but is not limited to, hafnium zirconium oxide, bismuth titanate or lead zirconate titanate; the source and drain electrodes are electrode materials that form ohmic contacts with the silicon substrate; the electrode materials include, but are not limited to, aluminum, nickel, gold or tungsten; the gate layer material includes, but is not limited to, aluminum, nickel, gold or tungsten; the electrode layer material of the RRAM includes, but is not limited to, aluminum, tungsten, platinum or titanium; and the resistive switching dielectric layer material includes, but is not limited to, titanium oxide, zinc oxide, hafnium oxide or germanium selenide.

[0037] The reconfigurable logic gate of this invention is based on the FeFET+RRAM structure. It uses the ferroelectric polarization state (manifested as threshold voltage) stored in the ferroelectric layer of the FeFET as one input and the voltage applied to the gate of the FeFET as another input. It then uses a suitable resistor to pull up the gate to realize the function of a dual-input logic gate. In addition, the reconfigurable logic gate utilizes the resistive switching characteristics of the RRAM. After adjusting the RRAM to a suitable resistance value, it serves as the pull-up resistor for the FeFET, thereby realizing different logic functions of the structure and demonstrating the reconfigurability of the FeFET+RRAM structure.

[0038] The method for fabricating reconfigurable logic gates based on the FeFET+RRAM structure of this invention includes the following steps:

[0039] (1) In such Figure 1 An oxide passivation layer 10 is deposited on the drain of the FeFET shown, and a via is etched on the passivation layer 10 for material deposition.

[0040] This embodiment first uses atomic layer deposition to prepare an oxide passivation layer on the drain of the FeFET. The oxide deposition thickness is tens to hundreds of nanometers. Figure 2 As shown in (a); then, the passivation layer 10 is etched using a wet etching method with inorganic acids such as hydrofluoric acid, hydrochloric acid, or sulfuric acid, to a depth of tens to hundreds of nanometers, as shown in (a). Figure 2 As shown in (b), a via is formed on the passivation layer 10.

[0041] (2) Sputter the bottom electrode layer 11 in the through hole, deposit the resistive switching dielectric layer 20, and sputter the top electrode layer 21.

[0042] In this embodiment, the RRAM bottom electrode layer 11 is prepared in the etched via using magnetron sputtering (or electron beam evaporation, thermal evaporation). Figure 2 As shown in (c), the thickness of the bottom electrode layer 11 is 1 nanometer to 200 nanometers; then, an atomic layer deposition method is used to deposit a resistive switching dielectric layer 20 on the bottom electrode layer 11 and the passivation layer 10. The material thickness of the resistive switching dielectric layer 20 is 1 nanometer to 200 nanometers. Figure 3 As shown in (a); finally, a top electrode layer 21 is deposited on the resistive switching dielectric layer 20 using magnetron sputtering (or electron beam evaporation, thermal evaporation). The material thickness of the top electrode layer 21 is approximately 1 nanometer to 200 nanometers. Figure 3 As shown in (b).

[0043] (3) The top electrode layer and resistive switching dielectric layer are formed by photolithography and etching to remove the unwanted patterned parts, thereby forming a MIM (metal-dielectric layer-metal) structure, thus realizing the integration of FeFET and RRAM, and forming a reconfigurable logic gate based on the FeFET+RRAM structure.

[0044] This embodiment employs plasma etching to perform photolithography and etching on the prepared material to complete the fabrication of the MIM structure. The etching depth is the sum of the thicknesses of the top electrode layer and the resistive switching layer. Figure 3 As shown in (c).

[0045] The method of using the reconfigurable logic gates based on the FeFET+RRAM structure of this invention is as follows:

[0046] like Figure 4 (a) and Figure 4 As shown in (b), firstly, a voltage V is applied to the top electrode layer 21 of the RRAM in the structure according to the logic function to be implemented. d The bottom electrode layer 11 is grounded, and the circuit matching resistor value corresponding to the RRAM setting adjustment logic function is set. Then, a voltage pulse signal is applied to the gate 31 of the FeFET to set the polarization switching state of the FeFET ferroelectric layer and use it as an input. Then, a voltage is applied to the gate 31 of the FeFET (as another input), and a constant voltage is applied to the top electrode layer 21 of the RRAM (or the source 22 of the FeFET). The source 22 of the FeFET (or the top electrode layer 21 of the RRAM) is grounded. At the same time, the current flowing through the source and drain is measured by a semiconductor parameter analyzer and the output voltage of the logic gate is calculated, thereby verifying that there is a specified logical relationship between the input voltage signal and the output voltage signal.

[0047] The appropriate resistance value of the RRAM is the matching resistor required for the corresponding logic function. The voltage pulse signal applied to the gate is the voltage pulse that enables the ferroelectric material to achieve polarization reversal. The constant voltage applied to the drain (source) is the voltage that enables the FeFET to operate in the linear region. The voltage at the intermediate node connecting the RRAM and the FeFET is taken as the output voltage of the logic gate.

[0048] In another embodiment of the present invention, the input-output curve of the reconfigurable logic gate in the AND gate operating state is measured. The resistance of the RRAM in the measurement circuit is set to 1.5V and 2.6MΩ. The voltage pulse used for the polarization reversal of the FeFET ferroelectric layer in the measurement circuit is +4V / 500ms (input "1") or -3V / 500ms (input "0"). The gate input voltage of the FeFET in the measurement circuit is 2V (input "1") or 0V (input "0"). The top electrode of the RRAM is grounded, and a voltage of 2V is applied to the source of the FeFET. The measurement time range is 5–15s. The formula for calculating the output voltage of the reconfigurable logic gate is:

[0049] V out =I d ×R RRAM

[0050] Among them: I d R is the current flowing through the source and drain of the FeFET. RRAM This is the resistance value of the RRAM.

[0051] like Figure 5 The diagram shows the output voltage results of the reconfigurable logic gates of this invention for different inputs. The embedded table in the figure is the logic truth table of the AND gate. Figure 5 It can be seen that the reconfigurable logic gate of the present invention can correctly realize the required logic function.

[0052] Therefore, it can be seen that the reconfigurable logic gate based on the FeFET+RRAM structure of this invention, compared with the traditional CMOS logic gate, utilizes the polarization state of the ferroelectric field-effect transistor as an input, thereby realizing dual input of a single transistor, which greatly reduces the circuit area and power consumption. The reconfigurable logic gate is fabricated by integrating FeFET and RRAM, with a simple process structure and compatibility with CMOS process. In addition, the reconfigurable logic gate of this invention utilizes the resistive switching characteristics of RRAM to achieve its reconfigurability (different logic functions can be achieved by adjusting the RRAM resistance), and can realize a large number of logic functions, with a wider range of practical application prospects.

[0053] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A reconfigurable logic gate based on a FeFET+RRAM structure, characterized in that: It consists of two parts: FeFET and RRAM. The FeFET includes three sets of electrodes: active, drain, and gate. The RRAM is integrated on the drain of the FeFET and consists of a bottom electrode layer, a resistive switching dielectric layer, and a top electrode layer from bottom to top. The reconfigurable logic gate uses the ferroelectric polarization state stored in the ferroelectric layer of the FeFET as one input and the voltage applied to the gate of the FeFET as another input, thereby realizing the function of a dual-input logic gate. In addition, the reconfigurable logic gate utilizes the resistive switching characteristics of RRAM, and after adjusting the RRAM to a suitable resistance value, it serves as the pull-up resistor of the FeFET, thereby realizing different logic functions and demonstrating its reconfigurability. The source and drain electrodes in the FeFET are electrode materials that form ohmic contacts with the silicon substrate. The electrode materials are aluminum, nickel, gold, or tungsten, and the gate material is also aluminum, nickel, gold, or tungsten. The electrode layer material in the RRAM is made of aluminum, tungsten, platinum or titanium, and the resistive switching dielectric layer material is made of titanium oxide, zinc oxide, hafnium oxide or germanium selenide.

2. A method for preparing a reconfigurable logic gate as described in claim 1, comprising the following steps: (1) An oxide passivation layer is deposited on the drain of the FeFET using atomic layer deposition, and an inorganic acid wet etching method is used to form a through hole for material deposition. (2) A bottom electrode layer, a resistive switching dielectric layer and a top electrode layer are sequentially prepared in the through hole. The bottom electrode layer and the top electrode layer are prepared by magnetron sputtering, electron beam evaporation or thermal evaporation, and the resistive switching dielectric layer is prepared by atomic layer deposition. (3) The material of the top electrode layer and the resistive switching dielectric layer, which are not required by photolithography and etching, are used to form a MIM structure, thereby realizing the integration of FeFET and RRAM and forming a reconfigurable logic gate based on the FeFET+RRAM structure; wherein the etching process adopts the plasma etching method.

3. A method of using the reconfigurable logic gate as described in claim 1, characterized in that: First, to achieve the required logic function, a voltage is applied to the top electrode layer of the RRAM, and the bottom electrode layer is grounded, setting the RRAM to an appropriate resistance value. Then, a voltage pulse signal is applied to the gate of the FeFET to set the ferroelectric polarization state of the FeFET as one input. After setting, a voltage is applied to the gate as another input, a constant voltage is applied to the drain, and the source is grounded. Finally, the current flowing through the source and drain and the output voltage are measured using a semiconductor parameter analyzer to verify the specified logic relationship between the input voltage and the output voltage. The appropriate resistance value of the RRAM is the matching resistor required for the corresponding logic function. The voltage pulse signal applied to the gate is the voltage pulse that enables the ferroelectric material to achieve polarization reversal. The constant voltage applied to the drain is the voltage that enables the FeFET to operate in the linear region. The output voltage is taken as the voltage at the intermediate node connecting the RRAM and the FeFET.

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