Gate driving circuit, circuit driving method, driving substrate and display device

Abstract

This application provides a gate driving circuit, a circuit driving method, a driving substrate, and a display device. The gate driving circuit includes a charging unit, a reset unit, an output unit, and a release unit. The release unit is configured to be turned on when the gate driving circuit is powered off and a low-level turn-on voltage is applied, and to output the high-level turn-on voltage generated by the power-off of the charging unit to the outside of the gate driving circuit, so that both the output unit and the reset unit release their respective residual charges. The high-level turn-on voltage exceeds a preset high level. Therefore, this solution can release the pulled-up high-level turn-on voltage and fully release the residual charge after power-off.

Description

Technical Field

[0001] The embodiments of this application relate to the technical field, and in particular to a gate driving circuit, a circuit driving method, a driving substrate, and a display device. Background Technology

[0002] In the relevant gate drive circuit, after the gate drive circuit has experienced multiple power outages, the charge in the circuit cannot be released. That is to say, there is a point where the voltage remains at a high level after the power is turned off and cannot be reduced. This will cause the electrical characteristics of the transistor in the gate drive circuit to drift, such as the threshold voltage drifting, which in turn will cause the transistor to fail to turn on normally.

[0003] When a transistor fails to turn on properly, it can cause abnormal output of the gate drive circuit, which in turn can lead to image display failures on the display panel, such as screen flickering, ghosting, or white screen.

[0004] Therefore, a solution is needed that can promptly release the high voltage inside the gate drive circuit after it is powered off. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a gate driving circuit, a circuit driving method, a driving substrate, and a display device.

[0006] For the purposes described above, this application provides a gate driving circuit, including a charging unit, a reset unit, and an output unit, and further includes a release unit;

[0007] The release unit is configured to be turned on when the gate drive circuit is de-energized and a low-level turn-on voltage is applied, and to output the high-level turn-on voltage generated by the power-off of the charging unit to the outside of the gate drive circuit, so that both the output unit and the reset unit release their respective residual charges; wherein the high-level turn-on voltage exceeds a preset high level.

[0008] Furthermore, the gate drive circuit also includes:

[0009] Circuit output port and bootstrap capacitor;

[0010] The bootstrap capacitor has one end electrically connected to both the charging unit and the output unit, and the other end electrically connected to the circuit output port. It is configured to apply a bootstrap voltage to the output unit after the gate drive circuit is powered off, so as to turn on the output unit.

[0011] The circuit output port is electrically connected to the output unit and is configured to output the remaining charge released by the output unit to the outside of the gate drive circuit.

[0012] Furthermore, the gate drive circuit also includes a low-level input port and at least one clock signal port; the release unit includes at least one first transistor;

[0013] The low-level input port is electrically connected to the first transistor and is configured to, after the gate drive circuit is powered off, pull the low-level turn-on voltage up to the threshold voltage of the first transistor and apply the pulled-up low-level turn-on voltage to the first transistor.

[0014] The first transistor is electrically connected to both the charging unit and the clock signal port, and is configured to turn on when a low-level turn-on voltage is applied after being pulled high, and to output the high-level turn-on voltage generated by the charging unit to the outside of the gate drive circuit through the clock signal port.

[0015] Furthermore, the gate drive circuit also includes at least two clock signal ports;

[0016] The two clock signal ports are configured to each receive a clock signal from outside the gate drive circuit, and the clock signals received by each other are signal pairs with the same period and opposite phases of high and low voltages.

[0017] The release unit further includes at least two first transistors, each of which is electrically connected to the charging unit and the low-level input port, and the two first transistors are respectively connected to different clock signal ports;

[0018] The two first transistors are configured such that when a low-level turn-on voltage is applied after being pulled high, the first transistor connected to the clock signal with a low voltage phase is turned on, and the high-level turn-on voltage generated by the charging unit is output to the outside of the gate drive circuit.

[0019] Furthermore, each first transistor includes:

[0020] First gate, first source, and first drain;

[0021] The first source of each of the two first transistors and the charging unit are electrically connected to each other and are configured such that the charging unit applies the high-level turn-on voltage.

[0022] The first drain of each of the two first transistors is connected to different clock signal ports;

[0023] The first gate of each of the two first transistors is electrically connected to the low-level input port and is configured to turn on the first drain of the clock signal connected to the low-voltage phase when a low-level turn-on voltage is applied, and output the high-level turn-on voltage to the outside of the gate drive circuit through the clock signal port corresponding to the low-voltage phase clock signal.

[0024] Furthermore, the gate drive circuit also includes a reset signal port, and is configured to receive a reset voltage from outside the gate drive circuit and apply it to the first sub-unit;

[0025] The reset unit includes a first subunit, a second subunit, a third subunit, and a fourth subunit;

[0026] The first sub-unit is electrically connected to the reset signal port and is configured to be turned on by the reset voltage before the gate drive circuit is powered off, and to discharge the charging unit and the output unit; when the charging unit is turned off due to power failure, it remains off after being driven by the reset voltage.

[0027] The second subunit is electrically connected to the first subunit, and is also electrically connected to the charging unit and the circuit output port. It is configured to, after the charging unit is turned off, be driven by the third subunit to release the remaining charge of all subunits in the reset unit to the circuit output port.

[0028] The third subunit is electrically connected to the at least one clock signal port and to the second subunit, and is configured to be turned on by the clock signal port, and to drive the second subunit to turn on after being turned on;

[0029] The fourth subunit is electrically connected to the low-level input port, and is also electrically connected to the second and third subunits. It is configured to be turned on by the charging unit and discharge to the low-level input port before the gate drive circuit is powered off; after the charging unit is turned off, the fourth subunit is turned off and stops discharging.

[0030] Furthermore, the second sub-unit includes at least two third transistors;

[0031] One of the third transistors is electrically connected to the charging unit and is configured to remain off after being driven by the third sub-unit after the charging unit is turned off.

[0032] Another third transistor is electrically connected to the circuit output port and is configured to be turned on by the third sub-unit after the charging unit is turned off, and to release the remaining charge of all sub-units in the reset unit to the circuit output port.

[0033] Based on the same inventive concept, this application also provides a circuit driving method for driving the gate driving circuit described in any of the above items, the method comprising:

[0034] When the gate drive circuit is de-energized and a low-level turn-on voltage is applied, it is turned on and outputs the high-level turn-on voltage generated by the power-off of the charging unit to the outside of the gate drive circuit, so that the output unit and the reset unit release their respective residual charges; wherein, the high-level turn-on voltage exceeds the preset high level.

[0035] Based on the same inventive concept, this application also provides a driving substrate, which includes the gate driving circuit described in any of the above items.

[0036] Based on the same inventive concept, this application also provides a display device, which includes the driving substrate described above.

[0037] As can be seen from the above, the gate driving circuit, circuit driving method, driving substrate and display device provided in this application, based on the condition that the GOA unit is powered off, comprehensively consider the high-level turn-on voltage applied by the charging unit to the release unit and the output unit, and use a low-level turn-on voltage to turn on the release unit, so that the high-level turn-on voltage can be discharged to the outside of the GOA unit through the release unit, avoiding the output unit from being affected by the high gate bias voltage, thereby avoiding the threshold voltage of the output unit from drifting, and after the high-level turn-on voltage is released, the remaining charge inside the output unit and the reset unit can be released to the outside of the GOA unit. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a first circuit diagram of the gate driving circuit according to an embodiment of this application;

[0040] Figure 2 This is a second circuit diagram of the gate drive circuit according to an embodiment of this application;

[0041] Figure 3 This is a third circuit diagram of the gate driving circuit according to an embodiment of this application;

[0042] Figure 4 This is a fourth circuit diagram of the gate driving circuit according to an embodiment of this application;

[0043] Figure 5 This is the fifth circuit diagram of the gate driving circuit in an embodiment of this application;

[0044] Figure 6 This is the sixth circuit diagram of the gate driving circuit in an embodiment of this application;

[0045] Figure 7 This is the sixth circuit diagram of the gate driving circuit in an embodiment of this application;

[0046] Figure 8 This is a signal timing diagram of the gate drive circuit in an embodiment of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0048] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] As described in the background section, the relevant gate drive circuits are still difficult to meet the needs of products in actual use.

[0050] In the process of implementing this application, the applicant discovered that the main problem with the relevant gate drive circuit is that after the gate drive circuit has undergone multiple power outages, the charge at a certain point in the circuit cannot be released. In other words, the voltage at that point will remain at a high level after the power is turned off and cannot be reduced. Based on this, the electrical characteristics of the transistor in the gate drive circuit will drift, such as the threshold voltage will drift, which will cause the transistor to fail to turn on normally.

[0051] Furthermore, when the transistor fails to turn on properly, it will cause abnormal output of the gate drive circuit, which in turn will cause image display failure on the display panel, such as screen distortion, ghosting, or white screen.

[0052] At the same time, the inability of the transistor to turn on properly will also prevent the gate drive circuit from properly releasing the internal residual charge after power is turned off, thereby further aggravating the fault or causing other faults.

[0053] In the embodiments of this application, such as Figure 1 As shown, Figure 1 The gate drive circuit shows the circuit of a GOA cell (gate drive integrated cell in gate drive integrated array substrate) in a GOA substrate (gate drive integrated array substrate), that is, the gate drive circuit, which is the Nth level cell in the array substrate.

[0054] like Figure 1 As shown, it includes a charging unit 101, a reset unit 102, an output unit 103, a bootstrap capacitor C1, a high-level input port 105, a circuit output port 106, a low-level input port 107, a first clock signal port 1081, a second clock signal port 1082, and a reset signal port 109.

[0055] The high-level input port 105 receives the output of the previous stage GOA unit on the GOA substrate. In other words, the high-level voltage input of the N-stage GOA unit is the output of the N-1 stage GOA unit, and transmits the high-level turn-on voltage into the GOA unit. Under normal circumstances, the high-level turn-on voltage is Vgh.

[0056] Furthermore, Figure 1 The output of the N-level GOA unit in the circuit will then output voltage to the N+1 level GOA unit.

[0057] Furthermore, Figure 1 The reset signal port 109 of the N-level GOA unit will receive the output voltage of the N+1-level GOA unit and use it as the reset voltage of the N-level GOA unit.

[0058] Furthermore, the low-level input port 107, the first clock signal port 1081, and the second clock signal port 1082 all receive the corresponding voltage or voltage signal from outside the GOA unit circuit and transmit it to the inside of the GOA unit circuit.

[0059] The low-level input port 107 provides a low-level enable voltage to the GOA unit. The first clock signal port 1081 and the second clock signal port 1082 both provide clock signals to the GOA unit. The clock signals provided by the first clock signal port 1081 and the clock signals provided by the second clock signal port 1082 are a pair of signals with the same period and opposite phases of high and low voltages. The low voltage is the same as the low-level enable voltage of the low-level input port 107, and the high voltage is the same as Vgh. The phases of the high voltage and the low voltage each occupy half of the phase.

[0060] Furthermore, the charging unit 101 includes a TFT (field-effect transistor) M1, and a high-level turn-on voltage is input to it through the high-level input port 105.

[0061] The reset unit 102 includes multiple TFTs: M2, M4, M10, M11, M5, M9, M6 and M8.

[0062] In the multiple TFTs of the reset unit 102, M2 and M4 form the first sub-unit, M10 and M11 form the second sub-unit, M5 and M9 form the third sub-unit, and M6 and M8 form the fourth sub-unit.

[0063] In this subunit, M2 and M4 are both electrically connected to the reset signal port 109 to obtain the reset voltage; M2 and M4 in the first subunit, M10 and M11 in the second subunit, and M8 and M6 in the fourth subunit are all electrically connected to the low-level input port 107; and M5 and M9 in the third subunit are electrically connected to the second clock signal port 1082.

[0064] Furthermore, the output unit 103 includes a TFT M3, such as Figure 1 As shown, M3 is electrically connected to the first clock signal port 1081 and the circuit output port 106.

[0065] Furthermore, the reset unit 102 is electrically connected to the charging unit 101; the output unit 103 is electrically connected to both the charging unit 101 and the reset unit 102; and the release unit 104 is electrically connected to the charging unit 101, the reset unit 102, and the output unit 103.

[0066] Furthermore, such as Figure 1 As shown, one end of the bootstrap capacitor C1 is electrically connected to the charging unit 101, the reset unit 102, and the output unit 103, and the other end is electrically connected to the circuit output port 106.

[0067] Based on the above connection relationships, the following is formed: Figure 1 The circuit of the N-level GOA unit shown is as follows. Figure 1The dots in the diagram represent circuits that intersect at that point and are connected and conductive. Intersecting line segments without dots represent multiple intersecting circuits that are not connected and are not conductive.

[0068] exist Figure 1 In the GOA unit shown, after multiple power outages or power failures, since there is no input voltage at the high-level input port 105, M1 is cut off, and M2 and M10 are also cut off. This prevents the charge between M2 and M1 from being released. Figure 1 The charge at the PU point cannot be released, causing the PU to remain in a high voltage state.

[0069] Multiple power outages or power failures could include, for example, multiple power outages during long-term use, or multiple sudden power failures.

[0070] In some cases, the voltage at the PU point will exceed Vgh and can reach twice Vgh.

[0071] In this case, the high voltage of PU will be applied to the gate of M3, which means that M3 will be affected by a high gate bias voltage. Therefore, the threshold voltage of M3 will drift under the high gate bias voltage, thus making M3 unable to turn on normally.

[0072] like Figure 1 As shown, since the drain of M3 is connected to the circuit output port 106, the inability of M3 to turn on properly will cause the output of the N-level GOA unit to the outside of the circuit to be abnormal.

[0073] It can be seen that when M3 fails to turn on normally, the output of the GOA unit becomes abnormal, which in turn leads to the image display failure of the display panel.

[0074] Furthermore, in Figure 1 In the circuit of the GOA unit shown, after multiple power outages, not only does the output unit 103 malfunction, but other problems also occur. For example, the reset unit 102 may experience problems such as abnormal discharge of residual charge.

[0075] Specifically, after power failure, residual charge will remain in the reset unit 102, and the residual charge needs to be released outside the N-level GOA unit.

[0076] However, since the turn-on voltage applied to the gate of M11 comes from Figure 1 The voltage at the PD point in the circuit is the voltage applied to the GOA unit by the second clock signal port 1082, after passing through M5 and M9. Therefore, when the voltage applied to the second clock signal port 1082 is a high-level voltage Vgh, the turn-on voltage applied to M11 is:

[0077] Threshold voltage of Vgh-M5 - Threshold voltage of M9

[0078] Based on this, it can be assumed that the gate voltage applied to M11 is too small, making it difficult to fully turn on M11. Therefore, the degree of conduction of M11 is also smaller than when it is fully turned on, resulting in less residual charge released by M11, which weakens the ability to release residual charge in the GOA cell.

[0079] Based on this, one or more embodiments of this application provide a gate driving circuit that releases a high-level turn-on voltage based on a release unit 104 composed of transistors, thereby enabling the output unit 103 to turn on normally and allowing the entire gate driving circuit to output normally.

[0080] The embodiments of this application are described in detail below with reference to the accompanying drawings.

[0081] refer to Figure 2 A gate driving circuit according to one embodiment of this application includes: a charging unit 101, a reset unit 102 and an output unit 103, characterized in that it further includes a release unit 104;

[0082] The release unit 104 is configured to be turned on when the gate drive circuit is de-energized and a low-level turn-on voltage is applied, and to output the high-level turn-on voltage generated by the power-off of the charging unit 101 to the outside of the gate drive circuit, so that the output unit 103 and the reset unit 102 release their respective residual charges; wherein the high-level turn-on voltage exceeds a preset high level.

[0083] In this embodiment, with Figure 2 The circuit of the N-level GOA unit is shown as a specific example.

[0084] Figure 2 The circuit of the N-level GOA unit shown includes a charging unit 101, a reset unit 102, a release unit 104, and an output unit 103.

[0085] The reset unit 102 is electrically connected to the charging unit 101; the output unit 103 is electrically connected to both the charging unit 101 and the reset unit 102; and the release unit 104 is electrically connected to the charging unit 101, the reset unit 102, and the output unit 103.

[0086] In some embodiments, the charging unit 101 may include at least one TFT.

[0087] The TFT is electrically connected to the high-level input port 105, the reset unit 102, the release unit 104, and the output unit 103.

[0088] Specifically, such as Figure 2 As shown, taking M1 as a specific example, the gate and source of M1 are connected to the high-level input port 105, and the drain is connected to the reset unit 102, the release unit 104 and the output unit 103.

[0089] Furthermore, Figure 2 The GOA unit shown also includes a high-level input port 105, a low-level input port 107, and a circuit output port 106.

[0090] In this embodiment, the circuit of the N-level GOA unit is in a state of power failure or power outage again after experiencing multiple power outages or power cuts.

[0091] Therefore, after the GOA unit is powered off, the charging unit 101 is in a cut-off state because no high-level turn-on voltage is applied to the charging unit 101.

[0092] Furthermore, after the GOA unit is powered off, although the charging unit 101 is in a cut-off state, due to the presence of residual charge, the charging unit 101 will still convert the residual charge into voltage and apply it to the output unit 103 and the release unit 104 connected to it.

[0093] In other words, after the GOA unit is powered off, the charging unit 101 can still charge the output unit 103 and the release unit 104.

[0094] Specifically, before the power is cut off, when the charging unit 101 is turned on, Figure 2 The voltage of the PU point connected to the output of the charging unit is at a high level, that is, the state of Vgh, and a high-level turn-on voltage equivalent to Vgh is applied to the output unit 103. When the power is off, the PU point is still in the state of high-level turn-on voltage.

[0095] Furthermore, after the GOA unit is powered off, due to the presence of residual charge, the high-level turn-on voltage of the PU point will be further increased, and the increased high-level turn-on voltage will exceed Vgh, and can reach up to twice Vgh.

[0096] Furthermore, such as Figure 8 The timing diagram shown indicates that, prior to the power outage, Figure 2 The high-level input port 105 applies a high-level turn-on voltage to M1. At this time, the PU point is at a high-level turn-on voltage. When the power is off, the high-level turn-on voltage applied by the high-level input port 105 becomes a low level. Based on this, M1 is turned off, and the voltage of the PU point rises again to 2Vgh.

[0097] Furthermore, after the power outage, Figure 2The low-level enable voltage input to the GOA unit via the low-level input port 107 will be pulled high.

[0098] Specifically, such as Figure 8 As shown, the low-level turn-on voltage applied to the low-level input port 107 experiences a brief rise after the power-off moment.

[0099] Furthermore, such as Figure 2 As shown, the low-level input port 107 will be pulled up by a low-level turn-on voltage and applied to the release unit 104.

[0100] Based on this, the release unit 104 will be turned on after the aforementioned low-level turn-on voltage is applied, and after being turned on, it will release the pulled-up high-level turn-on voltage to the outside of the N-level GOA unit.

[0101] Furthermore, since the high-level turn-on voltage pulled up at the aforementioned PU point is released by the release unit 104, therefore, as Figure 8 As shown, the high-level turn-on voltage of 2Vgh at the PU point will quickly drop to a low level, meaning that the voltage or residual charge at the PU point is released.

[0102] Based on this, the high-level turn-on voltage equivalent to 2Vgh applied to the output unit 103 will be eliminated, and the output unit 103 will no longer be subjected to high bias voltage, and the threshold voltage of the output unit 103 will not drift.

[0103] Therefore, the output unit 103 can output voltage normally or the residual charge of the output unit 103 itself, thereby avoiding output abnormalities at the circuit output port 106 of the N-level GOA unit.

[0104] Furthermore, in Figure 2 After the N-level GOA unit is powered off, the reset unit 102 can release its remaining charge to the outside of the circuit of the GOA unit through the circuit output port 106.

[0105] As can be seen, based on the set release unit 104, the high-level turn-on voltage pulled up in the N-level GOA circuit can be released to avoid the output unit 103 being affected by the high bias voltage, thereby avoiding abnormal output of the N-level GOA unit.

[0106] In another embodiment of this application, the gate driving circuit further includes:

[0107] Circuit output port 106 and bootstrap capacitor C1;

[0108] The bootstrap capacitor C1 has one end electrically connected to both the charging unit 101 and the output unit 103, and the other end electrically connected to the circuit output port 106. It is configured to apply a bootstrap voltage to the output unit 103 after the gate drive circuit is powered off, so as to turn on the output unit 103.

[0109] The circuit output port 106 is electrically connected to the output unit 103 and is configured to output the remaining charge released by the output unit 103 to the outside of the gate drive circuit.

[0110] In this embodiment, with Figure 3 As a specific example, based on the aforementioned Figure 2 In one embodiment, the circuit of the N-level GOA unit also includes a bootstrap capacitor C1.

[0111] The bootstrap capacitor is electrically connected to the charging unit 101, the reset unit 102, the output unit 103, and the circuit output port 106, and the bootstrap capacitor, the output unit 103, and the circuit output port 106 together form a bootstrap circuit.

[0112] Specifically, in Figure 3 In the example shown, one end of C1 is connected to the release unit 104, the output unit 103 and the charging unit 101, and the other end is connected to the circuit output port 106. The output unit 103 is connected to the circuit output port 106, thereby forming a bootstrap circuit, which can be affected by the charging unit 101 and the release unit 104.

[0113] In this embodiment, after the N-level GOA unit is powered off, as described in the previous embodiment, the high-level turn-on voltage applied to the output unit 103 is released. Since the voltage across C1 cannot change abruptly, under the bootstrap effect, C1 will apply a bootstrap voltage to the output unit 103.

[0114] Based on this, the output unit 103 can be turned on and output its remaining charge to the circuit output port 106.

[0115] In another embodiment of this application, the gate drive circuit further includes a low-level input port 107 and at least one clock signal port 108; the release unit 104 includes at least one first transistor;

[0116] The low-level input port 107 is electrically connected to the first transistor and is configured to, after the gate drive circuit is powered off, pull the low-level turn-on voltage up to the threshold voltage of the first transistor and apply the pulled-up low-level turn-on voltage to the first transistor.

[0117] The first transistor is electrically connected to both the charging unit 101 and the clock signal port 108, and is configured to turn on when a low-level turn-on voltage is applied after being pulled high, and to output the high-level turn-on voltage generated by the charging unit 101 to the outside of the gate drive circuit through the clock signal port 108.

[0118] In this embodiment, as Figure 4 As shown, the release unit 104 may consist of at least one first TFT (first transistor), and the N-level GOA unit is also provided with at least one clock signal port 108.

[0119] Among them, such as Figure 4 As shown, the first TFT M1213 of the release unit 104 has a first gate, a first source and a first drain. The first source is connected to the charging unit 101 through the PU point, the first drain is connected to any clock signal port 108, and the first gate can be electrically connected to the low-level input port 107.

[0120] Furthermore, based on the circuit connected above, as described in the previous embodiment, after the N-level GOA unit is powered off, the low-level turn-on voltage applied to the low-level input port 107 will be briefly pulled up, and the pulled-up low-level turn-on voltage will be applied to the first TFT M1213 connected to the low-level input port 107.

[0121] Based on this, the first TFT M1213 will be turned on. After it is turned on, the high-level turn-on voltage at PU will be applied to the first source of M1213 and released to the clock signal port 108 connected to it via the first drain.

[0122] It can be seen that, based on the first TFT in the release unit 104, the remaining charge in the N-level GOA unit, especially the high-level turn-on voltage at PU, will be released. In other words, the high-level turn-on voltage will no longer be applied to the output unit 103, thus eliminating the high bias voltage applied to the output unit 103.

[0123] In another embodiment of this application, the gate drive circuit further includes at least two clock signal ports 108;

[0124] The two clock signal ports 108 are configured to each receive a clock signal from outside the gate drive circuit, and the clock signals received by each other are signal pairs with the same period and opposite phases of high and low voltages.

[0125] The release unit 104 further includes at least two first transistors, each of which is electrically connected to the charging unit 101 and the low-level input port 107, and the two first transistors are respectively connected to different clock signal ports 108;

[0126] The two first transistors are configured such that when a low-level turn-on voltage is applied after being pulled high, the first transistor connected to the clock signal with a low voltage phase is turned on, and the high-level turn-on voltage generated by the charging unit 101 is output to the outside of the gate drive circuit.

[0127] In this embodiment, the release unit 104 may also include at least two identical first TFTs, and for each first TFT, the circuit of the GOA unit may also be provided with at least two clock signal ports 108.

[0128] Specifically, with Figure 5 As a specific example, the release unit 104 includes two first TFTs, M12 and M13, and the N-level GOA unit is provided with two clock signal ports 108, namely the first clock signal port 1081 and the second clock signal port 1082, and in Figure 5 The first clock signal port 1081 is designated as the CLK signal port, and the second clock signal port 1082 is designated as the CLKB signal port.

[0129] Furthermore, as described in the foregoing embodiments, combined with Figure 8 It can be determined that the clock signal emitted by the first clock signal port 1081 and the clock signal emitted by the second clock signal port 1082 are signal pairs with the same period and opposite phases of high and low voltages. That is, when the clock signal emitted by the first clock signal port 1081 is a high-level voltage, the clock signal emitted by the second clock signal port 1082 is a low-level voltage.

[0130] Among them, such as Figure 5 As shown, the second clock signal port 1082 is electrically connected to the reset unit 102 and applies a clock signal to the reset unit 102. The first clock signal port 1081 is electrically connected to the output unit 103 and applies a clock signal to the output unit 103.

[0131] In another embodiment of this application, each first transistor includes:

[0132] First gate, first source, and first drain;

[0133] The first source of each of the two first transistors and the charging unit are electrically connected to each other and are configured such that the charging unit applies the high-level turn-on voltage.

[0134] The first drain of each of the two first transistors is connected to different clock signal ports 108;

[0135] The first gate of each of the two first transistors is electrically connected to the low-level input port 107 and is configured such that when a low-level turn-on voltage is applied after being pulled high, the first drain connected to the low-voltage phase clock signal is turned on, and the high-level turn-on voltage is output to the outside of the gate drive circuit through the clock signal port 108 corresponding to the low-voltage phase clock signal.

[0136] In this embodiment, as Figure 5 As shown, the first clock signal port 1081 is connected to the first drain of M13, the second clock signal port 1082 is connected to the first drain of M12, and the first source of M12 is connected to the first source of M13. Both first sources are connected to the charging unit 101 through the PU point.

[0137] Furthermore, the first gate of M12 and the first gate of M13 are connected, and both first gates are connected to the low-level input port 107.

[0138] Furthermore, based on the circuit connected above, as described in the previous embodiment, after the N-level GOA unit is powered off, the low-level turn-on voltage applied to the low-level input port 107 will be briefly pulled up, and the pulled-up low-level turn-on voltage will be applied to the two first gates connected to the low-level input port 107.

[0139] Based on this, both M12 and M13 can be enabled.

[0140] Furthermore, since the high-level turn-on voltage applied to the first source of M12 and M13 is turned to low level, not both first TFTs in M12 and M13 can release the high-level turn-on voltage. Only the first TFT connected to the clock signal with a low-level voltage can be turned on and release the high-level turn-on voltage to the corresponding clock signal port 108.

[0141] It can be seen that by setting two first TFTs in the release unit 104, after the N-level GOA unit is powered off, since one of the first clock signal port 1081 and the second clock signal port 1082 is always in a low-level voltage state, the high-level turn-on voltage of the PU point can be continuously released to the outside of the GOA unit.

[0142] In another embodiment of this application, the output unit 103 includes at least one second transistor;

[0143] The second transistor includes a second gate electrically connected to the charging unit 101 and a second drain electrically connected to the circuit output port 106;

[0144] The second transistor is configured such that after the charging unit 101 applies a high-level turn-on voltage exceeding a preset high level to the second gate, before the high-level turn-on voltage is released, the threshold voltage of the second transistor drifts, the second transistor is turned off, and the second drain abnormally releases charge to the circuit output port 106.

[0145] In this embodiment, the output unit 103 may include at least one second TFT, wherein the second gate of the second TFT is connected to the charging unit 101 to charge the bootstrap capacitor when the GOA unit is not powered off.

[0146] Furthermore, the second source of the second TFT is electrically connected to the clock signal port 108, and the second drain is electrically connected to the circuit output port 106, so as to realize the discharge of the bootstrap capacitor through the circuit output port 106, and release its own residual charge through the circuit output port 106 after the GOA unit is powered off.

[0147] Furthermore, after the GOA unit is powered off, and before the release unit 104 releases the high-level turn-on voltage applied to the output unit 103, the high-level turn-on voltage will be applied to the output unit 103. It can be considered that the output unit 103 is subjected to a high bias voltage, which will cause the threshold voltage of the output unit 103 to drift, thereby preventing the output unit 103 from turning on normally.

[0148] exist Figure 6 In the specific example shown, the output unit 103 includes a second TFT M3, such as Figure 5 As shown, the second gate of M3 is electrically connected to the charging unit 101 through the PU point, and the second gate of M3 is also connected to one end of C1.

[0149] Furthermore, the second source of M3 is connected to the first clock signal port 1081, and the second drain of M3 is connected to the circuit output port 106.

[0150] In this embodiment, after the N-level GOA unit is powered off, the high-level turn-on voltage of the PU point will be applied to the gate of M3. As described in the previous embodiment, the high-level turn-on voltage at this time exceeds the preset high level Vgh and can reach a maximum of 2Vgh. Therefore, before the first TFT of the release unit 104 releases the high-level turn-on voltage, the second gate of M3 is in a high gate bias state, the threshold voltage of M3 will drift, and M3 will not be able to turn on normally, resulting in an output abnormality at the circuit output port 106 connected to the second drain of M3, which cannot release charge to the outside of the N-level GOA unit normally.

[0151] In other words, after the N-level GOA unit is powered off, the remaining charge of the output unit 103 cannot be released normally through the circuit output port 106.

[0152] In embodiments of this application, the gate drive circuit further includes a reset signal port 109, which is configured to receive a reset voltage from outside the gate drive circuit and apply it to the first sub-unit.

[0153] The reset unit 102 includes a first subunit, a second subunit, a third subunit, and a fourth subunit;

[0154] The first sub-unit is electrically connected to the reset signal port 109 and is configured to be turned on by the reset voltage before the gate drive circuit is powered off, and to discharge the charging unit 101 and the output unit 103; when the charging unit 101 is turned off due to power failure, it remains off after being driven by the reset voltage.

[0155] The second subunit is electrically connected to the first subunit, and is also electrically connected to the charging unit 101 and the circuit output port 106. It is configured to, after the charging unit 101 is turned off, be driven by the third subunit to release the remaining charge of all subunits in the reset unit 102 to the circuit output port 106.

[0156] The third subunit is electrically connected to the at least one clock signal port 108 and to the second subunit, and is configured to be turned on by the clock signal port 108, and to drive the second subunit to turn on after being turned on.

[0157] The fourth subunit is electrically connected to the low-level input port 107, and is also electrically connected to the second and third subunits. It is configured to be turned on by the charging unit 101 and discharge to the low-level input port 107 before the gate drive circuit is powered off. After the charging unit 101 is turned off, the fourth subunit is turned off and stops discharging.

[0158] In this embodiment, the reset unit 102 includes a first subunit, a second subunit, a third subunit, and a fourth subunit, and the GOA unit is also provided with a reset signal port 109 connected to the reset unit 102.

[0159] The reset signal port 109 is used to receive the reset voltage, which is provided by the next-level GOA unit. Specifically, the output of the next-level GOA unit is used as the reset voltage of the current GOA unit. The reset signal port 109 is applied to the reset unit 102 and specifically to the first sub-unit.

[0160] Furthermore, in addition to being connected to the reset signal port 109, the first sub-unit is also connected to the low-level input port 107, the charging unit 101, and the circuit output port 106.

[0161] Based on this, the first sub-unit can be turned on and off normally when the GOA unit is not powered off, so as to discharge the charging unit 101 and the output unit 103.

[0162] The reset voltage applied to the reset signal port 109 can drive the first sub-unit to turn on and off.

[0163] Furthermore, the second subunit is connected to the first subunit, and is also connected to the low-level input port 107, the charging unit 101, and the circuit output port 106.

[0164] Based on this, the second sub-unit can be turned on and off by the third sub-unit when the GOA unit is not powered off, so as to discharge the noise signal of the GOA unit and discharge the charging unit 101; after the GOA unit is powered off, that is, after the charging unit 101 is turned off, the second sub-unit can be turned on by the third sub-unit to release the remaining charge of all sub-units in the reset unit 102.

[0165] Furthermore, the third subunit is electrically connected to both the second and fourth subunits and is connected to at least one clock signal port 108.

[0166] Based on this, the clock signal port 108 can drive the third sub-unit to turn on and off, and after the third sub-unit is turned on, it can further drive the second sub-unit.

[0167] Furthermore, the fourth subunit is connected to the charging unit 101, the low-level input port 107, the third subunit, and the fourth subunit.

[0168] Based on this, when the GOA unit is not powered off, the charging unit 101 can drive the fourth sub-unit to turn on and off. After the fourth sub-unit is turned on, it can discharge the third sub-unit. However, when the GOA unit is powered off, that is, when the charging unit 101 is turned off, it cannot drive the fourth sub-unit, that is, the fourth sub-unit is turned off, and thus the third sub-unit cannot discharge through the fourth sub-unit.

[0169] Furthermore, the reset unit 102 also includes a discharge TFT driven by a low-level input port 107. The gate and source of the discharge TFT are both connected to the low-level input port 107, while the drain is connected to the circuit output port 106. The discharge TFT is also electrically connected to the first sub-unit, the second sub-unit, and the fourth sub-unit.

[0170] Based on this, when the low-level turn-on voltage is pulled high after the GOA unit is powered off, the discharge TFT can be turned on, so that the remaining charge in the reset unit 102 is released to the circuit output port 106 through the drain of the discharge TFT, and further released to the outside of the GOA unit.

[0171] exist Figure 7 In the specific example shown, the first sub-unit includes M2 and M4, the second sub-unit includes M10 and M11, the third sub-unit includes at least two third TFTs M5 and M9, and the fourth sub-unit includes M6 and M8. The discharge TFTs are... Figure 7 It is represented as M7.

[0172] Furthermore, M2 of the first sub-unit is connected to M1 through the PU point, while M4 is connected to the circuit output port 106. The gates of both M2 and M4 are connected to the reset signal port 109.

[0173] Based on this, when the N-level GOA unit is not powered off, the reset signal port 109 can control M2 to turn on in order to discharge M1, and control M4 to turn on in order to discharge the output unit 103.

[0174] Furthermore, after the N-level GOA unit is powered off, that is, after M1 is cut off, the reset signal port 109 cannot turn on M2 and M4. In other words, M2 cannot discharge to M1 or PU point, and M4 cannot discharge to output unit 103.

[0175] Furthermore, M10 of the second sub-unit is connected to M1 via the PU point, and M11 is connected to the circuit output port 106. Both M10 and M11 are also connected to the low-level input port 107, and the gates of M10 and M11 are connected via... Figure 7 The PD point in the middle is connected to the third sub-unit.

[0176] Based on this, when the N-level GOA unit is not powered off, M10 and M11 can be turned on by the third sub-unit to discharge the PD point; however, after the N-level GOA unit is powered off, M1 is cut off, so even if the third sub-unit applies voltage to M10, M10 cannot be turned on, while M11 can be turned on by the voltage applied by the third sub-unit.

[0177] Furthermore, M11 is also connected to M2 and M4 of the first sub-unit, M5 and M9 of the third sub-unit, and M8 and M6 of the fourth sub-unit. Therefore, after M11 is turned on, the remaining charge in each sub-unit will be released through the circuit output port 106.

[0178] Furthermore, the gate of the third sub-unit M9 is connected to the second clock signal, the gate of M5 is connected to M9, and M9 is connected to M8 of the fourth sub-unit, while M5 is connected to M6 of the fourth sub-unit. Therefore, M9 can be turned on by the second clock signal port 1082. After M9 is turned on, M5 is turned on by the drive of M9. After M5 is turned on, the PD point connected to the gates of M10 and M11 can be charged to drive M10 and M11 of the second sub-unit.

[0179] Furthermore, the gates of M6 and M8 in the fourth sub-unit are each connected to the charging unit 101 through the PU point and are also connected to the low-level input port 107.

[0180] Based on this, when M1 of the charging unit 101 is turned on, it can drive M8 and M6 to turn on, so as to discharge the third sub-unit. When M1 is turned off, M8 and M6 are also turned off, that is, the discharge of the third sub-unit is stopped.

[0181] Furthermore, the gate of M7 is connected to the low-level input port 107, and the drain of M7 is connected to the circuit output port 106. Therefore, after the N-level GOA cell is powered off, the low-level turn-on voltage of the low-level input port 107 is briefly pulled up. At this time, the pulled-up low-level turn-on voltage will be applied to the gate of M7 to drive M7 to turn on. After M7 turns on, the remaining charge in each sub-cell will pass through the drain of M7 and finally be released to the outside of the N-level GOA cell through the circuit output port 106.

[0182] As can be seen, by setting the discharge TFT, the reset unit 102 can release the remaining charge inside the reset unit 102 after the GOA unit is powered off.

[0183] As can be seen, the gate drive circuit of the embodiment of this application, based on the condition that the GOA unit is powered off, comprehensively considers the high-level turn-on voltage applied by the charging unit 101 to the release unit 104 and the output unit 103, and uses a low-level turn-on voltage to turn on the release unit 104, so that the high-level turn-on voltage can be released to the outside of the GOA unit through the release unit 104, avoiding the output unit 103 from being affected by the high gate bias voltage, thereby avoiding the threshold voltage of the output unit 103 from drifting, and after the high-level turn-on voltage is released, it can realize the release of the remaining charge inside the output unit 103 and the reset unit 102 to the outside of the GOA unit.

[0184] For ease of description, the above apparatus is described in terms of its functions, divided into various modules. Of course, in implementing the embodiments of this application, the functions of each module can be implemented in one or more software and / or hardware.

[0185] Based on the same inventive concept, and corresponding to the circuits of any of the above embodiments, embodiments of this application also provide a circuit driving method.

[0186] The circuit driving method is applied to the gate driving circuit in any of the foregoing embodiments, and specifically includes:

[0187] When the gate drive circuit is de-energized and a low-level turn-on voltage is applied, it is turned on and outputs the high-level turn-on voltage generated by the power-off of the charging unit to the outside of the gate drive circuit, so that the output unit and the reset unit release their respective residual charges; wherein, the high-level turn-on voltage exceeds the preset high level.

[0188] It should be noted that the charge recovery method of this application can be executed by a single device, such as a computer or server. The method of this embodiment can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this application, and the multiple devices will interact with each other to complete the method described.

[0189] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0190] Based on the same inventive concept, corresponding to the gate driving circuit of any of the above embodiments, this application also provides a driving substrate, the driving substrate including the gate driving circuit as described in any of the above embodiments.

[0191] Based on the same inventive concept, corresponding to the driving substrate of the above embodiments, this application also provides a display device, the display device including the driving substrate as described in any of the above embodiments.

[0192] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0193] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0194] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0195] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A gate drive circuit comprising a charging unit, a reset unit, and an output unit, characterized by, The release unit is configured to be turned on when the gate drive circuit is powered off and a low-level start voltage is applied, and output a high-level start voltage generated by the charging unit to the outside of the gate drive circuit to release the residual charges of the output unit and the reset unit; wherein the high-level start voltage exceeds a preset high level; The gate drive circuit further comprises a low-level input port and at least one clock signal port; the release unit comprises at least one first transistor; The low-level input port is electrically connected to the first transistor and is configured to pull up the low-level start voltage to the threshold voltage of the first transistor after the gate drive circuit is powered off, and apply the pulled-up low-level start voltage to the first transistor; The first transistor is electrically connected to the charging unit and the clock signal port, and is configured to be turned on when the pulled-up low-level start voltage is applied, and output the high-level start voltage generated by the charging unit to the outside of the gate drive circuit through the clock signal port; The gate drive circuit further comprises at least two clock signal ports; The two clock signal ports are configured to respectively receive a clock signal from the outside of the gate drive circuit, and the clock signals received by the two clock signal ports are a signal pair with the same period and opposite high-low voltage phases; The release unit further comprises at least two first transistors, each of which is electrically connected to the charging unit and the low-level input port, and the two first transistors are connected to different clock signal ports; The two first transistors are configured to turn on the first transistor connected to the clock signal of the low-voltage phase when the pulled-up low-level start voltage is applied, and output the high-level start voltage generated by the charging unit to the outside of the gate drive circuit. The gate drive circuit further comprises:

2. The gate drive circuit according to claim 1, characterized by A circuit output port and a bootstrap capacitor; The bootstrap capacitor has one end electrically connected to the charging unit and the output unit, and the other end electrically connected to the circuit output port, and is configured to apply a bootstrap voltage to the output unit to turn on the output unit after the gate drive circuit is powered off; The circuit output port is electrically connected to the output unit and is configured to output the residual charges released by the output unit to the outside of the gate drive circuit. Each first transistor comprises:

3. The gate drive circuit according to claim 1, characterized by A first gate, a first source and a first drain; The first source of each of the two first transistors and the charging unit are electrically connected to each other and are configured to be applied with the high-level start voltage by the charging unit; The first drain of each of the two first transistors is connected to a different clock signal port. ​ The first gate of each of the two first transistors is electrically connected to the low-level input port, and is configured to, when a low-level on voltage is applied after being pulled high, turn on the first drain connected with a low-voltage phase clock signal, and output the high-level on voltage to the outside of the gate drive circuit through a clock signal port corresponding to the low-voltage phase clock signal.

4. The gate drive circuit according to claim 1, characterized by The gate drive circuit further comprises a reset signal port, and is configured to accept a reset voltage from the outside of the gate drive circuit and apply the reset voltage to the first subunit. The reset unit comprises a first subunit, a second subunit, a third subunit and a fourth subunit. The first subunit is electrically connected to the reset signal port, and is configured to, before the gate drive circuit is powered off, be turned on by the reset voltage and discharge the charging unit and the output unit; and after the charging unit is turned off due to power off, remain turned off after being driven by the reset voltage. The second subunit is electrically connected to the first subunit, and is electrically connected to the charging unit and the circuit output port, and is configured to, after the charging unit is turned off, be driven by the third subunit to release the residual charge of all subunits in the reset unit to the circuit output port. The third subunit is electrically connected to the at least one clock signal port and the second subunit, and is configured to be turned on by the clock signal port and drive the second subunit to be turned on after being turned on. The fourth subunit is electrically connected to the low-level input port, and is electrically connected to the second subunit and the third subunit, and is configured to, before the gate drive circuit is powered off, be turned on by the charging unit and discharge the low-level input port; and after the charging unit is turned off, the fourth subunit is turned off and stops discharging.

5. The gate drive circuit according to claim 4, characterized in that, The second subunit comprises at least two third transistors. One of the third transistors is electrically connected to the charging unit, and is configured to, after the charging unit is turned off, remain turned off after being driven by the third subunit. The other third transistor is electrically connected to the circuit output port, and is configured to, after the charging unit is turned off, be turned on after being driven by the third subunit and release the residual charge of all subunits in the reset unit to the circuit output port.

6. A circuit driving method, characterized by, The method comprises: The method comprises: The gate drive circuit is powered off, and is turned on when a low-level on voltage is applied, and outputs a high-level on voltage generated by the charging unit due to power off to the outside of the gate drive circuit, so that the output unit and the reset unit release their respective residual charges; wherein the high-level on voltage exceeds a preset high level.

7. A drive substrate, characterized by, The driving substrate comprises a plurality of gate drive circuits as claimed in any of claims 1-5.

8. A display device, characterized by The driving substrate comprises a plurality of gate drive circuits as claimed in any of claims 1-5.

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