Pixel circuit and driving method thereof

Abstract

The present application provides a pixel circuit and a driving method thereof. In the pixel circuit, a driving circuit generates a conduction current according to a light emitting control signal. A first voltage adjuster adjusts a voltage level of a first control terminal according to the light emitting control signal, a third source driving signal, a first data voltage and a reference voltage, and generates a first driving current according to the voltage level of the first control terminal. A second voltage adjuster adjusts a voltage level of a second control terminal according to the first, second and fourth source driving signals, a second data voltage and the reference voltage, and generates a second driving current according to the voltage level of the second control terminal. In a first operation mode, the conduction current has a current value equal to that of the first driving current. In a second operation mode, the conduction current has a current value equal to the sum of the first driving current and the second driving current.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device, and in particular to a pixel circuit and a driving method thereof. BACKGROUND

[0002] In the prior art, the display panel is susceptible to the threshold voltage variation of the transistors in the pixel circuit, which degrades the display quality of the display panel.

[0003] In addition, when the pixel circuit operates in a display panel with different gray scales (e.g., a low gray scale state or a high gray scale state), the on current of the driving transistor is in a large current state, and the light emitting element is turned on for a long time, which results in excessive power consumption of the pixel circuit. Furthermore, the system low voltage in the pixel circuit is susceptible to the line resistance of the transmission path, which causes the end voltage of each pixel to be different, and thus the on current of the light emitting element in each pixel is erroneous.

[0004] Therefore, how to improve the threshold voltage variation of the transistors and effectively reduce the power consumption of the pixel circuit when the pixel circuit operates in a display panel with different gray scales to improve the display quality of the display panel is an important issue for those skilled in the art. SUMMARY

[0005] The present application provides a pixel circuit and a driving method thereof, which can effectively reduce the overall power consumption and improve the threshold voltage variation of the transistors in different operation modes to improve the display quality of the display panel.

[0006] The pixel circuit of the present application comprises a driving circuit, a first voltage regulator and a second voltage regulator. The driving circuit generates an on current according to a light emitting control signal. The first voltage regulator has a first control terminal, is coupled to the driving circuit, adjusts the voltage level of the first control terminal according to the light emitting control signal, a third source driving signal, a first data voltage and a reference voltage, and generates a first driving current according to the voltage level of the first control terminal. The second voltage regulator has a second control terminal, is coupled to the driving circuit, adjusts the voltage level of the second control terminal according to a first source driving signal, a second source driving signal, a fourth source driving signal, a second data voltage and a reference voltage, and generates a second driving current according to the voltage level of the second control terminal. In a first operation mode, the size of the on current is the current value of the first driving current, and in a second operation mode, the size of the on current is the current value of the sum of the first driving current and the second driving current.

[0007] The driving method of the pixel circuit of the present application comprises: causing the driving circuit to generate a conduction current according to a light-emitting control signal; causing the first voltage adjuster to adjust the voltage level of the first control end of the first voltage adjuster according to the light-emitting control signal, the third source driving signal, the first data voltage and the reference voltage, and to generate a first driving current according to the voltage level of the first control end; causing the second voltage adjuster to adjust the voltage level of the second control end of the second voltage adjuster according to the first source driving signal, the second source driving signal, the fourth source driving signal, the second data voltage and the reference voltage, and to generate a second driving current according to the voltage level of the second control end; and causing the size of the conduction current to be the current value of the first driving current in the first operation mode, and causing the size of the conduction current to be the current value of the sum of the first driving current and the second driving current in the second operation mode.

[0008] Based on the above, the pixel circuit according to the embodiments of the present application can determine the light-emitting brightness of the light-emitting element by only the main voltage adjuster in the low gray scale display state, and determine the light-emitting brightness of the light-emitting element by the additional voltage adjuster and the main voltage adjuster together in the high gray scale display state. In this way, the pixel circuit can control the gray scale state of the display picture by two current paths to reduce the cross voltage between the system high voltage and the system low voltage, and achieve the effect of improving power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic diagram of a pixel circuit according to an embodiment of the present application.

[0010] Figure 2 is a schematic diagram of a pixel circuit according to an embodiment of the present application. Figure 1 is a timing diagram when the pixel circuit according to the embodiment of the present application operates in the first and second operation modes.

[0011] Figures 3A to 3D is an equivalent circuit diagram when the pixel circuit according to the embodiment of the present application operates in the first operation mode. Figure 1

[0012] is an equivalent circuit diagram when the pixel circuit according to the embodiment of the present application operates in the second operation mode. Figures 4A to 4D Figure 1 is a flowchart of the driving method of the pixel circuit according to an embodiment of the present application.

[0013] Figure 5 REFERENCE NUMERALS:

[0014] 100: pixel circuit

[0015] 110: driving circuit

[0016] 110: driving circuit

[0017] ​120, 130: voltage regulator

[0018] C1-C3: capacitor

[0019] CT1, CT2: control terminal

[0020] CP: compensation phase

[0021] EM: emission control signal

[0022] EP: emission phase

[0023] EP1, EP2: sub-phase

[0024] ID: on current

[0025] I1, I2: drive current

[0026] LED: light emitting element

[0027] P1, P2: node

[0028] RP: reset phase

[0029] S1-S4: source drive signal

[0030] S510-S540: step

[0031] T1-T9: transistor

[0032] TD: drive transistor

[0033] TFR: pixel period

[0034] TP: turn-off phase

[0035] VREF: reference voltage

[0036] VL: low voltage

[0037] VSS: system low voltage

[0038] VDD: system high voltage

[0039] VDATA1, VDATA2: data voltage

[0040] VGH: gate high voltage

[0041] VGL: gate low voltage DETAILED DESCRIPTION

[0042] The term "coupled" (or connected) used in the detailed description of the specification (including the claims) can refer to any direct or indirect connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. In addition, wherever possible, the same reference numbers are used in the drawings and embodiments to represent the same or similar parts. Elements / components / steps using the same reference numbers or using the same terms in different embodiments can be referred to each other in the relevant description.

[0043] Figure 1 is a schematic diagram of a pixel circuit according to an embodiment of the present application. Please refer to Figure 1 In this embodiment, the pixel circuit 100 includes a driving circuit 110, a voltage adjuster 120, and a voltage adjuster 130. The driving circuit 110 includes a driving transistor TD and a light emitting element LED. The first end of the driving transistor TD is coupled to the voltage adjuster 120 and the voltage adjuster 130, and the control end of the driving transistor TD receives a light emitting control signal EM. The anode end of the light emitting element LED is coupled to the second end of the driving transistor TD, and the cathode end of the light emitting element LED is coupled to a system low voltage VSS.

[0044] Specifically, the driving circuit 110 of this embodiment can generate a conduction current ID according to the state of the light emitting control signal EM, and the driving circuit 110 can correspondingly light up the light emitting element LED according to the conduction current ID. The light emitting element LED of this embodiment can be, for example, an organic light emitting diode (OLED), a mini LED, or other micro light emitting element, and the present application is not particularly limited.

[0045] The voltage regulator 120 is coupled to the driving circuit 110. The voltage regulator 120 includes transistors T1-T5 and a capacitor C1. A first terminal of the transistor T1 is coupled to the system high voltage VDD, a second terminal of the transistor T1 is coupled to a node P1, and a control terminal of the transistor T1 receives an emission control signal EM. A first terminal of the transistor T2 (i.e., a switching transistor) is coupled to the system high voltage VDD, a second terminal of the transistor T2 is coupled to the driving circuit 110, and a control terminal of the transistor T2 is coupled to a control terminal CT1. A first terminal of the transistor T3 is coupled to a reference voltage VREF, a second terminal of the transistor T3 is coupled to the control terminal CT1, and a control terminal of the transistor T3 receives a source driving signal S3. A first terminal of the transistor T4 is coupled to the node P1, and a control terminal of the transistor T4 receives the source driving signal S3. A first terminal of the transistor T5 receives a source driving signal S2, a second terminal of the transistor T5 is coupled to a second terminal of the transistor T4, and a control terminal of the transistor T5 is coupled to a data voltage VDATA1. The capacitor C1 is coupled between the control terminal CT1 and the node P1.

[0046] In particular, the voltage regulator 120 of the present embodiment can adjust a voltage level of the control terminal (i.e., the control terminal CT1) of the transistor T2 according to the emission control signal EM, the source driving signal S3, the data voltage VDATA1, and the reference voltage VREF. Also, the voltage regulator 120 can generate the driving current II to the driving circuit 110 according to the voltage level of the control terminal CT1 when the pixel circuit 100 operates in the light emission phase of the first operation mode and the second operation mode.

[0047] In another aspect, the voltage regulator 130 includes transistors T6-T9 and capacitors C2-C3. A first terminal of the transistor T6 is coupled to a data voltage VDATA2, a second terminal of the transistor T6 is coupled to a node P2, and a control terminal of the transistor T6 receives a source driving signal S4. A first terminal of the transistor T7 is coupled to a low voltage VL, a second terminal of the transistor T7 is coupled to a control terminal CT2, and a control terminal of the transistor T7 receives a source driving signal S1. A first terminal of the transistor T8 is coupled to the driving circuit 110, a second terminal of the transistor T8 is coupled to the control terminal CT2, and a control terminal of the transistor T8 receives a source driving signal S2. A first terminal of the transistor T9 is coupled to the reference voltage VREF, a second terminal of the transistor T9 is coupled to the driving circuit 110, and a control terminal of the transistor T9 is coupled to the control terminal CT2. The capacitor C2 is coupled between the control terminal CT2 and the node P2. The capacitor C3 is coupled between the node P2 and the reference voltage VREF.

[0048] In particular, the voltage adjuster 130 can adjust the voltage level of the control terminal (i.e., the control terminal CT2) of the transistor T9 according to the source driving signal S1, the source driving signal S2, the source driving signal S4, the data voltage VDATA2, and the reference voltage VREF. Moreover, the voltage adjuster 130 can generate the driving current I2 to the driving circuit 110 according to the voltage level of the control terminal C2 when the pixel circuit 100 operates in the light emitting stage of the second operation mode.

[0049] It is worth mentioning that in the present embodiment, the pixel circuit 100 can receive the data voltage VDATA1 and the data voltage VDATA2 from a source driver (or a data driver) (not shown). The source driver (or the data driver) can generate the data voltage VDATA1 and the data voltage VDATA2 to the pixel circuit 100 according to the display requirement. For example, the data voltage VDATA1 can be a square wave signal with a voltage range between a second voltage value (e.g., 0 volt (V)) and a first voltage value (e.g., 6V), and the data voltage VDATA2 can be set to the second voltage value (e.g., 0V) or the first voltage value (e.g., 6V) according to the display requirement.

[0050] Further, when the pixel circuit 100 operates in the first operation mode according to the display requirement, the voltage adjuster 130 can receive the data voltage VDATA2 with the first voltage value (i.e., 6V) in the light emitting stage of the first operation mode. When the pixel circuit 100 operates in the second operation mode according to the display requirement, the voltage adjuster 130 can receive the data voltage VDATA2 with the second voltage value (i.e., 0V) in the light emitting stage of the second operation mode.

[0051] In which, the above-mentioned first operation mode can mean that the pixel circuit 100 operates in a low gray level display state, and the second operation mode can mean that the pixel circuit 100 operates in a high gray level display state. In other words, the present embodiment can change the operation mode or the display state of the pixel circuit 100 by switching the voltage state of the data voltage VDATA2.

[0052] It is worth mentioning that in the present embodiment, the transistor T2 and the transistor T5 are matched with each other. In which, the above-mentioned matching can mean that the sizes of the transistors are the same and / or the threshold voltages of the transistors are the same. In addition, in the design of the driving transistor TD and the transistors T1-T9, the driving transistor TD and the transistors T1-T9 can be taken as P-type transistors, but the present embodiment is not limited thereto.

[0053] Figure 2is in accordance with the present invention Figure 1 Timing diagrams of the pixel circuit of the embodiment when operating in the first and second operation modes. Please refer to Figure 2 In the present embodiment, one pixel period TFR of the pixel circuit 100 can be divided into a reset phase RP, a compensation phase CP, an emission phase EP, and a turn-off phase TP. The pixel circuit 100 can sequentially operate in the reset phase RP, the compensation phase CP, the emission phase EP, and the turn-off phase TP. The reset phase RP, the compensation phase CP, the emission phase EP, and the turn-off phase TP do not overlap with each other. Among them, the emission phase EP can include a sub-phase EP1 and a sub-phase EP2.

[0054] For details of the operation of the pixel circuit 100 when operating in the first operation mode (i.e., the low gray scale display state), please refer to Figure 2 and Figures 3A to 3D , Figures 3A to 3D is in accordance with the present invention Figure 1 Equivalent circuit diagram of the pixel circuit of the embodiment when operating in the first operation mode. Please note that, for the sake of convenience, in Figures 3A to 3D Transistors that are turned off are shown with a cross, while transistors that are turned on are shown without a cross.

[0055] For details of the operation of the pixel circuit 100 when operating in the first operation mode, please refer to Figure 2 and Figure 3A In the present embodiment, Figure 3A is an equivalent circuit diagram of the pixel circuit 100 when operating in the reset phase RP of the first operation mode. Specifically, in the reset phase RP, the source driving signal S1, the source driving signal S3, and the source driving signal S4 can be set to a low voltage level (e.g., the gate low voltage VGL), while the source driving signal S2 and the emission control signal EM can be set to a high voltage level (e.g., the gate high voltage VGH).

[0056] In detail, in the reset phase RP, the voltage regulator 120 can provide the reference voltage VREF to the control terminal CT1 through the conduction path of the transistor T3 according to the source driving signal S3 being pulled low, thereby causing the voltage level of the control terminal CT1 to be correspondingly pulled high to a voltage value equal to the reference voltage VREF. Also, the voltage regulator 120 can provide the gate high voltage VGH to the node P1 through the conduction paths of the transistors T4 and T5 based on the source driving signal S2 being pulled high and according to the source driving signal S3 being pulled low and the data voltage VDATA1, thereby causing the voltage level of the node P1 to be correspondingly pulled high to a voltage value equal to the gate high voltage VGH.

[0057] Next, the voltage adjuster 130 can provide the low voltage VL to the control terminal CT2 through the on-path of the transistor T7 in accordance with the pulled-down source driving signal S1, thereby causing the voltage level of the control terminal CT2 to be correspondingly pulled down to a voltage value equal to the low voltage VL.

[0058] In another aspect, in the reset phase RP of the first operation mode, the data voltage VDATA2 of the present embodiment can be set to a second voltage value VDATA2_L (i.e., 0 V). In this case, the voltage adjuster 130 can provide the data voltage VDATA2 to the node P2 in accordance with the pulled-down source driving signal S4, thereby causing the voltage level of the node P2 to be correspondingly pulled down to the second voltage value VDATA2_L equal to the data voltage VDATA2. Meanwhile, the driving circuit 110 can be turned off in accordance with the pulled-up emission control signal EM.

[0059] After the reset actions of the nodes are completed, please refer to Figure 2 and Figure 3B In the present embodiment, Figure 3B is an equivalent circuit diagram of the pixel circuit 100 operating in the compensation phase CP of the first operation mode. Specifically, in the compensation phase CP, the source driving signal S1 and the emission control signal EM can be set to a high voltage level (e.g., the gate high voltage VGH), while the source driving signal S2, the source driving signal S3, and the source driving signal S4 can be set to a low voltage level (e.g., the gate low voltage VGL).

[0060] In detail, in the compensation phase CP, the voltage adjuster 120 can provide the reference voltage VREF to the control terminal CT1 through the on-path of the transistor T3 in accordance with the pulled-down source driving signal S3, thereby causing the voltage level of the control terminal CT1 to be maintained at the voltage value of the reference voltage VREF. Also, the voltage adjuster 120 can discharge the node P1 through the on-paths of the transistors T4 and T5 based on the pulled-down source driving signal S2, and in accordance with the pulled-down source driving signal S3 and the data voltage VDATA1, so that the voltage level of the node P1 is adjusted to the sum of the voltage value of the data voltage VDATA1 and the voltage value of the threshold voltage VTH5 of the transistor T5 (i.e., VDATA1 + |VTH5|).

[0061] Next, the voltage adjuster 130 can charge the control terminal CT2 through the on-paths of the transistors T8 and T9 in accordance with the pulled-down source driving signal S2, so that the voltage level of the control terminal CT2 is adjusted to the voltage difference between the voltage value of the reference voltage VREF and the threshold voltage VTH9 of the transistor T9 (i.e., VREF - |VTH9|).

[0062] At this time, the transistor T9 can form a diode according to the connection mode of the diode connection through the on-path of the transistor T8, so as to compensate the threshold voltage VTH9, thereby improving the compensation accuracy.

[0063] In addition, in the compensation phase CP of the first operation mode, the data voltage VDATA2 of the present embodiment can be set as the second voltage value VDATA2_L (i.e., 0 V). In this case, the voltage adjuster 130 can provide the data voltage VDATA2 to the node P2 through the on-path of the transistor T6 according to the pulled-down source driving signal S4, thereby maintaining the voltage level of the node P2 at the second voltage value VDATA2_L of the data voltage VDATA2. Meanwhile, the driving circuit 110 can be turned off according to the pulled-up light emitting control signal EM.

[0064] Next, please refer to Figure 2 and Figure 3C In the present embodiment, Figure 3C is an equivalent circuit diagram of the pixel circuit 100 operating in the light emitting phase EP of the first operation mode. Specifically, in the light emitting phase EP, the source driving signals S1-S3 can be set as high voltage levels (e.g., gate high voltage VGH), and the light emitting control signal EM can be set as a low voltage level (e.g., gate low voltage VGL). Moreover, the source driving signal S4 can be set as a low voltage level (e.g., gate low voltage VGL) in the sub-phase EP1 of the light emitting phase EP, and can be set as a high voltage level (e.g., gate high voltage VGH) in the sub-phase EP2 of the light emitting phase EP.

[0065] In detail, in the light emitting phase EP, the voltage adjuster 120 can provide the system high voltage VDD to the node P1 through the on-path of the transistor T1 according to the pulled-down light emitting control signal EM, so that the voltage level of the node P1 is adjusted as the voltage value of the system high voltage VDD.

[0066] Next, the voltage adjuster 120 can adjust the voltage level of the control terminal CT1 as the sum of the reference voltage VREF and the voltage difference between the system high voltage VDD, the data voltage VDATA1 and the threshold voltage VTH5 of the transistor T5 through the coupling effect of the capacitor C1. That is, the voltage level of the control terminal CT1 at this time is VREF+(VDD-VDATA1- |VTH5|).

[0067] In this case, the transistor T2 of the voltage regulator 120 can generate the driving current I1 to the driving circuit 110 according to the voltage level of the control terminal CT1. At this time, the size of the on current ID flowing through the light emitting element LED is the current value of the driving current I1. Here, the on current ID and the driving current I1 can be expressed as the following equation (1):

[0068] ID = I1 = K (VDD - (VREF - |VTH5| + VDD - VDATA1) - |VTH2|)2

[0069] = K (VDATA1 - VREF)2Equation (1)

[0070] According to the above equation, when the pixel circuit 100 operates in the light emitting phase EP, since the transistor T2 and the transistor T5 match each other (i.e., the threshold voltage VTH2 is the same as the threshold voltage VTH5), the on current ID generated by the pixel circuit 100 can be independent of the threshold voltage VTH2 of the transistor T2 and the voltage value of the system high voltage VDD. In this way, the pixel circuit 100 can improve the influence of the shift of the threshold voltage of the transistor T2 (or the switching transistor) caused by the process difference or long-time operation. Also, the on current ID generated by the pixel circuit 100 is less likely to be affected by the line resistance in the path of the system high voltage VDD and the system low voltage VSS.

[0071] On the other hand, in the light emitting phase EP of the first operation mode, the data voltage VDATA2 of the present embodiment can be set to the first voltage value VDATA2_H (i.e., 6V). In this case, in the sub-phase EP1 of the light emitting phase EP of the first operation mode, the voltage regulator 130 can provide the data voltage VDATA2 to the node P2 through the on path of the transistor T6 according to the pulled-down source driving signal S4, thereby making the voltage level of the node P2 be pulled up to the first voltage value VDATA2_H.

[0072] Then, the voltage regulator 130 can make the voltage level of the control terminal CT2 be pulled up to the sum of the voltage difference between the reference voltage VREF and the threshold voltage VTH9 of the transistor T9 and the voltage variation amount AVDATA2 of the data voltage VDATA2 through the coupling effect of the capacitor C2. That is, the voltage level of the control terminal CT2 at this time is VREF - |VTH9| + AVDATA2. Here, the voltage variation amount AVDATA2 is the voltage difference between the first voltage value VDATA2_H and the second voltage value VDATA2_L (i.e., VDATA2_H - VDATA2_L).

[0073] In addition, in the sub-stage EP2 of the light emission stage EP in the first operating mode, the voltage regulator 130 can disconnect the transistor T6 according to the pulled-up source drive signal S4, and maintain the voltage level of node P2 at the first voltage value VDATA2_H.

[0074] In other words, when the pixel circuit 100 is operating in the light-emitting stage EP of the first operating mode, the pixel circuit 100 can disconnect the voltage regulator 130 and stop generating the driving current I2 to the driving circuit 110 according to the voltage level of the control terminal CT2.

[0075] Next, please refer to the following: Figure 2 as well as Figure 3D In this embodiment, Figure 3D This is an equivalent circuit diagram of the pixel circuit 100 operating in the cutoff phase TP of the first operating mode. Specifically, in the cutoff phase TP, the source drive signals S1 to S4 and the light emission control signal EM can be set to a high voltage level (e.g., gate high voltage VGH).

[0076] It is worth mentioning that, due to Figure 3D The voltage levels of the control terminals CT1 and CT2 and nodes P1 and P2 of the pixel circuit 100 shown are all the same as those of the control terminals CT1 and CT2 and nodes P1 and P2 shown. Figure 3C The voltage levels of the control terminals CT1 and CT2 and nodes P1 and P2 of the pixel circuit 100 shown, therefore, regarding Figure 3D The voltage state of each node in the pixel circuit 100 can be referenced Figure 3C The description of the pixel circuit 100 shown is analogous to this, so it will not be repeated here. In the cutoff phase TP, the driving circuit 110 can stop lighting the light-emitting element LED according to the pulled-up light-emitting control signal EM.

[0077] For details regarding the implementation of the pixel circuit 100 in the second operating mode (i.e., high grayscale display state), please also refer to... Figure 2 as well as Figures 4A to 4D , Figures 4A to 4D According to the present invention Figure 1 The equivalent circuit diagram of the pixel circuit in the embodiment when operating in the second operating mode. It should be noted that, for ease of illustration, in... Figures 4A to 4D A transistor that is off is indicated by an "X", while a transistor that is on is indicated by no "X".

[0078] Please refer to the following at the same time Figure 2 as well as Figure 4A In this embodiment, Figure 4A This is the equivalent circuit diagram for pixel circuit 100 during the reset phase RP of the second operating mode. Wherein, due to... Figure 4AThe voltage levels of the control terminals CT1, CT2, and node P1 of the pixel circuit 100 shown are all the same. Figure 3A The voltage levels of the control terminals CT1 and CT2 and node P1 of the pixel circuit 100 shown, therefore, regarding Figure 4A The voltage states of each node in the pixel circuit 100 during the reset phase RP can be referenced. Figure 3A The relevant descriptions of the pixel circuit 100 shown are analogous, so they will not be repeated here.

[0079] Unlike Figure 3A In the example, in Figure 4A In this embodiment, the data voltage VDATA2 can be set to a first voltage value VDATA2_H (i.e., 6V). In this case, the voltage regulator 130 can provide the data voltage VDATA2 to node P2 through the conduction path of transistor T6 according to the pulled-down source drive signal S4, thereby causing the voltage level of node P2 to be correspondingly pulled up to the first voltage value VDATA2_H equal to the data voltage VDATA2.

[0080] Next, please refer to the following: Figure 2 as well as Figure 4B In this embodiment, Figure 4B This is the equivalent circuit diagram for pixel circuit 100 during the compensation phase CP in the second operating mode. Wherein, due to... Figure 4B The voltage levels of the control terminals CT1, CT2, and node P1 of the pixel circuit 100 shown are all the same. Figure 3B The voltage levels of the control terminals CT1 and CT2 and node P1 of the pixel circuit 100 shown, therefore, regarding Figure 4B The voltage state of each node in the pixel circuit 100 during the compensation phase CP can be referenced. Figure 3B The relevant descriptions of the pixel circuit 100 shown are analogous, so they will not be repeated here.

[0081] Unlike Figure 3B In the example, in Figure 4B In this embodiment, the data voltage VDATA2 can be set to a first voltage value VDATA2_H (i.e., 6V). In this case, the voltage regulator 130 can provide the data voltage VDATA2 to node P2 through the conduction path of transistor T6 according to the pulled-down source drive signal S4, thereby maintaining the voltage level of node P2 at the first voltage value VDATA2_H of the data voltage VDATA2.

[0082] Next, please refer to the following: Figure 2 as well as Figure 4C In this embodiment, Figure 4C The equivalent circuit diagram for pixel circuit 100 operating in the light emission stage EP of the second operating mode.

[0083] In detail, in the light emitting phase EP, the voltage adjuster 120 can provide the system high voltage VDD to the node P1 through the on-path of the transistor T1 according to the light emitting control signal EM being pulled low, so that the voltage level of the node P1 is adjusted to the voltage value of the system high voltage VDD.

[0084] Then, the voltage adjuster 120 can adjust the voltage level of the control terminal CT1 to the sum of the reference voltage VREF and the voltage difference between the system high voltage VDD, the data voltage VDATA1 and the threshold voltage VTH5 of the transistor T5 through the coupling effect of the capacitor C1. That is, the voltage level of the control terminal CT1 at this time is VREF+(VDD-VDATA1-|VTH5|).

[0085] In this case, the transistor T2 of the voltage adjuster 120 can generate the driving current I1 to the driving circuit 110 according to the voltage level of the control terminal CT1. Wherein, the current size of the driving current I1 at this time can be shown by the above equation (1).

[0086] On the other hand, in the light emitting phase EP of the second operation mode, the data voltage VDATA2 of the present embodiment can be set to the second voltage value VDATA2_L (i.e. 0V). In this case, in the sub-phase EP1 of the light emitting phase EP of the second operation mode, the voltage adjuster 130 can provide the data voltage VDATA2 to the node P2 through the on-path of the transistor T6 according to the source driving signal S4 being pulled low, thereby pulling down the voltage level of the node P2 to the second voltage value VDATA2_L.

[0087] Then, the voltage adjuster 130 can pull down the voltage level of the control terminal CT2 to the voltage difference between the reference voltage VREF, the threshold voltage VTH9 of the transistor T9 and the voltage variation amount △VDATA2 of the data voltage VDATA2 through the coupling effect of the capacitor C2. That is, the voltage level of the control terminal CT2 at this time is VREF-|VTH9|-△VDATA2. Wherein, the above voltage variation amount △VDATA2 is the voltage difference between the first voltage value VDATA2_H and the second voltage value VDATA2_L (i.e. VDATA2_H-VDATA2_L).

[0088] In this case, the transistor T9 of the voltage adjuster 130 can generate the driving current I2 to the driving circuit 110 according to the voltage level of the control terminal CT2. Wherein, the driving current I2 can be shown by the following equation (2):

[0089] I2=K(VREF-(VREF-|VTH9|-△VDATA2)-|VTH9|)^2

[0090] = K (△VDATA2)2Equation (2)

[0091] That is, in the second operation mode, the current value of the on current ID generated by the driving circuit 110 can be the sum of the current values of the driving current I1 and the driving current I2. At this time, the on current ID can be as shown in the following Equation (3):

[0092] ID = I1 + I2 = K (VDATA1 - VREF)2+ K (△VDATA2)2Equation (3)

[0093] wherein ID is the current value of the on current ID; K is the process parameter of the driving transistor TD; VDATA1 is the voltage value of the data voltage VDATA1; VREF is the voltage value of the reference voltage VREF; and △VDATA2 is the voltage variation of the data voltage VDATA2.

[0094] Next, please refer to Figure 2 and Figure 4D In the present embodiment, Figure 4D is the equivalent circuit diagram of the pixel circuit 100 operating in the off phase TP of the second operation mode. Since Figure 4D the voltage levels of the control terminals CT1 and CT2 and the node P1 of the pixel circuit 100 shown in Figure 3D are the same as the voltage levels of the control terminals CT1 and CT2 and the node P1 of the pixel circuit 100 shown in Figure 4D , the voltage states of the respective nodes of the pixel circuit 100 in the off phase TP can be analogized by referring to the related description of the pixel circuit 100 shown in Figure 3D , and thus will not be described again.

[0095] Unlike the Figure 3D embodiment, in the Figure 4D embodiment, the data voltage VDATA2 can be set to the second voltage value VDATA2_L (i.e., 0V). Therefore, the voltage regulator 130 can turn off the transistor T6 according to the pulled-up source driving signal S4, so as to maintain the voltage level of the node P2 at the second voltage value VDATA2_L of the data voltage VDATA2.

[0096] Based on the above description, it can be understood that when the pixel circuit 100 operates in the first operating mode (i.e., low grayscale display state) light-emitting stage, the light-emitting brightness of the light-emitting element LED can be determined solely by the voltage regulator 120. However, when the pixel circuit 100 operates in the second operating mode (i.e., high grayscale display state) light-emitting stage, the light-emitting brightness of the light-emitting element LED can be determined jointly by the additional voltage regulator 130 and the voltage regulator 120.

[0097] In this way, the pixel circuit 100 of this embodiment can control the grayscale state of the display screen through two current paths, thereby reducing the voltage difference between the system high voltage VDD and the system low voltage VSS, and achieving the effect of improving power consumption.

[0098] Furthermore, the pixel circuit 100 in this embodiment can also compensate for the critical voltage variation of the transistor, thereby improving the consistency of the conduction current ID and improving the display quality.

[0099] Figure 5 This is a flowchart of a pixel circuit driving method according to an embodiment of the present invention. Please also refer to... Figure 1 as well as Figure 5 In step S510, the pixel circuit 100 causes the driving circuit 110 to generate a conduction current ID based on the light emission control signal EM. In step S520, the pixel circuit 100 causes the voltage regulator 120 to adjust the voltage level of the control terminal CT1 of the voltage regulator 120 based on the light emission control signal EM, the source drive signal S3, the data voltage VDATA1, and the reference voltage VREF, and generates a drive current I1 based on the voltage level of the control terminal CT1. In step S530, the pixel circuit 100 causes the voltage regulator 130 to adjust the voltage level of the control terminal CT2 of the voltage regulator 130 based on the source drive signals S1, S2, and S4, the data voltage VDATA2, and the reference voltage VREF, and generates a drive current I2 based on the voltage level of the control terminal CT2. In step S540, in the first operating mode, the pixel circuit 100 sets the magnitude of the conduction current ID to be the current value of the drive current I1, and in the second operating mode, the pixel circuit 100 sets the magnitude of the conduction current ID to be the current value of the sum of the drive current I1 and the drive current I2.

[0100] about Figure 5 The implementation details of each step are described in detail in the aforementioned embodiments and implementation methods, and will not be repeated here.

[0101] In summary, the pixel circuit of the embodiments of the present application can determine the luminance of the light emitting element by the main voltage regulator in the low gray scale display state, and determine the luminance of the light emitting element by the additional voltage regulator and the main voltage regulator in the high gray scale display state. In this way, the pixel circuit can control the gray scale state of the display image through two current paths to reduce the cross voltage between the system high voltage and the system low voltage, and achieve the effect of improving power consumption.

Claims

1. A pixel circuit, comprising: a driving circuit configured to generate a turn-on current according to a light emission control signal; a first voltage adjuster having a first control terminal, the first voltage adjuster coupled to the driving circuit, configured to adjust a voltage level of the first control terminal according to the light emission control signal, a third source driving signal, a first data voltage, and a reference voltage, and generate a first driving current according to the voltage level of the first control terminal; and a second voltage adjuster having a second control terminal, the second voltage adjuster coupled to the driving circuit, configured to adjust a voltage level of the second control terminal according to a first source driving signal, a second source driving signal, a fourth source driving signal, a second data voltage, and the reference voltage, and generate a second driving current according to the voltage level of the second control terminal, wherein in a first operation mode, a current value of the turn-on current is equal to a current value of the first driving current, and in a second operation mode, the current value of the turn-on current is equal to a sum of current values of the first driving current and the second driving current, wherein the first voltage adjuster comprises: a first transistor having a first terminal coupled to a system high voltage, a second terminal coupled to a first node, and a control terminal configured to receive the light emission control signal; a second transistor having a first terminal coupled to the system high voltage, a second terminal coupled to the driving circuit, and a control terminal coupled to the first control terminal; a third transistor having a first terminal coupled to the reference voltage, a second terminal coupled to the first control terminal, and a control terminal configured to receive the third source driving signal; a fourth transistor having a first terminal coupled to the first node, and a control terminal configured to receive the third source driving signal; a fifth transistor having a first terminal configured to receive the second source driving signal, a second terminal coupled to a second terminal of the fourth transistor, and a control terminal coupled to the first data voltage; and a first capacitor coupled between the first control terminal and the first node.

2. The pixel circuit of claim 1, wherein in a reset phase of the first operation mode or the second operation mode, the first voltage adjuster is configured to provide the reference voltage to pull up the voltage level of the first control terminal according to the third source driving signal being pulled down, and the second voltage adjuster is configured to provide a low voltage to pull down the voltage level of the second control terminal according to the first source driving signal being pulled down.

3. The pixel circuit of claim 1, wherein in a compensation phase of the first operation mode or the second operation mode, the second voltage adjuster is configured to provide the reference voltage to charge the second control terminal according to the second source driving signal being pulled down.

4. The pixel circuit of claim 1, wherein in a light emission phase of the first operation mode, the first voltage adjuster is configured to pull down the voltage level of the first control terminal according to the light emission control signal being pulled down, and generate the first driving current to the driving circuit, and the second voltage adjuster is configured to pull up the voltage level of the second control terminal according to the second data voltage and the fourth source driving signal being pulled down, and stop generating the second driving current. ​ 5. The pixel circuit of claim 4, wherein in the light emitting stage of the second operation mode, the first voltage adjuster pulls down the voltage level of the first control terminal according to the light emitting control signal being pulled down and generates the first driving current to the driving circuit, and the second voltage adjuster pulls down the voltage level of the second control terminal according to the second data voltage and the fourth source driving signal being pulled down and generates the second driving current to the driving circuit.

6. The pixel circuit of claim 5, wherein when the second data voltage is set to a first voltage value, the pixel circuit operates in the first operation mode, and when the second data voltage is set to a second voltage value, the pixel circuit operates in the second operation mode, wherein the first voltage value is greater than the second voltage value.

7. The pixel circuit of claim 1, wherein the driving circuit comprises: a driving transistor having a first terminal coupled to the first voltage adjuster and the second voltage adjuster, a control terminal receiving the light emitting control signal, and a second terminal; and a light emitting element having an anode terminal coupled to the second terminal of the driving transistor, and a cathode terminal coupled to a system low voltage.

8. The pixel circuit of claim 1, wherein the second transistor and the fifth transistor are matched to each other.

9. The pixel circuit of claim 1, wherein the second voltage adjuster comprises: a sixth transistor having a first terminal coupled to the second data voltage, a second terminal coupled to a second node, and a control terminal receiving the fourth source driving signal; a seventh transistor having a first terminal coupled to a low voltage, a second terminal coupled to the second control terminal, and a control terminal receiving the first source driving signal; an eighth transistor having a first terminal coupled to the driving circuit, a second terminal coupled to the second control terminal, and a control terminal receiving the second source driving signal; a ninth transistor having a first terminal coupled to the reference voltage, a second terminal coupled to the driving circuit, and a control terminal coupled to the second control terminal; a second capacitor coupled between the second control terminal and the second node; and a third capacitor coupled between the second node and the reference voltage.

10. A driving method of a pixel circuit, comprising: causing a driving circuit to generate a conduction current according to a light emitting control signal; causing a first voltage adjuster to adjust a voltage level of a first control terminal of the first voltage adjuster according to the light emitting control signal, a third source driving signal, a first data voltage, and a reference voltage, and to generate a first driving current according to the voltage level of the first control terminal; causing a second voltage adjuster to adjust a voltage level of a second control terminal of the second voltage adjuster according to a first source driving signal, a second source driving signal, a fourth source driving signal, a second data voltage, and the reference voltage, and to generate a second driving current according to the voltage level of the second control terminal; and ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ In a first operation mode, the conduction current has a current value equal to the first drive current, and in a second operation mode, the conduction current has a current value equal to the sum of the first drive current and the second drive current, wherein the first voltage regulator comprises: a first transistor having a first end coupled to a system high voltage, a second end coupled to a first node, and a control end receiving the light emission control signal; a second transistor having a first end coupled to the system high voltage, a second end coupled to the drive circuit, and a control end coupled to the first control end; a third transistor having a first end coupled to the reference voltage, a second end coupled to the first control end, and a control end receiving the third source drive signal; a fourth transistor having a first end coupled to the first node and a control end receiving the third source drive signal; a fifth transistor having a first end receiving the second source drive signal, a second end coupled to the second end of the fourth transistor, and a control end coupled to the first data voltage; and a first capacitor coupled between the first control end and the first node.

11. The driving method of claim 10, wherein the driving method further comprises: in a reset phase of the first operation mode or the second operation mode, causing the first voltage regulator to provide the reference voltage to pull up a voltage level of the first control end in response to the third source drive signal being pulled down, and causing the second voltage regulator to provide a low voltage to pull down a voltage level of the second control end in response to the first source drive signal being pulled down.

12. The driving method of claim 10, wherein the driving method further comprises: in a compensation phase of the first operation mode or the second operation mode, causing the second voltage regulator to provide the reference voltage to charge the second control end in response to the second source drive signal being pulled down.

13. The driving method of claim 10, wherein the driving method further comprises: in a light emission phase of the first operation mode, causing the first voltage regulator to generate the first drive current to the drive circuit in response to the light emission control signal being pulled down to pull down a voltage level of the first control end, and causing the second voltage regulator to stop generating the second drive current in response to the second data voltage and the fourth source drive signal being pulled down to pull up a voltage level of the second control end.

14. The driving method of claim 13, wherein the driving method further comprises: in the light emission phase of the second operation mode, causing the first voltage regulator to generate the first drive current to the drive circuit in response to the light emission control signal being pulled down to pull down a voltage level of the first control end, and causing the second voltage regulator to generate the second drive current to the drive circuit in response to the second data voltage and the fourth source drive signal being pulled down to pull down a voltage level of the second control end.

15. The driving method of claim 14, wherein the pixel circuit is operated in the first operation mode when the second data voltage is set to a first voltage value, and is operated in the second operation mode when the second data voltage is set to a second voltage value, wherein the first voltage value is greater than the second voltage value.

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