Input data pre-alignment circuit for semiconductor memory

Abstract

An embodiment of the present invention provides an input data pre-alignment circuit for a semiconductor memory. The input data pre-alignment circuit includes a first amplifier, a second amplifier, a timing control unit, a feedback signal generator, and a signal alignment unit. The first amplifier is used to receive and amplify a data signal and a reference signal. The second amplifier is coupled to the first output end of the first amplifier and the second output end of the first amplifier. The timing control unit is used to receive paired timing signals. The feedback signal generator is coupled to the second amplifier and the timing control unit. The signal alignment unit is coupled to the second input end of the first amplifier, the first output end of the first amplifier, the second output end of the first amplifier, and the feedback signal generator. By utilizing the input data pre-alignment circuit of the present invention, the signal offset of the dynamic random access memory under high-speed execution can be adjusted, and a first-in-first-out (FIFO) signal alignment function can be realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor memory technology, and in particular to an input data pre-alignment circuit for a semiconductor memory. Background Art

[0002] With the rapid advancement of technology, various volatile and non-volatile memory types have been incorporated into computer systems. Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that falls under the volatile category. Its primary operating principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. DRAM is a short-term data storage area in a computer system, storing information currently in use for quick access.

[0003] DRAM can provide high-speed transmission and high bandwidth utilization. However, due to the high speed and high bandwidth utilization required of DRAM, data synchronization and alignment are even more important. This is especially true with the newer Double-Data-Rate (DDR) 4 and DDR5 specifications, which require even higher data transmission speeds. Therefore, precisely aligning data with clock signals is a pressing issue. Summary of the Invention

[0004] In order to solve the above technical problems, the solution of the present invention is proposed. An embodiment of the present invention provides an input data pre-alignment circuit for a semiconductor memory.

[0005] According to one aspect of an embodiment of the present invention, an input data pre-alignment circuit for a semiconductor memory is provided. The input data pre-alignment circuit includes a first amplifier, a second amplifier, a clock control unit, a feedback signal generator, and a signal alignment unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference signal, a first output terminal, and a second output terminal. The second amplifier is coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier. The clock control unit is used to receive paired clock signals. The feedback signal generator is coupled to the second amplifier and the clock control unit. The signal alignment unit is coupled to the second input terminal of the first amplifier, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the feedback signal generator.

[0006] Optionally, the first amplifier also includes: a first transistor, including: a first end, for receiving an operating voltage; a second end; and a control end; a second transistor, including: a first end, for receiving the operating voltage; a second end; and a control end, coupled to the control end of the first transistor; a third transistor, including: a first end, coupled to the second end of the first transistor; a second end; and a control end, for receiving the data signal; a fourth transistor, including: a first end, coupled to the second end of the second transistor; a second end, coupled to the second end of the third transistor; and a control end, for receiving the reference signal; a fifth transistor, including: a first end, coupled to the second end of the fourth transistor; a second end, coupled to the ground end; and a control end, for receiving a bias signal.

[0007] Optionally, the first transistor and the second transistor are P-type metal oxide semiconductor field effect transistors, and the third transistor, the fourth transistor and the fifth transistor are N-type metal oxide semiconductor field effect transistors.

[0008] Optionally, the second amplifier includes: a first input terminal coupled to the first output terminal of the first amplifier; a second input terminal coupled to the second output terminal of the first amplifier; a first output terminal; and a second output terminal.

[0009] Optionally, it also includes: a sampling unit coupled to the second amplifier, the sampling unit including: a first input terminal coupled to the first output terminal of the second amplifier; a second input terminal coupled to the second output terminal of the second amplifier; a third input terminal for receiving a first clock signal; a fourth input terminal for receiving a second clock signal; a first output terminal for outputting even-numbered timing data; and a second output terminal for outputting odd-numbered timing data; wherein the paired clock signals include the first clock signal and the second clock signal, and the first clock signal and the second clock signal are in anti-phase.

[0010] Optionally, the clock control unit includes: multiple first inverters for receiving a first clock signal and outputting a first clock delay signal; and multiple second inverters for receiving a second clock signal and outputting a second clock delay signal; wherein the paired clock signals include the first clock signal and the second clock signal, the first clock signal and the second clock signal are in anti-phase, and the first clock delay signal and the second clock delay signal are in anti-phase.

[0011] Optionally, the feedback signal generator includes: a first NAND gate, including: a first input terminal coupled to the first output terminal of the second amplifier; a second input terminal for receiving the second clock delay signal; and an output terminal; a third inverter, including: an input terminal coupled to the output terminal of the first NAND gate; and an output terminal; a second NAND gate, including: a first input terminal coupled to the first input terminal of the first NAND gate; a second input terminal for receiving the first clock delay signal; a fourth inverter, including: an input terminal coupled to the output terminal of the second NAND gate; and an output terminal.

[0012] Optionally, the signal alignment unit includes: a sixth transistor, including: a first end coupled to the first output end of the first amplifier; a control end coupled to the output end of the third inverter; and a second end; a seventh transistor, including: a first end coupled to the first output end of the first amplifier; a control end coupled to the output end of the fourth inverter; and a second end coupled to the second end of the sixth transistor; an eighth transistor, including: a first end coupled to the second output end of the first amplifier; a control end for receiving the reference signal; and a second end coupled to the second end of the sixth transistor; a ninth transistor, including: a first end coupled to the second end of the sixth transistor; a control end for receiving a bias signal; and a second end; and a tenth transistor, including: a first end coupled to the second end of the ninth transistor; a control end for receiving a start signal; and a second end.

[0013] Optionally, when the data signal is at an even timing, the control terminal of the sixth transistor is a high voltage, causing the sixth transistor to be turned on, and the control terminal of the seventh transistor is a low voltage, causing the seventh transistor to be turned off.

[0014] Optionally, when the data signal is at an odd timing, the control terminal of the sixth transistor is at a low voltage, causing the sixth transistor to be turned off, and the control terminal of the seventh transistor is at a high voltage, causing the seventh transistor to be turned on.

[0015] Optionally, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are N-type metal oxide semiconductor field effect transistors.

[0016] In summary, the input data pre-alignment circuit for a semiconductor memory provided by an embodiment of the present invention utilizes a signal alignment unit, using different transistors to allow odd- and even-numbered data signals to be fed back to the amplifier output via different paths, thereby adjusting the signal skew of the dynamic random access memory under high-speed execution. Furthermore, the input data pre-alignment circuit for a semiconductor memory provided by an embodiment of the present invention incorporates a sampling unit that separates odd- and even-numbered input data, and both odd- and even-numbered input data can implement a first-in-first-out (FIFO) signal alignment function. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features, and advantages of the present invention will become more apparent through a more detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. The accompanying drawings are provided to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and are not intended to limit the present invention. In the drawings, the same reference numerals generally represent the same components or steps.

[0018] Figure 1 1 is a schematic structural diagram of an input data pre-alignment circuit for a semiconductor memory provided by an exemplary embodiment of the present invention;

[0019] Figure 2 yes Figure 1 A schematic structural diagram of the first amplifier in the input data pre-alignment circuit of the exemplary embodiment;

[0020] Figure 3 yes Figure 1 A schematic structural diagram of the second amplifier in the input data pre-alignment circuit of the exemplary embodiment;

[0021] Figure 4 yes Figure 1 A schematic structural diagram of the sampling unit in the input data pre-alignment circuit of the exemplary embodiment;

[0022] Figure 5 yes Figure 1 A schematic structural diagram of the clock control unit in the input data pre-alignment circuit of the exemplary embodiment;

[0023] Figure 6 yes Figure 1 A schematic structural diagram of the feedback signal generator in the input data pre-alignment circuit of the exemplary embodiment;

[0024] Figure 7 yes Figure 1 A schematic structural diagram of the signal alignment unit in the input data pre-alignment circuit of the exemplary embodiment;

[0025] Figure 8 It is an application Figure 1 A schematic diagram of associated signal waveforms when inputting data into the pre-alignment circuit according to an exemplary embodiment.

[0026] The following are the descriptions of the reference numerals:

[0027] 100 Input data pre-alignment circuit

[0028] 10 First Amplifier

[0029] 11 Second amplifier

[0030] 12 Sampling Unit

[0031] 13 Clock Control Unit

[0032] 14 Feedback signal generator

[0033] 15 Signal alignment unit

[0034] DIP data signal

[0035] DIN reference signal

[0036] POUTB First output signal

[0037] POUT second output signal

[0038] PT third output signal

[0039] PB fourth output signal

[0040] E1 even-numbered time series data

[0041] O1 odd time series data

[0042] CLK first clock signal

[0043] CLB second clock signal

[0044] CLKDB first clock delay signal

[0045] CLKDT second clock delay signal

[0046] PE_FB first feedback signal

[0047] PO_FB Second feedback signal

[0048] V DD Operating voltage

[0049] BIAS bias signal

[0050] T1 first transistor

[0051] T2 second transistor

[0052] T3 third transistor

[0053] T4 fourth transistor

[0054] T5 fifth transistor

[0055] T6 Sixth transistor

[0056] T7 seventh transistor

[0057] T8 eighth transistor

[0058] T9 Ninth transistor

[0059] T10 tenth transistor

[0060] INV1 first inverter

[0061] INV2 Second inverter

[0062] INV3 third inverter

[0063] INV4 Fourth inverter

[0064] NAND1 first NAND gate

[0065] NAND2 second NAND gate

[0066] HF_EN start signal

[0067] P1 Output phase waveform of the first amplifier

[0068] P2 Output phase waveform of the second amplifier DETAILED DESCRIPTION

[0069] The present invention will be further described below with reference to the embodiments shown in the accompanying drawings. Obviously, the embodiments described are only a part of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described herein.

[0070] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0071] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of the present invention are only used to distinguish different steps, devices or modules, and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0072] It should also be understood that, in the embodiments of the present invention, “a plurality of” may refer to two or more than two, and “at least one” may refer to one, two or more than two.

[0073] It should also be understood that any component, data or structure mentioned in the embodiments of the present invention can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0074] In addition, the term "and / or" in this invention merely describes an association relationship between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the character " / " in this invention generally indicates that the related objects are in an "or" relationship.

[0075] It should also be understood that the description of the various embodiments of the present invention focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced with each other. For the sake of brevity, they will not be described one by one.

[0076] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0077] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0078] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0079] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0080] The following combination Figures 1 to 8 , the input data pre-alignment circuit for a semiconductor memory of the present invention is described.

[0081] Figure 1 FIG. 1 is a schematic diagram of a structure of an input data pre-alignment circuit for a semiconductor memory provided by an exemplary embodiment of the present invention. Figure 1The input data pre-alignment circuit 100 is designed to accurately align the data signal with the clock signal based on the input data signal and the reference signal, thereby achieving a first-in, first-out (FIFO) signal alignment function in both odd and even timings. The input data pre-alignment circuit 100 includes a first amplifier 10, a second amplifier 11, a clock control unit 13, a feedback signal generator 14, and a signal alignment unit 15. The first amplifier 10 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is used to receive the data signal DIP. The second input terminal is used to receive the reference signal DIN. The second amplifier 11 is coupled to the first output terminal of the first amplifier 10 and the second output terminal of the first amplifier 10. The clock control unit 13 is used to receive a pair of clock signals (CLK and CLB). The feedback signal generator 14 is coupled to the second amplifier 11 and the clock control unit 13. The signal alignment unit 15 is coupled to the second input terminal of the first amplifier 10, the first output terminal of the first amplifier 10, the second output terminal of the first amplifier 10, and the feedback signal generator 14. In the input data pre-alignment circuit 100, the first amplifier 10, the second amplifier 11, the clock control unit 13, the feedback signal generator 14, and the signal alignment unit 15 form a circuit loop that automatically aligns data based on paired clock signals (CLK and CLB) according to the data signal DIP and the reference signal DIN. Furthermore, the input data pre-alignment circuit 100 may also include a sampling unit 12. The sampling unit 12 is coupled to the second amplifier 11. The sampling unit 12 can generate even timing data E1 and odd timing data O1 based on the first clock signal CLK, the second clock signal CLB, and the dual output signals of the second amplifier 11. Furthermore, the even timing data E1 and the odd timing data O1 are coordinated with the first clock signal CLK. For example, the start time of the even-numbered timing data E1 may be the rising edge time of the first clock signal CLK, and the start time of the odd-numbered timing data O1 may be the falling edge time of the first clock signal CLK. Details of the input data pre-alignment circuit 100 will be described in detail later.

[0082] Figure 2 yes Figure 1 A schematic structural diagram of the first amplifier in the input data pre-alignment circuit of the exemplary embodiment; Figure 3 yes Figure 1 The schematic diagram of the structure of the second amplifier in the input data pre-alignment circuit of the exemplary embodiment. Figure 2 and Figure 3The first amplifier 10 and the second amplifier 11 in the input data pre-alignment circuit 100 are not limited by the circuit of the amplifier. For example, the first amplifier 10 and the second amplifier 11 can be a voltage amplifier, a current amplifier or a differential amplifier. Figure 2 In the embodiment, the first amplifier 10 may be a differential amplifier. The first amplifier 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The first transistor T1 includes a transistor for receiving an operating voltage V DD The second transistor T2 includes a first terminal, a second terminal and a control terminal for receiving the working voltage V DD The first transistor T1 includes a first terminal, a second terminal, and a control terminal coupled to the first transistor T1. The third transistor T3 includes a first terminal coupled to the second terminal of the first transistor T1, a second terminal, and a control terminal for receiving a data signal DIP. The fourth transistor T4 includes a first terminal coupled to the second terminal of the second transistor T2, a second terminal coupled to the second terminal of the third transistor T3, and a control terminal for receiving a reference signal DIN. The fifth transistor T5 includes a first terminal coupled to the second terminal of the fourth transistor T4, a second terminal coupled to ground, and a control terminal for receiving a bias signal BIAS. For purposes of illustration, the first transistor T1 and the second transistor T2 may be P-type metal-oxide-semiconductor field-effect transistors (P-Type Metal-Oxide-Semiconductor Field-Effect Transistors). The third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be N-type metal-oxide-semiconductor field-effect transistors (N-Type Metal-Oxide-Semiconductor Field-Effect Transistors). The bias signal BIAS may be a custom or default voltage value used to control the conduction state of the fifth transistor T5. For example, when the fifth transistor T5 is an N-type metal oxide semiconductor field effect transistor, the voltage of the bias signal BIAS will affect the conduction state of the fifth transistor T5, so the current of the first amplifier 10 passing through the fifth transistor T5 can also be controlled by the bias signal BIAS. In addition, when the third transistor T3 and the fourth transistor T4 are in the linear region, and the first transistor T1 and the second transistor T2 are turned on, the two outputs of the first amplifier 10, namely the first output signal POUTB and the second output signal POUT will also be linearly amplified according to the data signal DIP and the reference signal DIN. It should be understood that the first output signal POUTB is located at the first end of the third transistor T3, and the second output signal POUT is located at the first end of the fourth transistor T4. In addition, the first output signal POUTB and the second output signal POUT are inverted to each other. Figure 3In the embodiment, the second amplifier 11 can also be a differential amplifier, whose inputs are the first output signal POUTB and the second output signal POUT, which are mutually inverted. The second amplifier 11 includes a first input terminal coupled to the first output terminal of the first amplifier 10, a second input terminal coupled to the second output terminal of the first amplifier 10, a first output terminal coupled to the feedback signal generator 14, and a second output terminal. Therefore, after the first output signal POUTB and the second output signal POUT are operated by the second amplifier 11, they are amplified into a third output signal PT and a fourth output signal PB, respectively. The third output signal PT is output from the first output terminal. The fourth output signal PB is output from the second output terminal. Furthermore, the third output signal PT and the fourth output signal PB may be mutually inverted.

[0083] Figure 4 yes Figure 1 The schematic diagram of the structure of the sampling unit in the input data pre-alignment circuit of the exemplary embodiment. Figure 4 The sampling unit 12 includes a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to the first output terminal of the second amplifier 11. The second input terminal is coupled to the second output terminal of the second amplifier 11. The third input terminal is used to receive the first clock signal CLK. The fourth input terminal is used to receive the second clock signal CLB. In other words, the aforementioned paired clock signals include the first clock signal CLK and the second clock signal CLB, and the first clock signal CLK and the second clock signal CLB are in anti-phase. The first output terminal is used to output the even-numbered timing data E1. The second output terminal is used to output the odd-numbered timing data O1. It should be understood that the sampling unit 12 of the present invention can be implemented by any reasonable circuit. For example, the sampling unit 12 may include a sampling switch. The sampling switch can sample the amplified data signal DIP when the first clock signal CLK is at a rising edge to output the even-numbered timing data E1. Similarly, the sampling switch can sample the amplified data signal DIP when the first clock signal CLK is at a falling edge to output odd-numbered timing data O1. It should be understood that the waveform of the first clock signal CLK is a plurality of square waves. The time from the rising edge of a square wave to the rising edge of the next square wave is a complete cycle. This cycle is twice the width of the square wave. Therefore, each piece of even-numbered timing data E1 is latched for two square wave times, so the time index of the even-numbered timing data E1 is {0, 2, 4, 6…}. Similarly, the time from the falling edge of a square wave to the falling edge of the next square wave is a complete cycle. This cycle is twice the width of the square wave. Therefore, each piece of odd-numbered timing data O1 is latched for two square wave times, so the time index of the odd-numbered timing data O1 is {1, 3, 5, 7…}.

[0084] Figure 5 yes Figure 1 Schematic diagram of the structure of the clock control unit in the input data pre-alignment circuit of the exemplary embodiment. Figure 5 , the clock control unit 13 includes a plurality of first inverters INV1 and a plurality of second inverters INV2. The plurality of first inverters INV1 are used to receive the first clock signal CLK and output the first clock delay signal CLKDB. The plurality of second inverters INV2 are used to receive the second clock signal CLKB and output the second clock delay signal CLKDT. Moreover, the first clock signal CLK and the second clock signal CLKB are paired clock signals and are inverted to each other. In the clock control unit 13, the plurality of first inverters INV1 connected in series are used to delay the first clock signal CLK to output the first clock delay signal CLKDB. Similarly, the plurality of second inverters INV2 connected in series are used to delay the second clock signal CLKB to output the second clock delay signal CLKDT. As shown Figure 5 The number of first inverters INV1 and second inverters INV2 in the clock control unit 13 is unlimited. Furthermore, since each inverter has its own time delay, the more inverters there are in the clock control unit 13, the greater the time delay. Furthermore, when the number of first inverters INV1 and second inverters INV2 is the same, the first clock delay signal CKLDB and the second clock delay signal CLKDT are in opposite phases.

[0085] Figure 6 yes Figure 1 Schematic diagram of the structure of the feedback signal generator in the input data pre-alignment circuit of the exemplary embodiment. Figure 6 The feedback signal generator 14 includes a first NAND gate NAND1, a third inverter INV3, a second NAND gate NAND2, and a fourth inverter INV4. The first NAND gate NAND1 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first output terminal of the second amplifier 11 for receiving the third output signal PT. The second input terminal is used to receive the second clock delay signal CLKDT. The third inverter INV3 includes an input terminal and an output terminal. The input terminal is coupled to the output terminal of the first NAND gate NAND1. The output terminal is used to output the first feedback signal PE_FB. The second NAND gate NAND2 includes a first input terminal and a second input terminal. The first input terminal is coupled to the first input terminal of the first NAND gate NAND1 for receiving the third output signal PT. The second input terminal is used to receive the first clock delay signal CLKDB. The fourth inverter INV4 includes an input terminal and an output terminal. The input terminal is coupled to the output terminal of the second NAND gate NAND2. The output terminal is used to output the second feedback signal PO_FB. The operation of the feedback signal generator 14 is as follows. Figure 6When the data signal DIP is at an even timing (time index {0, 2, 4, 6...}), the second clock delay signal CLKDT is high and the first clock delay signal CLKDB is low. Therefore, when the third output signal PT contains valid data (high), both inputs of the first NAND gate NAND1 are high. Therefore, the output of the first NAND gate NAND1 is low. Ultimately, the third inverter INV3 outputs a high first feedback signal PE_FB. The second NAND gate NAND2 has two inputs, one high (PT) and one low (CLKDB). Therefore, the output of the second NAND gate NAND2 is high. Ultimately, the fourth inverter INV4 outputs a low second feedback signal PO_FB. Similarly, when the data signal DIP is at an odd timing (time index {1, 3, 5, 7...}), the second clock delay signal CLKDT is low and the first clock delay signal CLKDB is high. Therefore, when the third output signal PT contains valid data (high voltage), it will cause the two input terminals of the first NAND gate NAND1 to be at a high voltage (PT) and a low voltage (CLKDT). Therefore, the output terminal of the first NAND gate NAND1 will be at a high voltage. Ultimately, the third inverter INV3 will output a low-voltage first feedback signal PE_FB. Both input terminals of the second NAND gate NAND2 are high voltage. Therefore, the output terminal of the second NAND gate NAND2 will be low voltage. Ultimately, the fourth inverter INV4 will output a high-voltage second feedback signal PO_FB. From the above operation of the feedback signal generator 14, it can be seen that when the time index is {1, 3, 5, 7…}, the second feedback signal PO_FB corresponding to the odd timing is high, and the first feedback signal PE_FB corresponding to the even timing is low. Moreover, when the time index is {0, 2, 4, 6 . . .}, the second feedback signal PO_FB corresponding to the odd timing is at a low level, and the first feedback signal PE_FB corresponding to the even timing is at a high level.

[0086] Figure 7 yes Figure 1 Schematic diagram of the structure of the signal alignment unit in the input data pre-alignment circuit of the exemplary embodiment. Figure 7The signal alignment unit 15 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The sixth transistor T6 includes a first terminal coupled to the first output terminal of the first amplifier 10, a control terminal coupled to the output terminal of the third inverter INV3, for receiving the first feedback signal PE_FB, and a second terminal. The seventh transistor T7 includes a first terminal coupled to the first output terminal of the first amplifier 10, a control terminal coupled to the output terminal of the fourth inverter INV4, for receiving the second feedback signal PO_FB, and a second terminal coupled to the second terminal of the sixth transistor T6. The eighth transistor T8 includes a first terminal coupled to the second output terminal of the first amplifier 10, a control terminal for receiving the reference signal DIN, and a second terminal coupled to the second terminal of the sixth transistor T6. The ninth transistor includes a first terminal coupled to the second terminal of the sixth transistor T6, a control terminal for receiving the bias signal BIAS, and a second terminal. The tenth transistor T10 includes a first end coupled to the second end of the ninth transistor T9, a control end for receiving a start signal HF_EN, and a second end connected to the ground. In the signal alignment unit 15, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are N-type metal oxide semiconductor field effect transistors. The start signal HF_EN can be regarded as a switching signal of the signal alignment unit 15. For example, if the start signal HF_EN is a low voltage, the tenth transistor T10 is cut off, so no current passes through the tenth transistor T10. If the start signal HF_EN is a high voltage, the tenth transistor T10 is turned on. The signal alignment unit 15 can operate according to the bias signal BIAS, the first feedback signal PE_FB, the second feedback signal PO_FB, and the reference signal DIN, as described below.

[0087] As mentioned above, when the time index of the data signal DIP is {1, 3, 5, 7…}, the second feedback signal PO_FB corresponding to the odd timing is high, and the first feedback signal PE_FB corresponding to the even timing is low. Therefore, the control terminal of the sixth transistor T6 is at a low voltage (PE_FB), causing the sixth transistor T6 to be turned off. The control terminal of the seventh transistor T7 is at a high voltage (PO_FB), causing the seventh transistor T7 to be turned on. Because the voltages of the first output signal POUTB and the second output signal POUT are opposite, a current is generated between the first output signal POUTB and the second output signal POUT. Since the sixth transistor T6 is turned off and the seventh transistor T7 is turned on, the current between the first output signal POUTB and the second output signal POUT passes through the seventh transistor T7. In other words, when the time index of the data signal DIP is an odd-numbered sequence {1, 3, 5, 7...}, the input data pre-alignment circuit 100 can utilize the seventh transistor T7 of the signal alignment unit 15 to latch the amplified data signal DIP (i.e., the differential output: the first output signal POUTB and the second output signal POUT) according to the first clock signal CLK, thereby aligning the data signal DIP of the odd-numbered sequence {1, 3, 5, 7...} with the first clock signal CLK. Similarly, when the time index of the data signal DIP is {0, 2, 4, 6...}, the second feedback signal PO_FB corresponding to the odd-numbered sequence is low, and the first feedback signal PE_FB corresponding to the even-numbered sequence is high. Consequently, the control terminal of the sixth transistor T6 is a high voltage (PE_FB), turning on the sixth transistor T6. The control terminal of the seventh transistor T7 is a low voltage (PO_FB), turning off the seventh transistor T7. Because the voltages of the first output signal POUTB and the second output signal POUT are opposite, a current flows between the first output signal POUTB and the second output signal POUT. Since the sixth transistor T6 is on and the seventh transistor T7 is off, the current flows between the first output signal POUTB and the second output signal POUT through the sixth transistor T6. In other words, when the time index of the data signal DIP is an even-numbered sequence {0, 2, 4, 6...}, the input data pre-alignment circuit 100 can utilize the sixth transistor T6 of the signal alignment unit 15 to latch the amplified data signal DIP (i.e., the differential output: the first output signal POUTB and the second output signal POUT) according to the first clock signal CLK. This allows the data signal DIP of the even-numbered sequence {0, 2, 4, 6...} to be aligned with the first clock signal CLK. Furthermore, because the voltage of the bias signal BIAS affects the conduction state of the ninth transistor T9, a portion of the current flowing between the first output signal POUTB and the second output signal POUT can be directed to ground by the ninth transistor T9 and the tenth transistor T10. Therefore, the signal alignment unit 15 can also adjust the gain between the first output signal POUTB and the second output signal POUT.

[0088] Figure 8 It is an application Figure 1 Schematic diagram of the signal waveform associated with the input data pre-alignment circuit of the exemplary embodiment. As mentioned above, refer to Figure 8 The data signal DIP time index is represented as {0, 1, 2, 3, 4, 5, 6, 7…}. The output phase waveform P1 of the first amplifier 10 is similar to the data signal DIP, only slightly delayed. The output phase waveform P2 of the second amplifier 11 is similar to the output phase waveform P1 of the first amplifier 10, only slightly delayed. The first clock delay signal CLKDB and the second clock delay signal CLKDT are in opposite phases. The first clock signal CLK is a signal composed of multiple square waves. As mentioned above, when the time index of the data signal DIP is an even-numbered sequence {0, 2, 4, 6…}, the input data pre-alignment circuit 100 can utilize the signal alignment unit 15 to latch according to the first clock signal CLK, thereby aligning the data signal DIP of the even-numbered sequence {0, 2, 4, 6…} with the first clock signal CLK. Furthermore, the waveform of the first clock signal CLK is multiple square waves. The time from the rising edge of a square wave to the rising edge of the next square wave is a complete cycle. This cycle is twice the width of the square wave. Therefore, each piece of even-numbered sequential data E1 is latched for two square wave periods, resulting in a time index of {0, 2, 4, 6…}, which is exactly two time indexes apart. Similarly, when the time index of the data signal DIP is an odd-numbered sequence {1, 3, 5, 7…}, the input data pre-alignment circuit 100 can utilize the signal alignment unit 15 to latch according to the first clock signal CLK, thereby aligning the data signal DIP of the odd-numbered sequence {1, 3, 5, 7…} with the first clock signal CLK. Furthermore, the waveform of the first clock signal CLK is a plurality of square waves. The time from the falling edge of a square wave to the falling edge of the next square wave constitutes a complete cycle. This cycle is twice the width of the square wave. Therefore, each piece of odd-numbered sequential data O1 is latched for two square wave periods, resulting in a time index of {1, 3, 5, 7…}, which is exactly two time indexes apart.

[0089] In summary, an embodiment of the present invention provides an input data pre-alignment circuit for a semiconductor memory, which can be applied to a dynamic random access memory to realize signal synchronization and alignment functions. The input data pre-alignment circuit can utilize a signal alignment unit and use different transistors to allow the data signal of the odd timing and the data signal of the even timing to be fed back to the output of the amplifier through different paths, thereby adjusting the signal offset of the dynamic random access memory under high-speed execution. In addition, the input data pre-alignment circuit introduces a sampling unit. The sampling unit can separate the input data of the odd timing and the even timing, and the input data of the odd timing and the even timing can both realize the first-in-first-out (FIFO) signal alignment function.

[0090] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. An input data pre-alignment circuit for a semiconductor memory, characterized in that: include: A first amplifier comprising: A first input terminal for receiving a data signal; A second input terminal for receiving a reference signal; a first output terminal; and a second output terminal; a second amplifier coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier; A clock control unit for receiving paired clock signals; a feedback signal generator coupled to the second amplifier and the clock control unit; and a signal alignment unit coupled to the second input terminal of the first amplifier, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the feedback signal generator; Wherein, the second amplifier comprises: a first input terminal coupled to the first output terminal of the first amplifier; a second input terminal coupled to the second output terminal of the first amplifier; a first output terminal; and a second output terminal; Wherein, the input data pre-alignment circuit further includes: The sampling unit is coupled to the second amplifier.

2. The input data pre-alignment circuit according to claim 1, wherein: The first amplifier further includes: A first transistor comprising: A first terminal is used to receive an operating voltage; the second end; and Control terminal; A second transistor comprising: A first end, for receiving the operating voltage; the second end; and a control terminal coupled to the control terminal of the first transistor; A third transistor includes: a first terminal coupled to the second terminal of the first transistor; the second end; and A control terminal, configured to receive the data signal; a fourth transistor comprising: a first terminal coupled to the second terminal of the second transistor; A second terminal coupled to the second terminal of the third transistor; and A control terminal, configured to receive the reference signal; a fifth transistor comprising: a first terminal coupled to the second terminal of the fourth transistor; The second terminal is coupled to the ground terminal; and The control terminal is used to receive a bias signal.

3. The input data pre-alignment circuit according to claim 2, wherein: The first transistor and the second transistor are P-type metal oxide semiconductor field effect transistors, and the third transistor, the fourth transistor, and the fifth transistor are N-type metal oxide semiconductor field effect transistors.

4. The input data pre-alignment circuit according to claim 1, wherein: The sampling unit comprises: a first input terminal coupled to the first output terminal of the second amplifier; a second input terminal coupled to the second output terminal of the second amplifier; A third input terminal for receiving a first clock signal; a fourth input terminal for receiving a second clock signal; A first output terminal is used to output even-numbered timing data; and The second output terminal is used to output odd-numbered timing data; The paired clock signals include the first clock signal and the second clock signal, and the first clock signal and the second clock signal are in anti-phase.

5. The input data pre-alignment circuit according to claim 1, wherein: The clock control unit includes: A plurality of first inverters for receiving a first clock signal and outputting a first clock delay signal; and A plurality of second inverters for receiving a second clock signal and outputting a second clock delay signal; The paired clock signals include the first clock signal and the second clock signal, the first clock signal and the second clock signal are in opposite phases, and the first clock delay signal and the second clock delay signal are in opposite phases.

6. The input data pre-alignment circuit according to claim 5, characterized in that: The feedback signal generator includes: The first NAND gate includes: a first input terminal coupled to the first output terminal of the second amplifier; A second input terminal for receiving the second clock delay signal; and Output terminal; The third inverter comprises: an input terminal coupled to the output terminal of the first NAND gate; and Output terminal; The second NAND gate includes: a first input terminal coupled to the first input terminal of the first NAND gate; A second input terminal, configured to receive the first clock delay signal; The fourth inverter comprises: an input terminal coupled to the output terminal of the second NAND gate; and Output end.

7. The input data pre-alignment circuit according to claim 6, wherein: The signal alignment unit includes: a sixth transistor comprising: a first terminal coupled to the first output terminal of the first amplifier; a control terminal coupled to the output terminal of the third inverter; and Second end; A seventh transistor comprising: a first terminal coupled to the first output terminal of the first amplifier; a control terminal coupled to the output terminal of the fourth inverter; and a second terminal coupled to the second terminal of the sixth transistor; an eighth transistor comprising: a first terminal coupled to the second output terminal of the first amplifier; a control terminal, configured to receive the reference signal; and a second terminal coupled to the second terminal of the sixth transistor; A ninth transistor comprising: a first terminal coupled to the second terminal of the sixth transistor; a control terminal for receiving a bias signal; and the second end; and A tenth transistor comprising: a first terminal coupled to the second terminal of the ninth transistor; A control terminal for receiving a start signal; and Second end.

8. The input data pre-alignment circuit according to claim 7, wherein: When the data signal is at an even timing, the control terminal of the sixth transistor is a high voltage, causing the sixth transistor to be turned on, and the control terminal of the seventh transistor is a low voltage, causing the seventh transistor to be turned off.

9. The input data pre-alignment circuit according to claim 7, wherein: When the data signal is at an odd timing, the control terminal of the sixth transistor is at a low voltage, causing the sixth transistor to be turned off, and the control terminal of the seventh transistor is at a high voltage, causing the seventh transistor to be turned on.

10. The input data pre-alignment circuit according to claim 7, wherein: The sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are N-type metal oxide semiconductor field effect transistors.

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