A method and structure for three-dimensional packaged interlayer connections

Abstract

The present application relates to the technical field of microelectronic packaging, and aims to solve the problem of interconnection gap after interconnection between layers in the prior art interconnection method, and provide a three-dimensional packaging interconnection method and structure; wherein the interconnection method comprises preparing a substrate and a frame, processing interconnection holes and bonding pads on the substrate where interconnection between layers is needed, performing a metallization treatment on the inner wall of the interconnection holes, setting metal balls in the interconnection holes, deforming the metal balls by ultrasonic bonding to realize interconnection between the upper and lower substrates, stacking the substrates in turn and interconnecting them using the metal balls, and packaging the stacked and interconnected substrates in the frame; after packaging, there is almost no gap between the substrates, effectively solving the problem of interconnection gap between layers in packaging; the interconnection structure is obtained by the above interconnection method; the process of interconnecting the substrates is simple, convenient to operate, low in interconnection temperature, and small in interconnection gap between layers, and is particularly suitable for packaging high-frequency devices and heat-sensitive devices.

Description

Technical Field

[0001] This invention relates to the field of microelectronic packaging technology, and more specifically, to a three-dimensional packaging interlayer interconnection method and structure. Background Technology

[0002] In the field of microelectronic packaging technology, the development trend of packaging continues to move towards miniaturization and high integration. Devices such as mobile phones, wearable devices, and sensors have given priority to the use of 3D packaging technology, which reduces the packaging volume while improving integration and adding more functions.

[0003] 3D packaging mainly includes two types: chip-level 3D packaging and multi-layer board stacking 3D packaging. Chip-level 3D packaging involves stacking the same or different semiconductor chips multiple times in space to achieve packaging, while multi-layer board stacking 3D packaging involves stacking multiple layers of boards that have been assembled with chips and components multiple times in space. Both chip-level and multi-layer board stacking 3D packaging require interlayer interconnection.

[0004] Current interlayer interconnect technologies mainly include BGA interlayer interconnect, ultrasonic bonding interconnect with prefabricated metal bumps, and TSV interconnect.

[0005] BGA interlayer interconnection is widely used and the technology is the most mature. Patent CN201811574127 discloses a microstrip antenna with BGA interlayer interconnection. After interlayer interconnection, there will be an interconnection gap between each layer, which wastes packaging space and causes problems such as large insertion loss for high frequency device packaging.

[0006] Patent CN202210669029.3 discloses a method for interconnecting prefabricated metal bumps using ultrasonic bonding, thereby achieving interlayer interconnection. However, this ultrasonic bonding method using prefabricated metal bumps also suffers from interlayer gaps. When bonding large areas, it is prone to issues such as some bumps failing to bond properly, or others deforming excessively during bonding.

[0007] TSV interconnect, or Through Silicon Via Interconnect, is disclosed in patent CN202211068311.2, which uses several TSV adapter boards to achieve interlayer interconnection. Pre-fabricated metal bumps are also used between layers, and ultrasonic bonding is then employed for interconnection. This structure also suffers from interlayer gaps after interconnection. In large-area 3D packaging, issues such as some bumps failing to bond properly and others deforming excessively during bonding can easily arise. Furthermore, the addition of numerous TSV adapter boards between the package layers results in low space utilization. Summary of the Invention

[0008] The present invention aims to provide a three-dimensional packaging interlayer interconnection method and structure to solve the problem of interconnection gaps after interlayer interconnection in existing interlayer interconnection methods.

[0009] In complex 3D packaging applications, multiple packaging materials and assembly processes are often used together to achieve the desired packaging effect. These materials and processes typically have vastly different temperature tolerances. To better accommodate these diverse materials and processes, it is essential to find a packaging method that offers lower packaging temperatures and simpler operation, suitable for the specific needs of 3D packaging.

[0010] This invention provides a three-dimensional packaging interlayer interconnection method, comprising the following steps:

[0011] S1: Prepare multiple substrates and a frame. The substrates have embedded device vias and interconnect vias. Corresponding circuits and interconnect pads are fabricated on the substrates. The inner walls of the interconnect vias are provided with a metallization layer.

[0012] S2: Micro-assemble each substrate separately. The assembly process includes die bonding, flip-chip bonding, wire bonding, and functional index testing. After passing the test, place each substrate on one side in order for later use.

[0013] S3: Select a substrate as the starting stacking board, place it in the limiting fixture, then place the second substrate on the starting stacking board, adjust the limiting fixture to align the interconnect vias of the upper substrate with the interconnect pads of the lower substrate, and press the two substrates together.

[0014] S4: Place the metal balls into the interconnect vias of the upper substrate one by one, carefully check and ensure that there is a metal ball in each interconnect via;

[0015] S5: Place the stacked substrates on the ultrasonic bonding machine table, use a special bonding wedge, adjust the bonding parameters, and flatten and deform each metal ball in sequence. At this time, all the deformed metal balls will interconnect the upper and lower substrates. The bottom surface of the deformed metal ball is interconnected with the interconnection pad of the lower substrate, and the side surface of the deformed metal ball is interconnected with the metallization layer of the interconnection through hole of the upper substrate.

[0016] S6: Following the steps of S3 to S5, repeat the operation to stack the remaining substrates in sequence to achieve interconnection;

[0017] S7: The stacked multi-layer 3D packaging products are placed into the frame, and soft solder B is installed in the gap between the product side and the frame. The product is then placed in a vacuum eutectic furnace for heating. The soft solder B melts and fills the gap to complete the welding between the frame and the product.

[0018] S8: Place the product with the welded frame under the stencil and print solder A on the top and bottom surfaces of the product respectively;

[0019] S9: Place the product in a reflow oven to heat the metal bumps formed by the solder A into a spherical shape, and finally clean it;

[0020] S10: Place the product in the test fixture for testing, and after passing the test, vacuum pack it and put it into storage.

[0021] As a preferred technical solution:

[0022] S1 specifically includes:

[0023] S11: Prepare multiple substrates, make holes in each substrate according to the circuit structure, make through holes for embedded devices at the locations where embedded devices need to be set on the substrate, and make interconnection through holes at the locations where interconnection needs to be performed on the substrate. Then, according to the circuit structure, prepare corresponding circuits and interconnection pads on the substrate. During the process, gold plating is performed on the inner wall of the interconnection through holes and the outer side of the substrate.

[0024] S12: Prepare a metal frame. When processing the frame, chamfer the outer side of the frame, plate the inner side of the frame with nickel-gold, and plate the outer side with nickel.

[0025] As a preferred technical solution:

[0026] S11 also includes: grounding pads arranged around the surface and bottom of the substrate.

[0027] As a preferred technical solution:

[0028] In S5, the bonding temperature does not exceed 150°C during bonding, and only one metal ball is bonded at a time.

[0029] As a preferred technical solution:

[0030] In S7, an indium-lead alloy with a melting point of 220 degrees Celsius is installed in the gap between the side of the product and the frame.

[0031] As a preferred technical solution:

[0032] In S8, indium lead solder paste with a melting point of 185°C is printed on the top and bottom surfaces of the product.

[0033] In S9, the product is placed in a 210-degree reflow oven to heat the metal bumps formed by indium lead solder paste into a spherical shape.

[0034] The present invention further provides a three-dimensional packaged interlayer interconnection structure, which is obtained by the above-described three-dimensional packaged interlayer interconnection method.

[0035] As a preferred technical solution:

[0036] The interlayer interconnect structure includes multiple stacked substrates. Embedded device vias are provided at the locations where embedded devices need to be installed on the substrates. Interconnect vias are provided at the locations where the substrates need to be interconnected with another substrate. Corresponding circuits and interconnect pads are prepared on the surface and bottom of the substrates according to the circuit structure. A metallization layer is provided on the inner wall of the interconnect vias.

[0037] The interconnect vias of the upper substrate are aligned with the interconnect pads of the lower substrate. Metal balls are placed inside the interconnect vias. The metal balls are flattened and deformed by an ultrasonic bonding machine. All the deformed metal balls interconnect the upper and lower substrates. The bottom surface of the deformed metal balls is interconnected with the interconnect pads of the lower substrate, and the side surface of the deformed metal balls is interconnected with the metallization layer of the inner wall of the interconnect vias of the upper substrate.

[0038] After stacking, the substrates are assembled in the frame, and the substrates are fixedly connected to the frame.

[0039] As a preferred technical solution:

[0040] The substrate can be an FR-4 substrate, an alumina substrate, a zirconia substrate, a beryllium oxide substrate, an aluminum nitride substrate, a silicon substrate, a quartz substrate, a glass substrate, an LCP substrate, an LTCC substrate, or an HTCC substrate.

[0041] As a preferred technical solution:

[0042] The substrate thickness is 0.1–5 mm, and the diameter of the interconnect vias is 0.05–2 mm.

[0043] As a preferred technical solution:

[0044] The interconnect pads have a diameter of 0.06 to 2 mm.

[0045] As a preferred technical solution:

[0046] The diameter of the metal sphere is 0.04 to 1.9 mm.

[0047] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0048] This invention processes interconnect vias and bonding pads on the substrate where interlayer interconnection is required. The inner walls of the interconnect vias are metallized, and metal balls are placed in the interconnect vias. Ultrasonic bonding is used to deform the metal balls and interconnect the upper and lower substrates. After packaging, there is almost no gap between the substrates, which effectively solves the problem of interlayer interconnection gap in packaging. By using a method of bonding each bonding point individually, the problem of poor bonding when bonding pre-fabricated metal bumps over a large area is solved. At the same time, it has good advantages in low-temperature packaging.

[0049] The interconnect substrate of this invention has a simple process, is easy to operate, has a low interconnect temperature, and has a small interlayer gap after interconnection, making it particularly suitable for packaging high-frequency devices and heat-sensitive devices. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the interlayer interconnection structure of the three-dimensional packaging described in this invention.

[0051] Figure 2 for Figure 1 Enlarged view of point A in the middle.

[0052] Figure 3 This is a schematic diagram of the bonding process of metal spheres.

[0053] Icons: 1-Substrate, 2-Metal ball, 3-Solder A, 4-Interconnect via, 5-Flip bond ball, 6-Embedded chip, 7-Bond wire, 8-Interconnect metallization layer, 9-Bond cutter, 10-Solder B, 11-Frame. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] Example 1

[0056] like Figure 1 and Figure 2 As shown in the figure, this embodiment proposes a three-dimensional packaging interlayer interconnect structure, which includes at least two substrates 1, which are stacked together, and the substrates 1 have holes formed according to the circuit structure. Specifically, embedded device through-holes are formed at the locations where embedded devices need to be placed on the substrates 1, and interconnection through-holes 4 are formed at the locations where the substrates 1 need to be interconnected with another substrate 1. Figure 1 In the diagram, 6 represents an embedded chip, 7 represents a bonding wire, and 5 represents a flip-chip. Since some chips are conventionally mounted chips, they are usually bonded using wire bonding, while others are flip-chips, they are usually bonded using ultrasonic bonding of metal balls or by heating and soldering with solder balls. Flip-chip ball 5 is the interconnect ball of the flip-chip.

[0057] The substrate 1 can be an FR-4 substrate, an alumina substrate, a zirconia substrate, a beryllium oxide substrate, an aluminum nitride substrate, a silicon substrate, a quartz substrate, a glass substrate, an LCP substrate, an LTCC substrate, or an HTCC substrate; the thickness of the substrate 1 is 0.1–5 mm. In this embodiment, the substrate 1 is an alumina ceramic substrate with a thickness of 0.38 mm, and a total of 7 substrates 1 are used, all of which are stacked.

[0058] The surface and bottom of the substrate 1 are prepared with corresponding circuits and interconnect pads according to the circuit structure. The material of the circuit can be gold, silver, copper, or aluminum, and a plating layer is formed on the surface of the substrate 1. The material of the interconnect pads can be a single metal or alloy of gold, silver, copper, platinum, aluminum, nickel, chromium, indium, and tin. A metallization layer is provided on the inner wall of the interconnect via 4 and on the outer side of the substrate 1. The material of the metallization layer can be a single metal or alloy of gold, silver, copper, platinum, aluminum, nickel, chromium, indium, and tin. Figure 2 and Figure 3 Reference numeral 8 represents the interconnect via metallization layer. The metal of the inner wall of the interconnect via 4 is consistent with the metal of the interconnect pad. In this embodiment, the inner wall of the interconnect via 4 and the outer side of the substrate 1 are plated with a gold layer with a thickness of 4 micrometers. Ground pads with a width of 0.1 to 5 millimeters are also provided around the surface and bottom of the substrate 1.

[0059] The bottom substrate 1 is used as the starting stacking board. Then, a second substrate 1 is placed on the starting stacking board and interconnected with the starting stacking board. Multiple substrates 1 are stacked and connected in this manner. Two adjacent substrates 1 are connected as follows: First, one substrate 1 is placed as the lower substrate 1. Another substrate 1 is placed on top of the lower substrate 1 as the upper substrate 1. The interconnect vias 4 on the upper substrate 1 are aligned with the interconnect pads on the lower substrate 1 using a limiting clamp. The two substrates 1 are then pressed together. A metal ball is placed in the interconnect via 4 of the upper substrate 1. A special bonding wedge 9 is used to flatten and deform the metal ball 2 in the interconnect via 4. All the deformed metal balls 2 interconnect the upper and lower substrates 1. The bottom surface of the deformed metal ball 2 is interconnected with the interconnect pads of the lower substrate 1, and the side surface of the deformed metal ball 2 is interconnected with the metallization layer of the inner wall of the interconnect via 4 of the upper substrate 1. Using the above method, the substrates 1 are connected sequentially from bottom to top to achieve the stacked interconnection of multiple substrates 1 with extremely small interconnect gaps between layers.

[0060] The interconnect pads correspond to the interconnect vias 4 in position, and the interconnect vias 4 are adapted to the shapes of the interconnect pads. The size of the interconnect pad is greater than or equal to the size of the interconnect via 4. The shape of the interconnect via 4 can be circular or polygonal, and the shape of the interconnect pad can also be circular or polygonal. When the shape of the interconnect via 4 is circular, the error between the interconnect pad and the interconnect via 4 does not exceed 10% of the diameter of the interconnect via 4. The diameter of the interconnect via 4 is 0.05–2 mm, and the diameter of the interconnect pad is 0.06–2 mm. A metal ball is machined according to the diameter of the interconnect via 4. The diameter of the metal ball is slightly smaller than the diameter of the interconnect via 4, and the diameter of the metal ball is usually 85–95% of the diameter of the interconnect via 4, which facilitates easy placement of the metal ball into the interconnect via 4 during interconnection. The diameter of the metal ball is 0.04–1.9 mm, and the material of the metal ball can be a single metal such as gold, silver, copper, platinum, aluminum, nickel, chromium, indium, or tin, or their alloys. In this embodiment, the diameter of the interconnecting via 4 is 0.25 mm, and the metal ball is a gold ball with a diameter of 0.2 mm. The end of the bonding wedge 9 is a cylinder or a multi-faceted cylinder, and the end size of the bonding wedge 9 is 0.03–1.8 mm. The material of the bonding wedge 9 can be tungsten carbide cemented carbide, titanium carbide cemented carbide, alumina ceramic, zirconium oxide ceramic, cermet, or ruby ​​petroleum stone.

[0061] The stacked and fixedly connected multilayer substrate 1 is assembled as a three-dimensional packaged product within a frame 11. In this embodiment, the frame 11 is a metal frame with a height of 2.6 mm and a thickness of 0.5 mm. The inner side of the frame 11 is plated with nickel-gold, and the outer side is plated with nickel. The gap between the side of the product and the frame 11 is filled with solder A3, and the side of the product is soldered to the frame 11. The top and bottom surfaces of the product after the frame 11 is soldered are printed with solder B10. The melting point of the solder is 120–400°C, and the solder can be pure tin, tin-lead alloy, tin-bismuth alloy, tin-silver-copper alloy, tin-antimony alloy, gold-tin alloy, gold-germanium alloy, pure indium, indium-lead alloy, or indium-tin alloy. In this embodiment, the gap between the side of the product and the frame 11 is filled with indium-lead alloy, and the side of the product is soldered to the frame 11. After the frame 11 is welded, the top and bottom surfaces of the product are printed with indium lead solder paste with a melting point of 185°C. The metal bumps formed by the indium lead solder paste printed on the top and bottom surfaces of the product are heated in a reflow oven at 210°C to form spheres.

[0062] This embodiment further proposes a three-dimensional packaging interlayer interconnection method, including the following steps:

[0063] S1: Prepare substrate 1 and frame 11:

[0064] S11: Prepare 7 alumina ceramic substrates with a thickness of 0.38 mm. According to the circuit structure, make holes in each substrate 1. Make embedded device through holes at the positions where embedded devices need to be set on the substrate 1. Make interconnection through holes 4 at the positions where interconnection needs to be performed on the substrate 1. The diameter of the interconnection through holes 4 is 0.25 mm. Then, according to the circuit structure, prepare the corresponding circuit and interconnection pads on the substrate 1. During the process, the inner wall of the interconnection through holes 4 and the outer side of the substrate 1 are gold plated with a gold plating thickness of 4 micrometers.

[0065] S12: Prepare a metal frame 11. The material of the frame 11 is Kovar alloy 4J34. When processing the frame 11, chamfer the outer side of the frame 11. The height of the frame 11 is 2.6 mm and the thickness is 0.5 mm. The inner side of the frame 11 is plated with nickel gold and the outer side is plated with nickel.

[0066] S2: The alumina ceramic substrates processed by thin film technology are micro-assembled. The assembly process includes steps such as die bonding, flip-chip bonding, wire bonding, and functional index testing. After passing the test, each substrate 1 is placed on one side in sequence for later use.

[0067] S3: Select an alumina ceramic substrate as the starting stacking board, place it in the limiting fixture, then place the second alumina ceramic substrate 1 on the starting stacking board, adjust the limiting fixture, align the interconnect via 4 of the upper substrate 1 with the interconnect pad of the lower substrate 1, and press the two substrates 1 together.

[0068] S4: Place gold balls with a diameter of 0.2 mm into the interconnect vias 4 of the upper substrate 1 in sequence, and carefully check to ensure that there is a gold ball in each interconnect via 4;

[0069] S5: As Figure 3 As shown, the stacked substrates 1 are placed on the worktable of an ultrasonic bonding machine. Using a dedicated bonding wedge 9, the bonding parameters are adjusted, and each gold ball is flattened and deformed in sequence. At this time, all the deformed gold balls interconnect the upper and lower substrates 1. The bottom surface of the deformed gold ball is interconnected with the interconnection pad of the lower substrate 1, and the side surface of the deformed gold ball is interconnected with the metallization layer of the inner wall of the interconnection through-hole 4 of the upper substrate 1. The total bonding strength between the upper and lower substrates 1 is linearly related to the number of interconnection points between the boards. During bonding, the bonding temperature does not exceed 150°C, and only one gold ball is bonded at a time to ensure that each gold ball is bonded in place.

[0070] S6: Following steps S3 to S5, repeat the operation to stack the remaining 5 substrates 1 sequentially to achieve interconnection;

[0071] S7: The stacked multi-layer ceramic three-dimensional packaging products are placed into the frame 11. Indium-lead alloy with a melting point of 220 degrees is placed in the gap between the product side and the frame 11. The product is placed in a vacuum eutectic furnace for heating. The indium-lead alloy melts and fills the gap to complete the welding of the frame 11 and the product.

[0072] S8: Place the product with the welded frame 11 under the stencil and print indium lead solder paste with a melting point of 185℃ on the top and bottom surfaces of the product respectively.

[0073] S9: Place the product in a 210-degree reflow oven to heat the metal bumps formed by the indium lead solder paste into a spherical shape, and finally clean it;

[0074] S10: Place the product in the test fixture for testing, and after passing the test, vacuum pack it and put it into storage.

[0075] Example 2

[0076] The difference between this embodiment and Embodiment 1 is that: it is not limited to using ultrasonic bonding to deform the metal spheres; hot pressing bonding can also be used to deform the metal spheres. Both processes produce excellent interconnection results. For metal spheres with small diameters (usually less than 300 micrometers), ultrasonic bonding should be used whenever possible because the wedge end of the ultrasonic bonding tool can be processed to be even smaller. For metal spheres with large diameters, both ultrasonic bonding and hot pressing bonding can achieve good interconnection results.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for interlayer interconnection in three-dimensional packaging, characterized in that: Includes the following steps: S1: Prepare multiple substrates and a frame. The substrates have embedded device vias and interconnect vias. Corresponding circuits and interconnect pads are fabricated on the substrates. The inner walls of the interconnect vias are provided with a metallization layer. S2: Micro-assemble each substrate separately. The assembly process includes die bonding, flip-chip bonding, wire bonding, and functional index testing. After passing the test, place each substrate on one side in order for later use. S3: Select a substrate as the starting stacking board, place it in the limiting fixture, then place the second substrate on the starting stacking board, adjust the limiting fixture to align the interconnect vias of the upper substrate with the interconnect pads of the lower substrate, and press the two substrates together. S4: Place the metal balls into the interconnect vias of the upper substrate one by one, carefully check and ensure that there is a metal ball in each interconnect via; S5: Place the stacked substrates on the ultrasonic bonding machine table, use a special bonding wedge, adjust the bonding parameters, and flatten and deform each metal ball in sequence. At this time, all the deformed metal balls will interconnect the upper and lower substrates. The bottom surface of the deformed metal ball is interconnected with the interconnection pad of the lower substrate, and the side surface of the deformed metal ball is interconnected with the metallization layer of the interconnection through hole of the upper substrate. S6: Following the steps of S3 to S5, repeat the operation to stack the remaining substrates in sequence to achieve interconnection; S7: The stacked multi-layer 3D packaging products are placed into the frame, and soft solder B is installed in the gap between the product side and the frame. The product is then placed in a vacuum eutectic furnace for heating. The soft solder B melts and fills the gap to complete the welding between the frame and the product. S8: Place the product with the welded frame under the stencil and print solder A on the top and bottom surfaces of the product respectively; S9: Place the product in a reflow oven to heat the metal bumps formed by the solder A into a spherical shape, and finally clean it; S10: Place the product in the test fixture for testing, and after passing the test, vacuum pack it and put it into storage.

2. The interlayer interconnection method for three-dimensional packaging according to claim 1, characterized in that: S1 specifically includes: S11: Prepare multiple substrates, make holes in each substrate according to the circuit structure, make through holes for embedded devices at the locations where embedded devices need to be set on the substrate, and make interconnection through holes at the locations where interconnection needs to be performed on the substrate. Then, according to the circuit structure, prepare corresponding circuits and interconnection pads on the substrate. During the process, gold plating is performed on the inner wall of the interconnection through holes and the outer side of the substrate. S12: Prepare a metal frame. When processing the frame, chamfer the outer side of the frame, plate the inner side of the frame with nickel-gold, and plate the outer side with nickel.

3. The interlayer interconnection method for three-dimensional packaging according to claim 2, characterized in that: S11 also includes: grounding pads arranged around the surface and bottom of the substrate.

4. The interlayer interconnection method for three-dimensional packaging according to claim 1, characterized in that: In S5, the bonding temperature does not exceed 150°C during bonding, and only one metal ball is bonded at a time.

5. The interlayer interconnection method for three-dimensional packaging according to claim 1, characterized in that: In S7, an indium-lead alloy with a melting point of 220 degrees Celsius is installed in the gap between the side of the product and the frame.

6. The interlayer interconnection method for three-dimensional packaging according to claim 5, characterized in that: In S8, indium lead solder paste with a melting point of 185°C is printed on the top and bottom surfaces of the product. In S9, the product is placed in a 210-degree reflow oven to heat the metal bumps formed by indium lead solder paste into a spherical shape.

7. A three-dimensional encapsulated interlayer interconnect structure, characterized in that: It is obtained by using the interlayer interconnection method of the three-dimensional packaging as described in any one of claims 1-6.

8. The interlayer interconnect structure of the three-dimensional packaging according to claim 7, characterized in that: The substrate includes multiple stacked substrates. Embedded device vias are provided at the locations where embedded devices need to be installed on the substrates. Interconnection vias are provided at the locations where the substrates need to be interconnected with another substrate. Corresponding circuits and interconnection pads are prepared on the surface and bottom of the substrates according to the circuit structure. A metallization layer is provided on the inner wall of the interconnection vias. The interconnect vias of the upper substrate are aligned with the interconnect pads of the lower substrate. Metal balls are placed inside the interconnect vias. The metal balls are flattened and deformed by an ultrasonic bonding machine. All the deformed metal balls interconnect the upper and lower substrates. The bottom surface of the deformed metal balls is interconnected with the interconnect pads of the lower substrate, and the side surface of the deformed metal balls is interconnected with the metallization layer of the inner wall of the interconnect vias of the upper substrate. After stacking, the substrates are assembled in the frame, and the substrates are fixedly connected to the frame.

9. The interlayer interconnect structure of the three-dimensional packaging according to claim 8, characterized in that: The substrate can be FR-4 substrate, alumina substrate, zirconia substrate, beryllium oxide substrate, aluminum nitride substrate, silicon substrate, quartz substrate, glass substrate, LCP substrate, LTCC substrate or HTCC substrate.

10. The interlayer interconnect structure of the three-dimensional packaging according to claim 8, characterized in that: The substrate thickness is 0.1–5 mm, and the diameter of the interconnect vias is 0.05–2 mm.

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