Method for evaluating reliability of dielectric layer and test system for evaluating reliability of dielectric layer

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a method for evaluating the reliability of a dielectric layer and a test system for evaluating the reliability of a dielectric layer. The method includes: providing a memory, the memory including a plurality of sub-word line drivers and a plurality of sub-word lines, each sub-word line driver including a plurality of transistors, each transistor including a gate, a source, a drain, and a dielectric layer, the plurality of transistors sharing the gate and the source, and the plurality of sub-word lines being electrically connected to the plurality of drains in a one-to-one correspondence; providing a pre-charge command to the memory to pre-charge at least one sub-word line driver, and all sub-word lines being in an off state, at least one sub-word line driver undergoing at least one pre-charge, and obtaining in real time the actual duration experienced by each pre-charge; the dielectric layer in the sub-word line driver undergoing pre-charge being the target dielectric layer, and realizing the reliability evaluation of the target dielectric layer based on the actual duration. Embodiments of the present disclosure can at least realize the reliability evaluation of the target dielectric layer in the sub-word line driver.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductors, and provide a method for evaluating the reliability of a dielectric layer and a test system for evaluating the reliability of a dielectric layer. Background Art

[0002] As the integration density of memories becomes higher and higher, the thickness of the dielectric layer of transistors in the memories becomes smaller and smaller. Moreover, as the dielectric layer in the transistor continues to develop in the direction of thin films, it is not easy to reduce the power supply voltage in the memory and the voltages on various circuits. Therefore, under a relatively high electric field strength, higher requirements are put forward for the anti-electricity performance of the dielectric layer thin film. Poor anti-electricity performance of the dielectric layer will cause instability of the electrical parameters of the memory, such as threshold voltage drift, transconductance decrease, or leakage current increase, etc. Further, it will cause breakdown of the dielectric layer, resulting in failure of the memory and paralysis of the entire integrated circuit. Therefore, it is necessary to evaluate and test the reliability of the dielectric layer to evaluate the reliability of the memory.

[0003] Currently, to evaluate the reliability of a dielectric layer, generally, tests are performed on the dielectric layer that needs to be evaluated for reliability. An external circuit is electrically connected to the dielectric layer, and the voltage across the dielectric layer when it breaks down, the current flowing through the dielectric layer, and the time elapsed from the start of the test to breakdown are measured in real time. The reliability of the dielectric layer is characterized by the above parameters, and the service life of the dielectric layer can be predicted based on this.

[0004] However, currently, there is a lack of a method for evaluating the reliability of the dielectric layers of multiple transistors in a memory, such as the dielectric layer in a sub-word line driver. Summary of the Invention

[0005] Embodiments of the present disclosure provide a method for evaluating the reliability of a dielectric layer and a test system for evaluating the reliability of a dielectric layer, which is at least beneficial to realizing the reliability evaluation of the target dielectric layer in a sub-word line driver.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for evaluating the reliability of a dielectric layer, including: providing a memory, the memory includes a plurality of sub-word line drivers and a plurality of sub-word lines, each of the sub-word line drivers includes a plurality of transistors, each of the transistors includes a gate, a source, a drain, and a dielectric layer, the plurality of transistors share the gate and the source, and the plurality of sub-word lines are electrically connected to the plurality of drains in a one-to-one correspondence; providing a precharge command to the memory, precharging at least one of the sub-word line drivers, and all the sub-word lines are in an off state; at least one of the sub-word line drivers undergoes at least one precharge, and the actual duration experienced by each precharge is obtained in real time; the dielectric layer in the sub-word line driver undergoing the precharge is the target dielectric layer, and the reliability of the target dielectric layer is evaluated based on the actual duration.

[0007] In some embodiments, the step of evaluating the reliability of the target dielectric layer based on the actual duration includes: judging in real time the magnitude relationship between the actual duration and the maximum duration allowed for the precharge. If the actual duration is greater than the maximum duration, it is determined that the target dielectric layer fails.

[0008] In some embodiments, in the step of obtaining in real time the actual duration experienced by each precharge, it further includes: obtaining in real time the standby current of the memory in the step of each precharge, where the standby current is the static current when all storage units in the memory are in an idle state during the precharge step; judging in real time the magnitude relationship between the standby current and the maximum standby current allowed for the memory during the precharge. If the actual duration is less than or equal to the maximum duration, and the standby current is greater than the maximum standby current, it is determined that the target dielectric layer fails.

[0009] In some embodiments, the memory further includes a first terminal for applying a working voltage and a second terminal for grounding. The step of obtaining in real time the standby current in the step of each precharge includes: during the precharge step, obtaining in real time the current flowing from the first terminal through the second terminal.

[0010] In some embodiments, the standby current obtained for the first time is used as the initial standby current, and the ratio of the maximum standby current to the initial standby current is greater than or equal to 2.

[0011] In some embodiments, in the step of precharging at least one of the sub-word line drivers, the gate is at a first potential, the plurality of drains are all at a second potential, and the second potential is lower than the first potential, and both the first potential and the second potential are constant values.

[0012] In some embodiments, the evaluation method further includes evaluating the reliability of the dielectric layer multiple times, and in different evaluation steps, the magnitude of the first potential is different.

[0013] In some embodiments, in the step of pre-charging at least one of the sub-word line drivers, the gate is at a first potential, and multiple drains are all at a second potential, and the second potential is lower than the first potential. While the second potential is a constant value, in any of the pre-charging steps, the magnitude of the first potential gradually increases with the pre-charging time.

[0014] In some embodiments, the evaluation method further includes evaluating the reliability of the dielectric layer multiple times, and in different evaluation steps, the amplitude of the gradual increase of the magnitude of the first potential with the pre-charging time is different.

[0015] In some embodiments, each of the sub-word line drivers includes at least 4 transistors arranged in an array, and the common gate of the multiple transistors is a ring structure.

[0016] In some embodiments, in the step of providing the pre-charging instruction to the memory, pre-charging is performed on all the sub-word line drivers in the memory; all the sub-word line drivers simultaneously undergo at least one pre-charging, and the actual duration experienced by each pre-charging is obtained in real time; the reliability evaluation of the target dielectric layer is realized based on the actual duration.

[0017] In some embodiments, the memory includes multiple main word lines, and the multiple main word lines are electrically connected to the gates of the multiple sub-word line drivers in a one-to-one correspondence; in the step of providing the pre-charging instruction to the memory, at least one main word line controls at least one gate to be at a first potential.

[0018] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a test system for evaluating the reliability of a dielectric layer, including: a memory, the memory includes a plurality of sub-word line drivers and a plurality of sub-word lines, each of the sub-word line drivers includes a plurality of transistors, each of the transistors includes a gate, a source, a drain, and a dielectric layer, the plurality of transistors share the gate and the source, and the plurality of sub-word lines are electrically connected to the plurality of drains in a one-to-one correspondence; a pre-charge module, configured to: provide a pre-charge instruction to the memory, pre-charge at least one of the sub-word line drivers, and all the sub-word lines are in an off state; an acquisition module, during the process of the memory operating in a cycle, the sub-word line driver experiences at least one pre-charge, the acquisition module is configured to: acquire the actual duration experienced by each pre-charge in real time; a judgment module, the dielectric layer in the sub-word line driver that performs the pre-charge is the target dielectric layer, the judgment module is configured to: evaluate the reliability of the target dielectric layer based on the actual duration.

[0019] In some embodiments, the dielectric layer in the sub-word line driver that performs the pre-charge is the target dielectric layer, and the judgment module includes: a parameter setting module, configured to: provide the maximum duration allowed for the pre-charge; a comparison module, configured to: judge the magnitude relationship between the actual duration and the maximum duration in real time, if the actual duration is greater than the maximum duration, determine that the target dielectric layer fails.

[0020] In some embodiments, the acquisition module is further configured to: in the step of pre-charging, acquire the standby current of the memory, and the standby current is the static current when all storage units in the memory are in an idle state in the step of pre-charging.

[0021] In some embodiments, the parameter setting module is further configured to: provide the maximum standby current allowed for the memory during the pre-charge; the comparison module is further configured to: judge the magnitude relationship between the standby current and the maximum standby current in real time, if the actual duration is less than or equal to the maximum duration, and the standby current is greater than the maximum standby current, determine that the target dielectric layer fails.

[0022] In some embodiments, in the step of pre-charging at least one of the sub-word line drivers, the gate is at a first potential, the plurality of drains are all at a second potential, and the second potential is lower than the first potential, and the pre-charge module is further configured to: control both the first potential and the second potential to be constant values.

[0023] In some embodiments, in the step of pre-charging at least one of the sub-word line drivers, the gate is at a first potential, a plurality of the drains are all at a second potential, and the second potential is lower than the first potential. The pre-charging module is further configured to: while controlling the second potential to be a constant value, in any one of the pre-charging steps, control the magnitude of the first potential to gradually increase with the progress time of the pre-charging.

[0024] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0025] In the above technical solution, by utilizing the working characteristics of the memory itself, in the pre-charging stage, at least one sub-word line driver is pre-charged, so that all the transistors in at least one sub-word line driver being pre-charged are in the on state, and in the pre-charging stage, all the sub-word lines are in the off state, so that the drains of a plurality of transistors electrically connected to the sub-word lines are all at the same potential. On the one hand, if one sub-word line driver is pre-charged, all the transistors in the sub-word line driver share the gate, which is beneficial to making the voltages across the dielectric layers of all the transistors in the sub-word line driver consistent, thereby realizing the reliability evaluation of the dielectric layers of all the transistors in the sub-word line driver. On the other hand, in the pre-charging stage, a plurality of sub-word line drivers can be pre-charged, then the transistors in the plurality of sub-word line drivers are all in the on state, and the voltages applied to the plurality of shared gates of the plurality of sub-word line drivers in the pre-charging stage are the same, which is beneficial to making the voltages across the plurality of dielectric layers in the plurality of sub-word line drivers being pre-charged consistent, thereby simultaneously realizing the reliability evaluation of the plurality of dielectric layers in the plurality of sub-word line drivers being pre-charged. In addition, based on the actual duration experienced by the pre-charging, it is judged whether the anti-electricity performance of the target dielectric layer has decreased and whether the target dielectric layer has failed and been broken down. Without additionally adding test equipment for measuring the voltage across the target dielectric layer and the current flowing through the target dielectric layer, the reliability evaluation of the target dielectric layer can be realized. Description of the Drawings

[0026] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the figures do not constitute a proportional limitation.

[0027] Figure 1 It is a schematic circuit diagram for currently evaluating the reliability of a transistor dielectric layer;

[0028] Figure 2 It is a flowchart of a method for evaluating the reliability of a dielectric layer provided by an embodiment of the present disclosure;

[0029] Figure 3A top view structural schematic diagram of a sub-word line driver provided by an embodiment of the present disclosure;

[0030] Figure 4 A circuit schematic diagram for schematically illustrating a method for evaluating the reliability of a dielectric layer provided by an embodiment of the present disclosure;

[0031] Figure 5 A broken line schematic diagram showing the actual duration experienced by each pre-charge varying with the increase of the memory operation time provided by an embodiment of the present disclosure;

[0032] Figure 6 A broken line schematic diagram showing the standby current of the memory in each pre-charge step varying with the increase of the memory operation time provided by an embodiment of the present disclosure;

[0033] Figure 7 A functional module schematic diagram of a test system for evaluating the reliability of a dielectric layer provided by another embodiment of the present disclosure. Detailed implementation manners

[0034] Through analysis, it is found that as the dielectric layer in the transistor continuously develops towards the thin film direction, at a higher electric field strength, higher requirements are put forward for the dielectric breakdown resistance of the dielectric layer thin film. Therefore, it is necessary to evaluate and test the reliability of the dielectric layer to determine under what conditions the dielectric layer will be broken down. The breakdown of the dielectric layer generally includes time-dependent dielectric breakdown (TDDB) and time-zero dielectric breakdown (TZDB), where time-dependent dielectric breakdown is also called breakdown over time.

[0035] In the current evaluation methods, generally, the breakdown over time of the dielectric layer is tested. An external electric field is applied to the transistor, and parameters such as the breakdown charge and breakdown time are measured actually to characterize the dielectric breakdown resistance and reliability of the dielectric layer. In addition, when evaluating the reliability of the dielectric layer, generally, regular transistors are targeted, that is, the situation where multiple transistors do not share a gate, a source, a drain, or a dielectric layer. Then, the reliability evaluation is only for the dielectric layer of a certain specified transistor, and it is impossible to evaluate the dielectric layers of multiple transistors in the memory simultaneously.

[0036] Reference Figure 1 , Figure 1It is a circuit schematic diagram for currently evaluating the reliability of the dielectric layer of a transistor. An external power supply is directly applied to the gate 110 of a certain transistor 100. The anode of the external power supply is electrically connected to the gate 110, and the cathode of the external power supply is electrically connected to the substrate 130. The substrate 130 and the gate 110 are isolated by the dielectric layer 120. The voltage across the dielectric layer 120, that is, the voltage between the substrate 130 and the gate 110, is measured by a voltmeter. The current flowing through the dielectric layer 120 is tested by an ammeter. By observing the change in the measured current, it is judged whether the dielectric layer 120 fails. For example, if the current suddenly increases, it indicates that the dielectric layer 120 is broken down, and the time experienced during this period is the lifetime of the dielectric layer 120 at this voltage.

[0037] However, currently, there is a lack of a method for evaluating the reliability of the dielectric layers of multiple transistors in a memory, and there is also a lack of a method for simultaneously evaluating the reliability of multiple dielectric layers in a memory.

[0038] The present disclosure provides a method for evaluating the reliability of a dielectric layer and a test system for evaluating the reliability of a dielectric layer. In the method, during the pre-charging stage of the memory, at least one sub-word line driver is pre-charged, so that all the transistors in the at least one sub-word line driver being pre-charged are in the on state, and during the pre-charging stage, all sub-word lines are in the off state. On the one hand, if a sub-word line driver is pre-charged, all the transistors in the sub-word line driver are in the on state, thereby realizing the reliability evaluation of the dielectric layer in the sub-word line driver; on the other hand, during the pre-charging stage, if multiple sub-word line drivers are pre-charged, all the transistors in the multiple sub-word line drivers are in the on state, thereby simultaneously evaluating the reliability of multiple dielectric layers in the multiple sub-word line drivers being pre-charged. In addition, based on the actual duration of the pre-charging, it is judged whether the anti-electricity performance of the target dielectric layer has decreased and whether the target dielectric layer has failed and been broken down. Without additionally adding test equipment for measuring the voltage across the target dielectric layer and the current flowing through the target dielectric layer, the reliability evaluation of the target dielectric layer can be realized.

[0039] The following will elaborate on the embodiments of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are proposed for the readers to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be realized.

[0040] An embodiment of the present disclosure provides a method for evaluating the reliability of a dielectric layer. The following will elaborate in detail on the method for evaluating the reliability of a dielectric layer provided by an embodiment of the present disclosure in conjunction with the accompanying drawings. Figure 2A flowchart of a method for evaluating the reliability of a dielectric layer provided by an embodiment of the present disclosure; Figure 3 A top view structural schematic diagram of a sub - word line driver provided by an embodiment of the present disclosure; Figure 4 A circuit schematic diagram for schematically illustrating a method for evaluating the reliability of a dielectric layer provided by an embodiment of the present disclosure; Figure 5 A broken - line schematic diagram showing the actual duration experienced by each pre - charge varying with the increase of the memory operation time provided by an embodiment of the present disclosure; Figure 6 A broken - line schematic diagram showing the standby current of the memory in each pre - charge step varying with the increase of the memory operation time provided by an embodiment of the present disclosure.

[0041] It should be noted that, Figure 4 in which SWL represents the sub - word line, MWL represents the main - word line, and VKK represents the potential at which the common source 122 of the four transistors 102 is located.

[0042] With reference to Figure 2 and Figure 3 , the method for evaluating the reliability of the dielectric layer includes the following steps:

[0043] S101: Provide a memory (not shown in the figure), the memory includes a plurality of sub - word line drivers 101 and a plurality of sub - word lines (not shown in the figure), each sub - word line driver 101 includes a plurality of transistors 102, each transistor 102 includes a gate 112, a source 122, a drain 132, and a dielectric layer (not shown in the figure), the plurality of transistors 102 share the gate 112 and the source 122, and the plurality of sub - word lines are electrically connected to the plurality of drains 132 in one - to - one correspondence.

[0044] It should be noted that in the memory, the plurality of sub - word lines are located in the memory cell array, and the sub - word line driver 101 is used to apply a voltage to the sub - word lines in the memory cell array, so the sub - word line driver 101 can selectively control the plurality of sub - word lines and achieve a fast switching of the signal levels on the sub - word lines.

[0045] In some embodiments, with reference to Figure 3 and Figure 4, each sub - word - line driver 101 includes at least 4 transistors 102 arranged in an array, and the common gate 112 of the multiple transistors 102 is a ring structure. In one example, each sub - word - line driver 101 may include 4 transistors 102, the 4 transistors 102 are arranged in a 2×2 array, and the common gate 112 of the 4 transistors 102 is a ring structure. Thus, a sub - word - line driver 101 can simultaneously control 4 transistors 102 through a common gate 112. Since the drains 132 of the 4 transistors 102 are not shared, and a sub - word - line is electrically connected to one drain 132, a sub - word - line driver 101 can respectively control 4 sub - word - lines through the 4 drains 132, and the potential of the sub - word - line is the same as that of the drain 132 corresponding to the sub - word - line.

[0046] It should be noted that Figure 3 in the above, the ring structure is exemplified by a square ring, and the ring structure can also be a circular ring. In practical applications, the specific shape of the ring structure is not limited. In other embodiments, the common gate 112 can also be other shapes, such as a rectangle, as long as it corresponds to the channel regions of the 4 transistors 102. In addition, Figure 3 the dielectric layer is not shown in the above. In some embodiments, the dielectric layers of the 4 transistors 102 in a sub - word - line driver 101 can be the same film - layer structure, that is, the 4 transistors 102 share the dielectric layer, and the dielectric layer is located between the gate 112 and the channel regions of the transistors 102 to achieve insulation between the gate 112 and the channel regions of the transistors 102; in other embodiments, the dielectric layers of the 4 transistors 102 in a sub - word - line driver 101 can be a layered structure, that is, the two dielectric layers of adjacent transistors 102 are spaced apart from each other, and any one dielectric layer only needs to be located between the gate 112 and the channel region of the transistor 102 corresponding to the dielectric layer.

[0047] In some embodiments, the dielectric layer of the transistor 102 in the sub - word - line driver 101 is generally composed of a gate oxide layer, and the gate oxide layer is a silicon dioxide insulating film formed by oxidizing a silicon substrate at a high temperature. In other embodiments, the material of the dielectric layer of the transistor can include high - dielectric - constant materials such as silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide or praseodymium oxide.

[0048] S102: Provide a pre - charge command to the memory, pre - charge at least one sub - word - line driver 101, and all sub - word - lines are in the off state.

[0049] Among them, since all the sub-word lines are in the off state, the potentials of all the sub-word lines are the same. Therefore, the potentials of the drains 132 of all the transistors 102 in all the sub-word line drivers 101 electrically connected to the sub-word lines are the same, which is convenient for subsequently controlling the conduction or cutoff of the transistors 102 in multiple sub-word line drivers 101 by controlling the common gate 112 of the sub-word line drivers 101.

[0050] It should be noted that pre-charging at least one sub-word line driver 101 through a pre-charging command may include the following three cases:

[0051] In some embodiments, a single sub-word line driver 101 can be pre-charged through a pre-charging command. Since all the transistors 102 in the aforementioned single sub-word line driver 101 share the common gate 112, the potentials of the gates 112 of all the transistors 102 in the single sub-word line driver 101 are the same, and the potentials of the drains 132 of all the transistors 102 in the aforementioned single sub-word line driver 101 are also the same. This is conducive to making the voltages across the dielectric layers of all the transistors 102 in the aforementioned single sub-word line driver 101 consistent, so as to subsequently perform a reliability assessment on the dielectric layers of all the transistors 102 in the aforementioned single sub-word line driver 101, that is, the target dielectric layer.

[0052] In some other embodiments, multiple sub-word line drivers 101 can be pre-charged through a pre-charging command, then the potentials of the multiple common gates 112 in the aforementioned multiple sub-word line drivers 101 can be controlled to be the same, and the potentials of all the drains 132 of all the transistors 102 in the aforementioned multiple sub-word line drivers 101 are also the same. This is conducive to making the voltages across the multiple dielectric layers of all the transistors 102 in the aforementioned multiple sub-word line drivers 101 consistent, so as to subsequently perform a reliability assessment on the multiple dielectric layers of all the transistors 102 in the aforementioned multiple sub-word line drivers 101, that is, the target dielectric layer.

[0053] In still some other embodiments, all the sub-word line drivers 101 in the memory can be pre-charged through a pre-charging command, then the potentials of all the common gates 112 in all the sub-word line drivers 101 can be controlled to be the same, and the potentials of all the drains 132 in all the sub-word line drivers 101 are also the same. This is conducive to making the voltages across all the dielectric layers of all the transistors 102 in all the sub-word line drivers 101 consistent, so as to subsequently perform a reliability assessment on all the dielectric layers of all the transistors 102 in all the sub-word line drivers 101, that is, the target dielectric layer.

[0054] In the above three cases of precharging the sub - word line driver 101, the working characteristics of the memory itself are utilized. That is, in the pre - charging stage, at least one sub - word line driver 101 is pre - charged, so that all transistors in the at least one pre - charged sub - word line driver are in the on state, and in the pre - charging stage, all sub - word lines are in the off state. This is conducive to realizing the reliability evaluation of the dielectric layer in a single pre - charged sub - word line driver 101, or simultaneously realizing the reliability evaluation of multiple dielectric layers in multiple pre - charged sub - word line drivers 101.

[0055] In some embodiments, referring to Figure 3 , in the above three cases of precharging the sub - word line driver 101, the memory may further include multiple main word lines 103, and the multiple main word lines 103 are electrically connected to the gates 112 of the multiple sub - word line drivers 101 in a one - to - one correspondence; in the step of providing a pre - charging instruction to the memory, at least one main word line 103 controls at least one gate 112 to be at a first potential. It should be noted that the main word line 103 can extend through the memory cell array region. In this way, an electrical signal can be applied to a predetermined number of main word lines 103 in the peripheral circuit, and then the electrical signal is transmitted to a predetermined number of gates 112 electrically connected to the main word line 103 to pre - charge a predetermined number of sub - word line drivers 101. Here, the predetermined number can be one, multiple, or the total number corresponding to all sub - word line drivers 101 in the memory.

[0056] Among them, the step of pre - charging at least one sub - word line driver 101 can include the following two methods:

[0057] In some embodiments, in the step of pre - charging at least one sub - word line driver 101, the gate 112 is at a first potential, and multiple drains 132 are all at a second potential, and the second potential is lower than the first potential, and both the first potential and the second potential are constant values.

[0058] It should be noted that in practical applications, the transistor 102 can be an NMOS transistor. The first potential can be the voltage magnitude of the electrical signal applied to the gate 112 through the main word line 103, such as 3V, and the second potential can be 0V. Since multiple transistors 102 share the source 122, the source 122 can be grounded so that the potential of the source 122 is 0V. In this way, by controlling the voltage magnitude of the electrical signal applied to the gate 112 through the main word line 103, the voltage across the target dielectric layer can be known without the need for an additional voltage detection device to measure the voltage across the target dielectric layer, and the voltage across the target dielectric layer will not be interfered by an additional voltage detection device, which is conducive to improving the accuracy of obtaining the voltage across the target dielectric layer.

[0059] In addition, in practical applications, the reliability of the dielectric layer can be evaluated multiple times, and the magnitude of the first potential is different in different evaluation steps. In this way, it is beneficial to compare the differences in the stability of the target dielectric layer in the same sub-word line driver 101 under different voltage conditions. Furthermore, the differences in the dielectric breakdown resistance and failure time of the target dielectric layer in the same sub-word line driver 101 under different voltage conditions can also be compared.

[0060] In some other embodiments, in the step of pre-charging at least one sub-word line driver 101, the gate 112 is at the first potential, and multiple drains 132 are all at the second potential, and the second potential is lower than the first potential. While the second potential is a constant value, in any pre-charging step, the magnitude of the first potential gradually increases with the progress time of pre-charging.

[0061] It should be noted that in practical applications, the transistor 102 can be an NMOS transistor, and the first potential can be determined by the electrical signal applied to the gate 112 through the main word line 103. By changing the electrical signal, the magnitude of the first potential can be made to gradually increase with the progress time of pre-charging. For example, the first potential can gradually change from Vt to Vb, where Vt is the conduction threshold voltage of the transistor 102, and the magnitude of Vb is 80% of the breakdown voltage value of the transistor 102. In addition, the second potential can be 0V. Since multiple transistors 102 share the source 122, the source 122 can be grounded so that the potential of the source 122 is 0V. In this way, by controlling the change of the electrical signal applied to the gate 112 by the main word line 103, the change in the voltage across the target dielectric layer can be known without the need for an additional voltage detection device to measure the voltage across the target dielectric layer in real time, and the voltage across the target dielectric layer will not be interfered by the additional voltage detection device, which is beneficial to improving the accuracy of obtaining the voltage across the target dielectric layer. Moreover, since the magnitude of the voltage across the target dielectric layer may fluctuate during the actual operation of the target dielectric layer, in the evaluation method, by changing the magnitude of the first potential, it is beneficial to simulate the actual working state of the target dielectric layer, thereby improving the evaluation accuracy of the stability of the target dielectric layer.

[0062] In addition, in practical applications, the reliability of the dielectric layer can be evaluated multiple times, and the amplitude of the gradual increase of the magnitude of the first potential with the progress time of pre-charging is different in different evaluation steps. In this way, it is beneficial to compare the differences in the stability of the target dielectric layer in the same sub-word line driver 101 under different voltage conditions. Furthermore, the differences in the dielectric breakdown resistance and failure time of the target dielectric layer in the same sub-word line driver 101 under different voltage conditions can also be compared.

[0063] S103: At least one sub - word line driver undergoes at least one pre - charge, and the actual duration experienced by each pre - charge is obtained in real time.

[0064] In some embodiments, in the step of providing a pre - charge instruction to the memory, if all the sub - word line drivers in the memory are pre - charged, all the sub - word line drivers 101 will undergo at least one pre - charge simultaneously, and the actual duration experienced by each pre - charge is obtained in real time, which is beneficial to subsequent evaluation of the reliability of the dielectric layer in all the sub - word line drivers 101 in the memory, that is, to evaluate the reliability of the dielectric layer of the entire memory.

[0065] In some embodiments, in the step of obtaining the actual duration experienced by each pre - charge in real time, it may further include: obtaining the standby current of the memory in real time during each pre - charge step, where the standby current is the static current when all the memory cells in the memory are in an idle state during the pre - charge step.

[0066] Since as the usage time of the dielectric layer in the sub - word line driver 101 increases, the anti - electric performance of the dielectric layer will change, which will not only affect the actual duration experienced by the pre - charge, but also affect the standby current of the memory. Therefore, obtaining the standby current of the memory during the pre - charge step is beneficial to subsequent comprehensive analysis of the reliability of the target dielectric layer based on the obtained actual duration experienced by the pre - charge and the standby current of the memory, which is beneficial to further improving the accuracy of the evaluation of the stability of the target dielectric layer.

[0067] In some embodiments, the memory further includes a first terminal for applying a working voltage and a second terminal for grounding. The step of obtaining the standby current in real time during each pre - charge step may include: obtaining the current flowing from the first terminal to the second terminal in real time during the pre - charge step.

[0068] S104: The dielectric layer in the pre - charged sub - word line driver 101 is the target dielectric layer, and the reliability of the target dielectric layer is evaluated based on the actual duration.

[0069] In some embodiments, in the step of providing a pre - charge instruction to the memory, if all the sub - word line drivers 101 in the memory are pre - charged and all the sub - word line drivers 101 will undergo at least one pre - charge simultaneously, then the actual duration experienced by each pre - charge is obtained in real time, so that the reliability of the target dielectric layer can be evaluated based on the actual duration.

[0070] It should be noted that, as can be seen from the above description, based on the pre-charge command, at least one sub-word line driver 101 is pre-charged. The target dielectric layer can be the dielectric layers of all the transistors 102 in a single sub-word line driver 101, can be the multiple dielectric layers of all the transistors 102 in multiple sub-word line drivers 101, or can also be all the dielectric layers of all the transistors 102 in all the sub-word line drivers 101 in the memory.

[0071] In some embodiments, the steps of realizing the reliability evaluation of the target dielectric layer based on the actual duration include: judging in real time the magnitude relationship between the actual duration and the maximum duration allowed for pre-charging. If the actual duration is greater than the maximum duration, it is determined that the target dielectric layer fails. In other embodiments, if the actual duration is greater than or equal to the maximum duration, it can also be determined that the target dielectric layer fails. Among them, the maximum duration can be 18 ns. In practical applications, the maximum duration allowed for pre-charging can be provided in the steps of realizing the reliability evaluation of the target dielectric layer based on the actual duration, or can also be provided in any step before the step of judging the magnitude relationship between the actual duration and the maximum duration allowed for pre-charging, that is, the maximum duration is preset.

[0072] In some embodiments, while determining that the target dielectric layer fails, the total working duration of the memory, that is, the service life of the target dielectric layer, can be recorded.

[0073] In some embodiments, the method for evaluating the reliability of the dielectric layer can further include: judging in real time the magnitude relationship between the standby current and the maximum standby current allowed to pass through the memory during pre-charging. If the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, it is determined that the target dielectric layer fails. In practical applications, the maximum standby current can be provided after judging in real time the magnitude relationship between the actual duration and the maximum duration and before determining that the target dielectric layer fails, or can also be provided in any step before the step of judging the magnitude relationship between the standby current and the maximum standby current, that is, the maximum standby current is preset.

[0074] Since as the usage time of the dielectric layer in the sub-word line driver 101 increases, the anti-electricity performance of the dielectric layer will change, which will not only affect the actual duration experienced by pre-charging, but also affect the standby current of the memory. Therefore, there is a situation where the standby current has become very large, for example, greater than the maximum standby current, when the actual duration experienced by pre-charging has not yet exceeded the maximum duration. At this time, the dielectric layer has failed. Therefore, if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, determining that the target dielectric layer fails is beneficial to more accurately determine the failure moment of the target dielectric layer and more efficiently determine whether the target dielectric layer fails.

[0075] In other embodiments, if the actual duration is less than or equal to the maximum duration and the standby current is greater than or equal to the maximum standby current, it can be determined that the target dielectric layer fails; or, if the actual duration is less than the maximum duration and the standby current is greater than or equal to the maximum standby current, it can be determined that the target dielectric layer fails; or, if the actual duration is less than the maximum duration and the standby current is greater than the maximum standby current, it can be determined that the target dielectric layer fails.

[0076] In some embodiments, the standby current obtained for the first time is used as the initial standby current, and the ratio of the maximum standby current to the initial standby current is greater than or equal to 2.

[0077] In some embodiments, referring to Figure 5 , T RP is the actual duration experienced by each pre-charge, T is the operating time of the memory, and it can be seen from Figure 5 that T RP shows a gradually increasing trend as the operating time of the memory increases. Therefore, as the operating time of the memory increases, the value of T RP will gradually approach the maximum duration allowed for pre-charge. In addition, referring to Figure 6 , I DD2P is the standby current of the memory in each step of pre-charge, T is the operating time of the memory, and it can be seen from Figure 6 that I DD2P shows a gradually increasing trend as the operating time of the memory increases. Therefore, as the operating time of the memory increases, the value of I DD2P will gradually approach the maximum standby current allowed for the memory during pre-charge. Combining Figure 5 and Figure 6 it can be known that the reliability of the dielectric layer of transistor 102 shows a gradually declining trend as the working duration of the dielectric layer increases. In summary, by utilizing the working characteristics of the memory itself, during the pre-charge stage, at least one sub-word line driver 101 is pre-charged so that all transistors 102 in the at least one pre-charged sub-word line driver 101 are in the conducting state, and during the pre-charge stage, all sub-word lines are in the off state. On the one hand, if a sub-word line driver 101 is pre-charged, it is possible to evaluate the reliability of the dielectric layer of all transistors 102 in this single sub-word line driver 101, that is, the target dielectric layer; on the other hand, during the pre-charge stage, multiple sub-word line drivers 101 can be pre-charged, and it is possible to evaluate the reliability of multiple dielectric layers in the multiple pre-charged sub-word line drivers 101. In addition, based on the actual duration experienced during pre-charge, it is possible to determine whether the anti-electricity performance of the target dielectric layer has decreased and whether the target dielectric layer has failed or been broken down, and it is possible to evaluate the reliability of the target dielectric layer without the need to additionally increase test equipment to measure the voltage across the target dielectric layer and the current flowing through the target dielectric layer.

[0078] Another embodiment of the present disclosure also provides a test system for evaluating the reliability of a dielectric layer, which is used to implement the above-mentioned method for evaluating the reliability of a dielectric layer. The following will describe in detail the test system for evaluating the reliability of a dielectric layer provided by another embodiment of the present disclosure with reference to the accompanying drawings. Figure 7 It is a schematic diagram of the functional modules of the test system for evaluating the reliability of a dielectric layer provided by another embodiment of the present disclosure.

[0079] Referring to Figure 7 , the test system for evaluating the reliability of a dielectric layer includes: a memory 200, the memory includes a plurality of sub-word line drivers and a plurality of sub-word lines, each sub-word line driver includes a plurality of transistors, each transistor includes a gate, a source, a drain and a dielectric layer, the plurality of transistors share the gate and the source, and the plurality of sub-word lines are electrically connected to the plurality of drains in one-to-one correspondence; a pre-charge module 201, configured to: provide a pre-charge instruction to the memory, pre-charge at least one sub-word line driver, and all sub-word lines are in an off state; an acquisition module 202, during the operation of the memory cycle, the sub-word line driver undergoes at least one pre-charge, and the acquisition module is configured to: acquire the actual duration experienced by each pre-charge in real time; a judgment module 203, the dielectric layer in the pre-charged sub-word line driver is the target dielectric layer, and the judgment module is configured to: evaluate the reliability of the target dielectric layer based on the actual duration.

[0080] In some embodiments, the dielectric layer in the pre-charged sub-word line driver is the target dielectric layer, and the judgment module 203 includes: a parameter setting module 213, configured to: provide the maximum duration allowed for pre-charging; a comparison module 223, configured to: judge the magnitude relationship between the actual duration and the maximum duration in real time, and if the actual duration is greater than the maximum duration, determine that the target dielectric layer fails. In this way, the failure time of the target dielectric layer can be indirectly obtained based on the working characteristics of the memory during the pre-charge stage and the actual duration of the pre-charge.

[0081] In some embodiments, the acquisition module 202 can also be configured to: in the pre-charge step, acquire the standby current of the memory, and the standby current is the static current when all storage units in the memory are in an idle state during the pre-charge step. In this way, it is beneficial to comprehensively analyze the reliability of the target dielectric layer based on the actual duration of the pre-charge and the standby current acquired, and it is beneficial to improve the accuracy of the evaluation of the stability of the target dielectric layer.

[0082] In addition, the parameter setting module 213 can also be configured to provide the maximum standby current that the memory allows to pass through during pre-charging; the comparison module 223 can also be configured to continuously determine the magnitude relationship between the standby current and the maximum standby current. If the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, the target dielectric layer fails.

[0083] As the usage time of the dielectric layer in the sub-word line driver 101 increases, the dielectric withstand voltage performance of the dielectric layer will change, which will not only affect the actual duration of pre-charging, but also affect the standby current of the memory. Therefore, there is a situation where the standby current has become very large, such as greater than the maximum standby current, before the actual duration of pre-charging has exceeded the maximum duration. At this time, the dielectric layer has failed. Therefore, if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, it is determined that the target dielectric layer has failed. In this way, it is beneficial to more accurately determine the failure time of the target dielectric layer and more efficiently determine whether the target dielectric layer has failed.

[0084] Among them, pre-charging at least one sub-word line driver 101 can include the following two methods:

[0085] In some embodiments, in the step of pre-charging at least one sub-word line driver 101, the gate 112 is at a first potential, and multiple drains 132 are all at a second potential, and the second potential is lower than the first potential. The pre-charging module can also be configured to control both the first potential and the second potential to be constant values. In this way, by controlling the first potential and the second potential, the voltage change across the target dielectric layer can be known without the need for an additional voltage detection device to measure the voltage across the target dielectric layer in real time, and the voltage across the target dielectric layer will not be interfered by the additional voltage detection device, which is beneficial to improving the accuracy of obtaining the voltage across the target dielectric layer.

[0086] In other embodiments, in the step of pre-charging at least one sub-word line driver 101, the gate 112 is at a first potential, and multiple drains 132 are all at a second potential, and the second potential is lower than the first potential. The pre-charging module can also be configured to, while controlling the second potential to be a constant value, control the magnitude of the first potential to gradually increase with the pre-charging time in any pre-charging step. Since the voltage magnitude across the target dielectric layer may fluctuate during the actual operation of the target dielectric layer, in the evaluation method, changing the magnitude of the first potential is beneficial to simulating the actual working state of the target dielectric layer, thereby being beneficial to improving the accuracy of evaluating the stability of the target dielectric layer.

[0087] In summary, the pre-charge module 201 pre-charges at least one sub-word line driver 101, so that all transistors 102 in the at least one sub-word line driver 101 being pre-charged are in the on state, and during the pre-charge phase, all sub-word lines are in the off state. On the one hand, the pre-charge module 201 can pre-charge a single sub-word line driver 101, and the reliability assessment of the dielectric layer, i.e., the target dielectric layer, of all transistors 102 in the single sub-word line driver 101 can be achieved through the acquisition module 202 and the judgment module 203. On the other hand, the pre-charge module 201 can also pre-charge multiple sub-word line drivers 101, and the reliability assessment of multiple dielectric layers in the multiple sub-word line drivers 101 being pre-charged can be achieved through the acquisition module 202 and the judgment module 203. In addition, based on the actual duration of the pre-charge experience, it is determined whether the anti-electricity performance of the target dielectric layer has decreased and whether the target dielectric layer has failed and been broken down. Without the need to additionally increase test equipment for measuring the voltage across the target dielectric layer and the current flowing through the target dielectric layer, the reliability assessment of the target dielectric layer can be achieved.

[0088] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A method for evaluating the reliability of a dielectric layer, characterized in that, Including: Providing a memory, the memory including a plurality of sub - word line drivers and a plurality of sub - word lines, each of the sub - word line drivers including a plurality of transistors, each of the transistors including a gate, a source, a drain, and a dielectric layer, the plurality of transistors sharing the gate and the source, and the plurality of sub - word lines being electrically connected to the plurality of drains in a one - to - one correspondence; Providing a pre - charge instruction to the memory, pre - charging at least one of the sub - word line drivers, and all of the sub - word lines being in an off state; At least one of the sub - word line drivers undergoes at least one pre - charge, and the actual duration experienced by each pre - charge is obtained in real time, and the standby current of the memory in each step of the pre - charge is obtained in real time, the standby current being the static current when all memory cells in the memory are in an idle state during the pre - charge step; The dielectric layer in the sub - word line driver that undergoes the pre - charge is a target dielectric layer, and a reliability evaluation of the target dielectric layer is realized based on the actual duration. The reliability evaluation includes the following steps: judging in real time the magnitude relationship between the actual duration and the maximum duration allowed for the pre - charge. If the actual duration is greater than the maximum duration, it is determined that the target dielectric layer fails; if the actual duration is less than or equal to the maximum duration, judging in real time the magnitude relationship between the standby current and the maximum standby current allowed for the memory during the pre - charge. If the standby current is greater than the maximum standby current, it is determined that the target dielectric layer fails.

2. The evaluation method according to claim 1, wherein The memory further includes a first terminal for applying a working voltage and a second terminal for grounding. The step of obtaining the standby current in each step of the pre - charge includes: during the pre - charge step, obtaining in real time the current flowing from the first terminal through the second terminal.

3. The evaluation method according to claim 1, characterized in that, Taking the standby current obtained for the first time as the initial standby current, and the ratio of the maximum standby current to the initial standby current is greater than or equal to 2.

4. The evaluation method according to claim 1, characterized in that, During the step of pre - charging at least one of the sub - word line drivers, the gate is at a first potential, and the plurality of drains are all at a second potential, and the second potential is lower than the first potential, and both the first potential and the second potential are constant values.

5. The evaluation method according to claim 4, characterized in that Further including, performing multiple evaluations on the reliability of the dielectric layer, and in different evaluation steps, the magnitude of the first potential is different.

6. The evaluation method according to claim 1, characterized in that During the step of pre - charging at least one of the sub - word line drivers, the gate is at a first potential, and the plurality of drains are all at a second potential, and the second potential is lower than the first potential. While the second potential is a constant value, in any pre - charge step, the magnitude of the first potential gradually increases with the progress time of the pre - charge.

7. The evaluation method according to claim 6, characterized in that Further including, performing multiple evaluations on the reliability of the dielectric layer, and in different evaluation steps, the amplitude of the gradual increase of the magnitude of the first potential with the progress time of the pre - charge is different.

8. The evaluation method according to claim 1, characterized in that, Each of the sub - word line drivers includes at least 4 of the transistors arranged in an array, and the shared gate of the plurality of transistors is a ring structure.

9. The evaluation method according to claim 1, characterized in that In the step of providing the precharge instruction to the memory, precharge all the sub - word line drivers in the memory; All the sub - word line drivers simultaneously undergo at least one precharge, and the actual duration experienced by each precharge is obtained in real - time; Based on the actual duration, the reliability assessment of the target dielectric layer is realized.

10. The evaluation method according to claim 1 or 9, wherein the memory includes a plurality of main word lines, and the plurality of main word lines are electrically connected to the gates of the plurality of sub - word line drivers in a one - to - one correspondence; in the step of providing the precharge instruction to the memory, at least one main word line controls at least one gate to be at a first potential.

11. A test system for evaluating the reliability of a dielectric layer, characterized in that, Comprising: A memory, the memory includes a plurality of sub - word line drivers and a plurality of sub - word lines. Each sub - word line driver includes a plurality of transistors. Each transistor includes a gate, a source, a drain, and a dielectric layer. The plurality of transistors share the gate and the source, and the plurality of sub - word lines are electrically connected to the plurality of drains in a one - to - one correspondence; A precharge module, configured to: provide a precharge instruction to the memory, precharge at least one sub - word line driver, and all the sub - word lines are in an off state; An acquisition module, during the cyclic operation of the memory, the sub - word line driver undergoes at least one precharge. The acquisition module is configured to: obtain in real - time the actual duration experienced by each precharge and, in the precharge step, obtain the standby current of the memory. The standby current is the static current when all the memory cells in the memory are in an idle state during the precharge step; A judgment module, the dielectric layer in the sub - word line driver undergoing the precharge is the target dielectric layer. The judgment module is configured to: realize the reliability assessment of the target dielectric layer based on the actual duration. The judgment module includes: a parameter setting module, configured to: provide the maximum duration allowed for undergoing the precharge; A comparison module, configured to: continuously judge the magnitude relationship between the actual duration and the maximum duration. If the actual duration is greater than the maximum duration, it is determined that the target dielectric layer fails.

12. The test system according to claim 11, wherein, The parameter setting module is further configured to: provide the maximum standby current allowed for the memory during the precharge; the comparison module is further configured to: continuously judge the magnitude relationship between the standby current and the maximum standby current. If the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, it is determined that the target dielectric layer fails.

13. The test system according to claim 11, characterized in that, In the step of precharging at least one sub - word line driver, the gate is at a first potential, and the plurality of drains are all at a second potential, and the second potential is lower than the first potential. The precharge module is further configured to: control both the first potential and the second potential to be constant values.

14. The test system according to claim 11, wherein In the step of pre-charging at least one of the sub-word line drivers, the gate is at a first potential, a plurality of the drains are all at a second potential, and the second potential is lower than the first potential. The pre-charge module is further configured to: while controlling the second potential to be a constant value, in any one of the pre-charging steps, control the magnitude of the first potential to gradually increase with the progress time of the pre-charging.

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