Electronic device and memory data repair method thereof

Abstract

The present application provides a memory data repair method applied to an electronic device to repair data of a flash memory. The electronic device includes a control circuit and a flash memory including a memory array having a plurality of storage blocks. The memory data repair method includes: performing, by the control circuit, a data reading procedure on storage data of the storage blocks; determining, by the control circuit, that one of the storage blocks corresponding to the storage data has a bit inversion error and is an error block according to the data reading procedure; and when a number of the bit inversion errors of the error block is greater than a preset error threshold, performing a memory data repair procedure to control the flash memory to write correction data generated by the data reading procedure on the storage data to the error block.

Description

Technical Field

[0001] This application relates to the field of flash memory repair technology, specifically to an electronic device with a flash memory data repair mechanism and a method for repairing memory data thereon. Background Technology

[0002] In memory, data is stored in digital form. More specifically, data is stored using bits containing 0s and 1s. However, in flash memory, due to the inherent characteristics of the hardware, a bit flip can occur, causing data that was originally 0 to become 1, or vice versa. The data error caused by this phenomenon is called a bit flip error.

[0003] Bit-flip errors are typically corrected through error checking and correcting mechanisms after the data is read. However, as flash memory is used more repeatedly and over time, the number of bit-flip errors often exceeds a default threshold, making data correction impossible. Some technologies back up the main block data in a backup block, allowing data to be read from the backup block if the main block fails. However, this configuration increases hardware costs, and the problem of an excessive number of bit-flip errors persists. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a memory device with a flash data repair mechanism and a memory data repair method thereof, so as to improve the prior art.

[0005] This invention includes an electronic device for repairing data in a flash memory, the flash memory including a memory array having a plurality of storage blocks. The electronic device includes a control circuit. The control circuit is configured to perform a memory data repair method on the flash memory. The memory data repair method includes: executing a data reading procedure on stored data in the storage blocks; determining, according to the data reading procedure, that one of the storage blocks corresponding to the stored data has a bit flip error and is therefore an erroneous block; and when the number of bit flip errors in the erroneous block exceeds a preset error threshold, performing a flash memory data repair procedure to control the flash memory to write correction data generated by the data reading procedure corresponding to the stored data into the erroneous block.

[0006] The present invention further includes a memory data repair method applied in an electronic device to repair data in flash memory. The electronic device includes a control circuit, and the flash memory includes a memory array having a plurality of storage blocks. The memory data repair method includes: the control circuit executing a data reading program on the stored data in the storage blocks; the control circuit determining, based on the data reading program, that one of the storage blocks corresponding to the stored data has a bit inversion error and is therefore an erroneous block; and when the number of bit inversion errors in the erroneous block is greater than a preset error threshold, performing a memory data repair program to control the flash memory to write the correction data generated by the data reading program on the corresponding stored data into the erroneous block.

[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a block diagram of an electronic device with a flash memory data repair mechanism according to an embodiment of this application;

[0010] Figure 2 This is a block diagram of the electronic device in the embodiments of this application;

[0011] Figures 3A to 3B This is a schematic diagram of the flash memory array in an embodiment of this application;

[0012] Figures 4A to 4D This is a schematic diagram of the flash memory array during data transfer in an embodiment of this application;

[0013] Figure 5 This is a flowchart of a memory data repair method according to an embodiment of this application;

[0014] Figure 6 This is a flowchart of the flash memory data repair procedure in the embodiments of this application;

[0015] Figure 7 This is a flowchart of the transfer procedure in the embodiments of this application. Detailed Implementation

[0016] One objective of this invention is to provide an electronic device with a flash memory data repair mechanism and a memory data repair method thereof. The device determines the existence of error blocks through a data reading program, and then performs a memory data repair program when the number of erroneous data in the error block is greater than a default error threshold, writing the correction data into the error block to achieve the purpose of repairing the storage block.

[0017] Please refer to Figure 1 . Figure 1 This diagram shows a block diagram of an electronic device 100 with a flash memory data repair mechanism according to an embodiment of the present invention. The electronic device 100 includes a flash memory 110, a control circuit 120, and a random access memory 180. In one embodiment, the flash memory 110, the control circuit 120, and the random access memory 180 are respectively disposed in different chips.

[0018] The flash memory 110, control circuit 120, and random access memory 180 can be implemented with different architectures according to actual needs, enabling the control circuit 120 to perform data reading, data writing, and data erasure operations on the flash memory 110. For data reading operations, due to the inherent characteristics of the flash memory 110, bit inversion may occur in the stored digital data, causing data that was originally 0 to become 1, or vice versa, resulting in bit inversion errors in the read data. Therefore, the electronic device 100 of the present invention has a flash memory data repair mechanism to not only correct the read data but also repair the stored data.

[0019] The following will use an example architecture to illustrate the flash memory data recovery mechanism of electronic device 100.

[0020] In this embodiment, the flash memory 110 includes a memory array 130, a repair circuit 140, a cache circuit 150, and a slave circuit 160. The flash memory 110 may be a reverse-access NAND flash memory, however, the present invention is not limited thereto. The control circuit 120 includes a master circuit 170.

[0021] The control circuit 120 controls the execution of a data reading program on the stored data SD stored in the multiple storage blocks of the memory array 130 in the flash memory 110. The data reading program will be described below.

[0022] In one embodiment, the storage data SD may be part of boot program code used to power on a computer system, and the boot program code may be stored in the form of an image file. However, the invention is not limited thereto.

[0023] The master circuit 170 of the control circuit 120 is configured to generate data read commands (not shown). The master circuit 170 may include control logic circuitry and a transmission interface (not shown) to generate data read commands and transmit them to the flash memory 110 via the transmission interface. The slave circuit 160 of the flash memory 110 is configured to receive and process the data read commands. The slave circuit 160 may also include control logic circuitry and a transmission interface (not shown) to receive data read commands via the transmission interface and process them by the control logic circuitry, thereby reading the stored data SD in the storage block according to the data read commands.

[0024] Next, the flash memory 110 performs error checking on the stored data SD according to the verification mechanism, and performs error correction when the stored data SD is faulty to generate correction data CD.

[0025] Repair circuit 140 is configured to perform a default error checking and correction (ECC) algorithm to check for bit flip errors in the stored data SD read from the storage block, and to correct for errors in the stored data SD by generating correction data CD. Cache circuit 150 is configured to receive the correction data CD for temporary storage.

[0026] Finally, the correction data CD is transmitted from the flash memory 110 to the control circuit 120 to complete the data reading process.

[0027] More specifically, slave circuit 160 may retrieve calibration data CD from cache circuit 150 and transmit it to master circuit 170. Master circuit 170 may then store the calibration data CD in random access memory 180. In one embodiment, random access memory 180 is, for example, but not limited to, dynamic random access memory (DRAM).

[0028] After the data reading program ends, the control circuit 120 determines, according to the data reading program, that one of the storage blocks of the corresponding stored data SD has a bit inversion error and is therefore an error block.

[0029] In one embodiment, the control circuit 120 determines that the storage block of the corresponding stored data SD is an error block based on the error check state ES generated by the verification mechanism of the flash memory 110. The error check state ES can be generated by the repair circuit 140 while performing the error check algorithm to indicate the existence of bit inversion errors and the number of data with bit inversion errors, and then transmitted to the master circuit 170 through the slave circuit 160.

[0030] According to the error check status ES, when the number of bit inversion errors in the error block exceeds a preset error threshold, the control circuit 120 performs a memory data repair procedure to control the flash memory 110 to write the correction data CD generated by the data reading procedure corresponding to the stored data SD into the error block. The control circuit 120 can then... Figure 1 The dashed path retrieves the calibration data CD from the random access memory 180 and writes it to the memory array 130 through the master circuit 170, slave circuit 160, and cache circuit 150.

[0031] In one embodiment, during the memory data repair process, the control circuit 120 controls the flash memory 110 to first erase the data in the erroneous block, and then write the correction data CD into the erroneous block. Therefore, the repaired storage block will contain the correct data and will no longer have bit-flip errors.

[0032] The preset error threshold can be set to different values ​​according to actual needs. In the most extreme case, the preset error threshold can be 0, that is, the flash memory data repair procedure will be performed as soon as there is a single erroneous data. However, in practice, due to the limited read and write lifespan of flash memory, the preset error threshold can be set to a value greater than 0. When the number of erroneous data is not greater than this default error threshold, the control circuit 120 will not perform the memory data repair procedure, but will only correct the data by the aforementioned error check.

[0033] Figure 2 This shows a block diagram of an electronic device 200 according to another embodiment of the present invention. Figure 1 The electronic device 100 is similar. Figure 2 The electronic device 200 includes flash memory 210, control circuitry 220, and random access memory 280. However, in this embodiment, flash memory 210 includes memory array 230, cache circuitry 250, and slave circuitry 260. Control circuitry 220 includes master circuitry 270 and repair circuitry 240.

[0034] Compared to Figure 1 Electronic device 100, Figure 2 The electronic device 200 performs error verification on the stored data SD read from a storage block of the flash memory 210 by the repair circuit 240 in the control circuit 220, so as to generate correction data CD and error verification status ES. The rest of the operation of the electronic device 200 is the same as or similar to the operation of the electronic device 100, and will not be described in detail here.

[0035] However, during the memory data repair process, due to environmental factors or factors inherent to the electronic device 100 itself, situations may arise where repair cannot be successfully completed. The following will explain the handling procedures performed by the electronic device 100 under different circumstances.

[0036] Regarding environmental factors, the electronic device 100 may encounter occasional power outages during operation. To ensure that flash memory data recovery is unaffected by power outages, the flash memory data recovery process can be performed through a backup mechanism.

[0037] The backup mechanism in the memory data recovery process will be explained below. It should be noted that the following operations are described in terms of actions performed by flash memory 110; however, in reality, the components inside flash memory 110 can be controlled by the slave circuit 160 in flash memory 110.

[0038] Please refer to Figure 3A and Figure 3B . Figure 3A and Figure 3B This diagram illustrates a memory array 130 according to one embodiment of the present invention. Figure 3A and Figure 3B As shown, memory array 130 contains storage blocks ST1 to ST2. M And backup blocks BA1 to BA3.

[0039] like Figure 3A As shown, the stored data SD corresponds to storage block ST1 and has a bit inversion error; therefore, storage block ST1 is an error block. Before writing the correction data CD to the error block, flash memory 110 first writes the correction data CD to one of the backup blocks BA1 to BA3 in memory array 130, such as, but not limited to, backup block BA1, for backup. After the backup is completed, the flash memory 110 records the error block as a repair block in the block status table TAB stored in memory array 130.

[0040] The block status table (TAB) is configured to record and store blocks ST1 to ST2. M The state. In one embodiment, storage blocks ST1 to ST M The status includes, but is not limited to, good blocks that are still writable and erasable, damaged blocks that are unreadable and writable, and repair blocks that are being repaired. In practice, the block status table (TAB) can be stored in storage blocks ST1 to ST2. M In a good block.

[0041] like Figure 3B As shown, the flash memory 110 writes the correction data CD from the backup block BA1 to the erroneous block that was erased. After the correction data CD is written, the memory 110 records the erroneous block (storage block ST1) as a good block in the block status table TAB.

[0042] During the above process, if the flash memory 110 experiences a power outage before the backup is completed and then power is restored, the calibration data CD is rewritten to the backup block BA1 for backup. Conversely, if the flash memory 110 experiences a power outage after the backup is completed but before the calibration data is written to the error block, the calibration data CD is directly written from the backup block BA1 to the error block.

[0043] Regarding the electronic device 100 itself, due to the limited read / write lifespan of the flash memory 110, storage blocks in the memory array 130 will become damaged and unable to be read or written again when the maximum number of read / write cycles is reached, thus becoming damaged blocks. In such a situation, the electronic device 100 cannot repair the damaged blocks and needs to move the data in the damaged blocks.

[0044] The following will explain the data transfer mechanism. It should be noted that the following operations are described in terms of actions performed by flash memory 110; however, in reality, the components inside flash memory 110 can be controlled by the slave circuitry 160 within flash memory 110.

[0045] Please refer to Figures 4A to 4D . Figures 4A to 4D These are schematic diagrams illustrating the data transfer process of the memory array 130 in one embodiment of the present invention. Figure 3A as well as Figure 3B Same as shown. Figures 4A to 4D The memory array 130 contains storage blocks ST1 to ST2. M And backup blocks BA1 to BA3.

[0046] Storage blocks ST1 to ST M Blocks containing data are represented as dotted blocks, while those without data are represented as blank blocks. Backup blocks BA1 to BA3 contain backups that have not yet been written back to storage blocks ST1 to ST2. M Data is represented by diagonal blocks, which contain backups and have been written back to storage blocks ST1 to ST2. M Data holders and those without stored data are represented by blank blocks.

[0047] like Figure 4A As shown, storage blocks ST1 to ST4 contain data SD1 to SD4, and storage blocks after storage block ST5 do not contain data.

[0048] In this embodiment, storage block ST1 is an error block with a bit flip error. Flash memory 110 writes the correction data CD1 corresponding to the error block into one of backup blocks BA1 to BA3 for backup. In this embodiment, the correction data CD1 is written into backup block BA1 for backup.

[0049] Flash memory 110 notes that the Mth storage block is a block to be repaired, and the block to be repaired is initially an erroneous block (storage block ST1, so M is 1).

[0050] If the number of failures to write correction data CD1 to the block to be repaired by flash memory 110 exceeds a preset threshold, for example, but not limited to, 3 times, the Mth storage block is recorded as a damaged block in the block status table TAB. Figure 4A In the diagram, the block status table TAB is not shown; it is only marked "damaged" in storage block ST1.

[0051] Flash memory 110 will perform a relocation procedure. First, flash memory 110 increments M by 1 (M is 2 at this time) to mark the Mth storage block as the block to be repaired. Therefore, storage block ST2 is marked as the block to be repaired. In one embodiment, storage block ST2 is adjacent to storage block ST1.

[0052] Flash memory 110 determines whether the block to be repaired contains existing data. If the block to be repaired (storage block ST2) contains existing data SD2, flash memory 110 writes the existing data SD2 into one of its backup blocks BA1 to BA3 for backup. In one embodiment, backup blocks BA1 to BA3 are ring buffers to sequentially write data. Therefore, existing data SD2 is written into backup block BA2 for backup.

[0053] like Figure 4B As shown, the flash memory 110 writes the correction data CD1 to the block to be repaired (storage block ST2). The flash memory 110 further annotates the existing data SD2 as the correction data CD2 to re-execute the transfer procedure.

[0054] Flash memory 110 increments M by 1 (M is 3 at this time) to mark the Mth storage block as a block to be repaired. Therefore, storage block ST3 is marked as a block to be repaired. In one embodiment, storage block ST3 is adjacent to storage block ST2.

[0055] Flash memory 110 determines whether the block to be repaired contains existing data. If the block to be repaired (storage block ST3) contains existing data SD3, flash memory 110 writes the existing data SD3 into the backup block BA3 of flash memory 110 for backup.

[0056] like Figure 4C As shown, the flash memory 110 writes the correction data CD2 (existing data SD2) to the block to be repaired (storage block ST3). The flash memory 110 further marks the existing data SD3 as correction data CD3 to re-execute the transfer procedure.

[0057] Flash memory 110 increments M by 1 (M is now 4) to mark the Mth storage block as a block to be repaired. Therefore, storage block ST4 is marked as a block to be repaired.

[0058] Flash memory 110 determines whether the block to be repaired contains existing data. If the block to be repaired (storage block ST4) contains existing data SD4, flash memory 110 writes the existing data SD4 to the backup block BA4 of flash memory 110 for backup.

[0059] like Figure 4D As shown, the flash memory 110 writes the correction data CD3 (existing data SD3) to the block to be repaired (storage block ST4). The flash memory 110 further marks the existing data SD4 as the correction data CD4 to re-execute the transfer procedure.

[0060] Flash memory 110 increments M by 1 (M is now 5) to mark the Mth storage block as a block to be repaired. Therefore, storage block ST5 is marked as a block to be repaired.

[0061] Flash memory 110 determines whether the block to be repaired contains existing data. If the block to be repaired (storage block ST5) does not contain existing data, flash memory 110 writes the correction data CD4 (existing data SD4) into the block to be repaired. At this point, flash memory 110 has completed the transfer process.

[0062] Using the above mechanism, when data stored in flash memory 110 (such as boot program code stored as image files) becomes unrecoverable due to damage to corresponding storage blocks, it can be repaired through data migration until all data is completely migrated to healthy storage blocks. Furthermore, this method avoids the need for a direct backup of the entire data set, saving on the number of backup blocks by migrating data block by block. Figures 4A to 4D In one embodiment, data that originally occupied four storage blocks can be moved with only three backup blocks.

[0063] Please refer to Figure 5 . Figure 5 This diagram shows a flowchart of a memory data repair method 500 according to an embodiment of the present invention.

[0064] In addition to the aforementioned apparatus, the present invention also discloses a memory data repair method 500, applicable to, for example, but not limited to, [other applications]. Figure 1 In the electronic device 100, an embodiment of the memory data repair method 500 is as follows: Figure 5 As shown, it includes the following steps.

[0065] In step S510: The control circuit 120 executes a data reading program on the stored data SD stored in the multiple storage blocks contained in the memory array 130 in the flash memory 110.

[0066] In step S520: The control circuit 120 determines, according to the data reading program, that one of the storage blocks of the corresponding stored data SD has a bit inversion error and is therefore an error block.

[0067] In step S530: When the number of bit inversion errors exceeds a preset error threshold, the control circuit 120 performs a memory data repair program to control the flash memory to write the correction data CD generated by the data reading program corresponding to the stored data SD into the error block.

[0068] Please refer to Figure 6 . Figure 6 This diagram shows a flowchart of a flash memory data recovery program 600 according to one embodiment of the present invention. One embodiment of the flash memory data recovery program 600 is shown below. Figure 6 As shown, it includes the following steps.

[0069] In step S610: The control circuit 120 erases the data in the erroneous block.

[0070] In step S620: The control circuit 120 writes the correction data into the backup block for backup.

[0071] In step S630: The control circuit 120 marks the Mth storage block as the block to be repaired, and the block to be repaired is initially an error block.

[0072] In step S640: The control circuit 120 writes the correction data into the block to be repaired.

[0073] In step S650: the control circuit 120 determines whether the write operation has failed.

[0074] In step S660: When a write operation fails, the control circuit 120 determines whether the number of failures exceeds a preset threshold. If the number of failures does not exceed the default threshold, the process returns to step S640 to write again.

[0075] In step S670: If the number of failures exceeds a preset threshold, the control circuit 120 initiates a transfer procedure.

[0076] In step S680: When the control circuit 120 determines that the writing is successful in step S650, the process ends.

[0077] Please refer to Figure 7 . Figure 7 This diagram shows a flowchart of a transfer procedure 700 according to one embodiment of the present invention. An example of an embodiment of the transfer procedure 700 is shown below. Figure 7 As shown, it includes the following steps.

[0078] In step S710, the flash memory 110 increments the value of M by 1 to mark the Mth storage block as the block to be repaired.

[0079] In step S720, it is determined whether the block to be repaired contains existing data.

[0080] In step S730, when the block to be repaired contains existing data, the existing data is written to one of the backup blocks for backup.

[0081] In step S740, the correction data is written to the block to be repaired.

[0082] In step S750, the existing data is marked as correction data to re-execute the transfer procedure. Therefore, the process will return to step S710.

[0083] In step S760, when the block to be repaired does not contain any existing data, the correction data is written to the block to be repaired.

[0084] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention. It should be understood that, unless otherwise specified, the order of the steps mentioned in the above embodiments can be adjusted as needed, and they can even be performed simultaneously or partially simultaneously.

[0085] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

Claims

1. An electronic device for repairing data in a flash memory, the flash memory comprising a memory array having a plurality of storage blocks, characterized in that, The electronic device includes: A control circuit configured to perform a memory data repair method on the flash memory, the memory data repair method comprising: A data read procedure is executed on a stored data in the storage block; According to the data reading program, one of the storage blocks corresponding to the stored data is determined to have a bit inversion error and is therefore an error block; as well as When the number of bit-inversion errors in the error block is greater than a preset error threshold, a memory data repair program is executed to control the flash memory to write a correction data generated by the data reading program corresponding to the stored data into the error block. The memory data repair program includes: The correction data is backed up by writing it into one of the multiple backup blocks of the memory array; After the backup is completed, the faulty block is recorded as a block to be repaired in a block status table stored in the memory array. Write the correction data from the backup block to the error block; and After the correction data is written to the erroneous block, the block to be repaired is recorded as a good block in the block status table.

2. The electronic device as claimed in claim 1, characterized in that, The data reading program further includes: The stored data is read from the flash memory; The flash memory performs an error check on the stored data according to a verification mechanism, and performs an error correction when the stored data is incorrect to generate the correction data; as well as The correction data is transmitted from the flash memory to the control circuit; The control circuit determines, based on an error verification state generated by the verification mechanism, that one of the storage blocks corresponding to the stored data is the error block.

3. The electronic device as claimed in claim 1, characterized in that, The data reading program further includes: The stored data is read from the flash memory; The stored data is transferred from the flash memory to the control circuit; and The control circuit performs an error check on the stored data according to a verification mechanism, and performs an error correction when the stored data is incorrect to generate the correction data. The control circuit determines, based on an error verification state generated by the verification mechanism, that one of the storage blocks corresponding to the stored data is the error block.

4. The electronic device as claimed in claim 1, characterized in that, The memory data repair program further includes: If the flash memory experiences a power outage before the backup is completed and then power is restored, the correction data is rewritten into one of the backup blocks of the flash memory. as well as When the power outage occurs after the flash memory has been backed up but before the correction data has been written to the error block, and then the power is restored, the correction data is written from the backup block to the error block.

5. The electronic device as claimed in claim 1, characterized in that, The memory data repair program further includes: When the number of failures to write the correction data into the error block exceeds a preset threshold, the error block is recorded as a damaged block in the block status table, wherein the error block is the Mth storage block in the block status table. as well as A transfer procedure is performed on the flash memory, comprising: Increment the value of M by 1 to mark the Mth storage block as the block to be repaired; Determine whether the block to be repaired contains existing data; When the existing data is stored in the block to be repaired, the existing data is written into one of the backup blocks for backup. Write the correction data into the block to be repaired; The existing data is noted as the correction data, in order to re-execute the transfer procedure; as well as When the block to be repaired does not contain the existing data, the correction data is written into the block to be repaired.

6. The electronic device as claimed in claim 1, characterized in that, The memory data repair program further includes: When the number of failures to write the correction data into the error block exceeds a preset threshold, the correction data is written into a first adjacent block adjacent to the error block, and existing data stored in the first adjacent block is moved to a second adjacent block adjacent to the first adjacent block.

7. A memory data repair method, applied in an electronic device to repair data in a flash memory, the electronic device comprising a control circuit, the flash memory comprising a memory array having a plurality of storage blocks, characterized in that, The memory data repair method includes: The control circuit executes a data reading program on a stored data in the storage block; The control circuit determines, according to the data reading program, that one of the storage blocks corresponding to the stored data has a bit inversion error and is therefore an erroneous block; as well as When the number of bit-inversion errors in the error block is greater than a preset error threshold, a memory data repair program is executed to control the flash memory to write a correction data generated by the data reading program corresponding to the stored data into the error block. The memory data repair program includes: The correction data is backed up by writing it into one of the multiple backup blocks of the memory array; After the backup is completed, the faulty block is recorded as a block to be repaired in a block status table stored in the memory array. Write the correction data from the backup block to the error block; and After the correction data is written to the erroneous block, the block to be repaired is recorded as a good block in the block status table.

8. The memory data repair method as described in claim 7, characterized in that, The data reading program further includes: The stored data is read from the flash memory; The flash memory performs an error check on the stored data according to a verification mechanism, and performs an error correction when the stored data is incorrect to generate the correction data; as well as The correction data is transmitted from the flash memory to the control circuit; The control circuit determines, based on an error verification state generated by the verification mechanism, that one of the storage blocks corresponding to the stored data is the error block.

9. The memory data repair method as described in claim 7, characterized in that, The data reading program further includes: The stored data is read from the flash memory; The stored data is transferred from the flash memory to the control circuit; and The control circuit performs an error check on the stored data according to a verification mechanism, and performs an error correction when the stored data is incorrect to generate the correction data. The control circuit determines, based on an error verification state generated by the verification mechanism, that one of the storage blocks corresponding to the stored data is the error block.

10. The memory data repair method as described in claim 7, characterized in that, The flash data recovery program further includes: When the flash memory experiences a power outage before backup is complete and then power is restored, the control circuit rewrites the correction data into one of the backup blocks of the flash memory. as well as When the flash memory experiences a power outage after backup is complete but before the correction data is written to the error block, and then power is restored, the control circuit writes the correction data from the backup block to the error block.

11. The memory data repair method as described in claim 7, characterized in that, The method further includes: When the number of failures to write the correction data into the error block exceeds a preset threshold, the error block is recorded as a corrupted block in the block status table, wherein the error block is the Mth storage block in the block status table; and A transfer procedure is performed on the flash memory, comprising: Increment the value of M by 1 to mark the (M+1)th storage block as the block to be repaired; Determine whether the block to be repaired contains existing data; When the existing data is stored in the block to be repaired, the existing data is written into one of the backup blocks for backup. Write the correction data into the block to be repaired; The existing data is noted as the correction data, in order to re-execute the transfer procedure; and When the block to be repaired does not contain the existing data, the correction data is written into the block to be repaired.

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