Fpga routing convenience receiver pin aggregation optimization method and system thereof

Abstract

The application relates to the technical field of FPGA, and discloses an FPGA wiring convenience receiver pin aggregation optimization method and system, which can improve RSB conversion interface connection efficiency and save local resources of wiring. The method performs the following operations on at least one device in the FPGA: determining at least one adjacent PLB of a PLB where a device is located as a candidate PLB; selecting one of the candidate PLBs as a target PLB and attempting to move the device into the target PLB; and if the physical constraint of the FPGA can be met after the movement and the pin cluster weighted total amount of the FPGA before the movement is greater than the pin cluster weighted total amount of the FPGA after the movement, the movement is successful.

Description

Technical Field

[0001] This application relates to FPGA technology, and in particular to FPGA routing convenience receiver pin aggregation optimization technology. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this application as set forth in the claims. The description herein is not intended to imply that it is prior art that has been disclosed, simply because it is included in this section.

[0003] An FPGA is a programmable logic device that can be programmed to perform specific functions according to user needs. An FPGA can be viewed as a programmable integrated circuit composed of a large number of logic cells, memory cells, and interconnect structures. By building and programming logic circuits within the FPGA, users can implement various functions such as digital signal processing, image processing, network processing, and computational acceleration. FPGAs offer reconfigurability and high flexibility, and compared to application-specific integrated circuits (ASICs), they have shorter design cycles, lower costs, and faster time-to-market, thus finding widespread application in various fields.

[0004] FPGA application design comprises two phases: front-end logic design and optimization, and back-end placement and routing. In the placement phase, the location of logic devices is optimized based on estimated timing parameters until the desired timing is achieved, after which the routing phase begins. In the routing phase, the logic connections are established using physical traces. Typically, device placement is not adjusted further at this stage to avoid disrupting the optimized timing results.

[0005] However, this approach often encounters a problem: the actual routing cannot be predicted during the placement phase, and performance can only be evaluated using idealized methods. Although placement employs many methods to reduce routing requirements, the actual connections of placed components are still difficult to predict because they may be affected by other connections. In areas with high resource demands, competition is inevitable, and some connections may require many detours to achieve, or may simply fail to be routed successfully.

[0006] Routing resources are generally divided into two categories: connections between RSBs and connections from RSBs to logic device pins. Connections between RSBs are relatively free, and the likelihood of connection is high as long as limits are not exceeded, although detours may be necessary sometimes. Connections from RSBs to device pins, however, are subject to many restrictions. On the one hand, these RSB conversion interface resources are not abundant; on the other hand, a single RSB conversion interface can only reach a limited number of pin locations. Although more locations can be reached through multiple conversions, these conversions consume additional conversion interface resources. If the number of pins to be connected is large and the matching is poor, routing failures will occur. Layout typically focuses on reducing bus length and optimizing timing, making it difficult to consider the placement of local components, thus also leading to poor matching between conversion interfaces and device pins. Summary of the Invention

[0007] The purpose of this application is to provide a method and system for optimizing receiver pin aggregation in FPGA wiring, which can improve the connection efficiency of RSB conversion interface and save local wiring resources.

[0008] This application discloses an FPGA routing convenience receiver pin aggregation optimization method, including: Perform the following operations on at least one device in the FPGA: Identify at least one neighboring PLB of a device as a candidate PLB; Select one of the candidate PLBs as the target PLB and attempt to move the device into the target PLB; If the physical constraints of the FPGA can be satisfied after the move, and the weighted total number of pin clusters of the FPGA before the move is greater than the weighted total number of pin clusters of the FPGA after the move, then the move is successful.

[0009] In a preferred embodiment, determining at least one neighboring PLB of a device as a candidate PLB further includes: Based on the net of the PLB, scores are calculated for the PLB where the device is located and each of its neighboring PLBs. If other devices in the PLB where the device is located have the same net as the device, each identical net is scored 1 point. If neighboring PLBs have the same net as the device, each identical net is scored 1 point. Each neighboring PLB with a score higher than that of the device is selected as a candidate PLB.

[0010] In a preferred embodiment, one of the candidate PLBs is selected as the target PLB in descending order of the scores, and the device is moved into the target PLB. If the move is successful, there is no need to continue trying to move the device into other candidate PLBs.

[0011] In a preferred embodiment, the weighted total of the pin cluster is calculated as follows: Sum the weights of all pin clusters, where the weight of a single pin cluster = (sum-1) / N+1; Where N is the maximum number of receiver pins that a single RSB conversion interface can drive, sum is the total number of receiver pins belonging to the same net within a PLB, and / represents rounding down.

[0012] In a preferred embodiment, the physical constraints include one or any combination of the following: The target PLB contains devices of the same type as the device, the target PLB has sufficient spare capacity to accommodate the device, and the clock signal of the device is consistent with the clock signal in the target PLB.

[0013] In a preferred embodiment, the at least one neighboring PLB includes PLBs whose Manhattan distance from the PLB containing the device is less than or equal to a predetermined threshold.

[0014] In a preferred embodiment, the predetermined threshold is 2.

[0015] In a preferred embodiment, the device includes one or any combination of the following: a lookup table, a register, and a random access memory.

[0016] This application also discloses an FPGA routing convenience receiver pin aggregation optimization system, including: Memory, used to store computer-executable instructions; and, A processor, coupled to the memory, is configured to implement the steps of the method as described above when executing the computer-executable instructions.

[0017] This application also discloses a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the method described above.

[0018] The embodiments of this application can improve the connection efficiency of RSB conversion interfaces and reduce the number of pin clusters, thereby helping to save local wiring resources and improve wiring success rate. It solves the problem of limiting the number of receiver pins in the prior art to reduce the demand for local resources by receiver pins, and also avoids the difficulties in timing convergence and global routing caused by the dispersed placement of devices.

[0019] Employing a net-based scoring mechanism to evaluate candidate PLBs as destinations prioritizes the optimal destination, and even if a move fails, it easily switches to a suboptimal one, accelerating the optimization process. This improves cabling efficiency and accuracy while reducing cabling costs.

[0020] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded. Attached Figure Description

[0021] Figure 1 This is a schematic flowchart of an FPGA routing convenience receiver pin aggregation optimization method according to an embodiment of this application; Figure 2 This is a diagram illustrating the significant amount of RSB conversion interfaces used in an example where aggregation optimization was not performed. Figure 2 'a' is a schematic diagram of the logical connections before optimization. Figure 2 b is a schematic diagram of the physical connections before optimization; Figure 3 This is a schematic diagram illustrating the RSB conversion interface usage after aggregation optimization in an example. Figure 3 a is a schematic diagram of the optimized logical connection. Figure 3 b is a schematic diagram of the optimized physical connections; Figure 4 This is a receiver pin aggregation optimization method according to an embodiment of the present application; Figure 5 This is a schematic diagram of the range in which the device attempts to move in one embodiment of this application; Figure 6 This is an example of pin cluster optimization in one embodiment of this application. Detailed Implementation

[0022] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0023] Explanation of some concepts: Devices: In FPGAs, they are also called Cells, which are modules that implement logic functions, such as LUTs (Look-Up Tables), Registers, RAM (Random Access Memory), etc.

[0024] FPGA stands for Field Programmable Gate Array, which is a programmable digital logic device.

[0025] PLB stands for Programmable Logic Block, which is used to implement various combinational logic and sequential functions.

[0026] RSB stands for Routing Switch Block, which is used to implement the interconnection network inside the FPGA.

[0027] net: refers to the logical connection between device pins in an FPGA.

[0028] Driver: Refers to the driver pin of a logical connection, usually the output port of a device.

[0029] Load: refers to the load pin of the logical connection, which is usually the input port of the device.

[0030] Pin cluster: In the same PLB, the receiving pins driven by the same net can be connected through an RSB conversion interface. The combination of these pins is called a pin cluster.

[0031] Manhattan distance: the sum of the absolute differences between the horizontal and vertical axes of two coordinate systems.

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0033] The first embodiment of this application relates to an FPGA routing convenience receiver pin aggregation optimization method, the process of which is as follows: Figure 1 As shown, the method includes performing the following operations on at least one device in the FPGA: Step 101: Determine at least one neighboring PLB of a device's PLB as a candidate PLB. The method for determining neighboring PLBs can be varied. For example, it can be PLBs whose Manhattan distance to the device's PLB is less than a predetermined threshold. The predetermined threshold can be 2, or other values ​​such as 1 or 3. Other indicators can also be used to determine the proximity relationship of PLBs, such as whether they share common edges or vertices.

[0034] Step 102: Select one of the candidate PLBs as the target PLB and attempt to move the device into the target PLB.

[0035] Step 103: Determine whether the physical constraints of the FPGA can be met after the move and whether the weighted total number of pin clusters of the FPGA before the move is greater than the weighted total number of pin clusters of the FPGA after the move. If so, proceed to step 104. The move is successful and there is no need to continue trying to move the device to other candidate PLBs. Otherwise, return to step 102, select the next candidate PLB as the target PLB, and try to move the device to this new target PLB.

[0036] Physical constraints may include, but are not limited to: the type of device accommodated by the target PLB is consistent with the device, the target PLB has sufficient spare capacity to accommodate the device, the clock signal of the device is consistent with the clock signal in the target PLB, and so on.

[0037] There are many types of devices that can be optimized, including but not limited to device lookup tables, registers, random access memory, and so on.

[0038] Optionally, in one embodiment, step 101 further includes: calculating scores for the PLB where the device is located and each of its neighboring PLBs based on the net of the PLB, wherein if other devices in the PLB where the device is located have the same net as the device, each same net is scored 1 point; if neighboring PLBs have the same net as the device, each same net is scored 1 point.

[0039] Each neighboring PLB with a score higher than that of the device is designated as a candidate PLB. Based on the scores from highest to lowest, one of the candidate PLBs is selected sequentially as the target PLB. An attempt is made to move the device into the target PLB. If the move is successful, there is no need to continue trying to move the device to other candidate PLBs. This reduces the number of candidate PLBs and the number of attempts required to move the device.

[0040] Optionally, in one embodiment, instead of considering only neighboring PLBs with scores higher than those of the device's PLB as candidate PLBs, all neighboring PLBs can be considered as candidate PLBs. When determining whether a move is successful, in addition to considering the weighted total number of pin clusters and the physical constraints that must be met, other optimization metrics are also considered. For example, besides the physical constraints that must be met, the degree of reduction in the weighted total number of pin clusters and the degree of optimization of other metrics can be weighted and scored. A score exceeding a predetermined threshold is considered a successful move.

[0041] Optionally, in one embodiment, the weighted total of the pin cluster is calculated as follows: Sum the weights of all pin clusters, where the weight of a single pin cluster is (sum-1) / N+1.

[0042] Where N is the maximum number of receiver pins that a single RSB conversion interface can drive, sum is the total number of receiver pins belonging to the same net within a PLB, and / represents rounding down.

[0043] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0044] In existing technologies, limiting the number of receiver pins is commonly used to reduce the demand for local resources. Within an FPGA chip, the capacity of the internal devices in a PLB and the corresponding receiver pin capacity are fixed. While limiting the number of pins reduces the demand for local routing resources, it also limits the number of internal devices in the PLB, increasing the overall demand on the PLB. For large designs, this can lead to insufficient PLB capacity. Furthermore, a smaller number of internal devices in a single PLB results in more dispersed device placement, posing challenges to timing convergence and global routing.

[0045] To address this issue, embodiments of this application propose a receiver pin aggregation optimization method, which is a local layout optimization method. Essentially, receiver pin aggregation allows a single RSB conversion interface to serve more receiver pins. By improving the efficiency of the RSB conversion interface and reducing the overall demand for it, routing can be facilitated.

[0046] The following example illustrates the necessity of receiver pin aggregation. Assume two devices, I1 and I2, are placed in two adjacent PLBs. Figure 2 As shown in the original logical connection diagram of pin 'a', pins A are driven by different nets, while pins B, C, and D are each driven by the same net. For physical cabling, refer to... Figure 2 The diagram below shows the physical connections before optimization (b). These five nets need to go to their respective RSBs first, and then to the device pins. This approach will occupy a total of 8 RSB conversion interfaces.

[0047] If pins driven by the same net are merged into the same PLB, what is actually moved is the device containing the pin. In this example, I1 can be moved to the PLB containing I2, or vice versa. The optimized logic connection is as follows: Figure 3 As shown in diagram a. During wiring, ports B, C, and D of I1 and I2 can share a single port, requiring only 5 ports in total. The optimized physical connection is as follows: Figure 3 As shown in b. The resources saved in this way can be used to help other places in need.

[0048] To reduce the number of pin clusters, effective pin cluster merging is necessary. This invention utilizes a scoring mechanism to select target devices for movement, accelerating the optimization process. In general, receiver pin aggregation optimization is an effective method that reduces routing resource requirements and improves the performance and reliability of FPGA designs. The pin cluster concept proposed in this invention can simulate the resource requirements of RSB conversion interfaces, thereby reducing the number of pin clusters. Furthermore, this invention also proposes a scoring mechanism to select target devices for movement, thus accelerating the optimization process. By merging pins driven by the same net into the same PLB, the requirement for RSB conversion interfaces can be significantly reduced, thereby improving routing efficiency.

[0049] In practical FPGA design, the complexity of circuit connections makes determining how to move devices difficult. Each device has multiple receiver pins, each driven by a different net, and they are completely independent. Each pin needs to be aggregated with other pins in its net, and the distribution of receiver pins in different nets is also inconsistent. This means that each receiver pin needs to find a suitable partner based on its own situation. Therefore, the aggregation process needs to comprehensively consider the situation of each receiver pin, rather than simply making a decision based on the situation of a single receiver pin. The optimization process is as follows: Figure 4 As shown.

[0050] In step 401, the number of pins in each PLB pin cluster and the number of receive pins in each pin cluster are calculated. The number of receive pins in each pin cluster is used to determine the weight of the pin cluster.

[0051] Then proceed to step 402, where it is determined whether the sequence of devices to be optimized is empty. If it is, the optimization process ends; otherwise, proceed to step 403. The sequence of devices to be optimized contains all the devices currently required.

[0052] In step 403, a device is selected from the sequence of devices to be optimized.

[0053] Next, in step 404, the scores of the PLB containing the device and all its neighboring PLBs are calculated, and the PLBs are sorted from highest to lowest score to form a PLB sequence. In this embodiment, neighboring PLBs are other PLBs whose Manhattan distance from the PLB containing the device is less than or equal to 2. That is, the movement range of the device is limited to other PLBs whose Manhattan distance from the PLB containing the device is less than or equal to 2, in order to reduce the impact of movement on timing. Figure 5 As shown. Figure 5The PLB, which is centered in the middle of the device, attempts to move within the area containing the second darkest color.

[0054] Then proceed to step 405 to determine whether there are no neighboring PLBs in the PLB sequence or whether the PLB containing the device has the highest score. If so, return to step 402 to continue optimizing the next device; otherwise, proceed to step 406.

[0055] In step 406, the neighboring PLB with the highest current score is taken from the PLB sequence.

[0056] Then proceed to step 407, where the device is moved to the neighboring PLB with the highest current score.

[0057] Then proceed to step 408 to determine whether the physical constraints are met after the move and the total weighted amount of the pin cluster is reduced. If so, the device optimization is successful, and return to step 402 to continue optimizing the next device. Otherwise, abandon the move attempt and return to step 405 to continue trying to move the device to the next neighboring PLB in the PLB sequence.

[0058] Within the same PLB, receiver pins driven by the same net can be connected through a single RSB conversion interface. These pin combinations constitute a pin cluster. In other words, each pin cluster corresponds to one RSB conversion interface requirement. For example... Figure 2 In b, I1 / A, I1 / B, I1 / C, I1 / D, I2 / A, I2 / B, I2 / C, and I2 / D each correspond to a pin cluster, while Figure 3 In configuration b, {I1 / B, I2 / B}, {I1 / C, I2 / C}, and {I1 / D, I2 / D} each form a pin cluster, while I1 / A and I2 / A remain separate clusters. There are exceptions: if the number of receiver pins within a PLB exceeds the number of drivers for a single RSB conversion interface, additional RSB conversion interfaces are required. Therefore, based on the conversion interface's driving capability N, the weight of a pin cluster is defined as n = (sum-1) / N+1, where sum is the total number of receiver pins belonging to a particular net within a single PLB. Assuming a single RSB conversion interface can connect 5 receiver pins simultaneously, a pin cluster driving 1-5 receiver pins within a PLB has a weight of 1; driving 6-10 receiver pins results in a weight of 2. The optimization goal is to reduce the overall design's demand for RSB conversion interfaces, which translates to reducing the total weighted number of receiver pin clusters in the entire design.

[0059] Among these candidate PLBs, it is necessary to consider how to select the best target for movement. Although it is possible to try moving to each candidate PLB in turn and finally keep the result that reduces the pin cluster the most, this method takes a lot of time. In order to find the result faster, this embodiment adopts a scoring mechanism. Specifically, for a device to be moved, it is checked whether there is a drive net with the same value in its current PLB and each candidate PLB. If so, each net is scored as 1 point. The PLB with the highest total score will be tried first, while PLBs with a lower score than its current PLB score will be discarded because moving to these PLBs will not reduce the pin cluster. Although the PLB with the highest total score is the best choice, the move to this PLB may not be successful due to insufficient capacity or timing degradation caused by the move. Other options may need to be tried. Therefore, the attempt will not be limited to one time, but will be performed sequentially by sorting the PLBs in descending order of score. Once successful, no further attempts are needed.

[0060] Figure 6 An example illustrates the role of the scoring mechanism. Figure 6 Two nets drive 5 devices with 6 receive pins, resulting in 5 pin clusters. We plan to optimize by moving I1. In PLB(0,1), a device shares n1 with it, scoring 1; in PLB(0,0), a device shares n2 with it, also scoring 1; in PLB(0,-1), two devices share n1 and n2 respectively, scoring 2. Therefore, we can try moving I1 to PLB(0,-1), reducing the pin cluster count to 4.

[0061] After the move, the number of pin clusters needs to be recalculated. If the number of pin clusters decreases, the move is successful; otherwise, the move is invalid, and you can continue to try or return to the original state. Other criteria for judging the success of the move can also be added, such as timing and congestion level.

[0062] In summary, receiver pin aggregation optimization is a local layout optimization that reduces the demand for local routing resources by allowing a single RSB conversion interface to serve more receiver pins. This embodiment uses pin clusters to represent the resource requirements of the RSB conversion interface and reduces the number of pin clusters by moving components, thereby reducing the demand on the RSB conversion interface. This embodiment also proposes a scoring mechanism to select target components for movement, accelerating the optimization process. Furthermore, this embodiment limits the range of movement to minimize its impact on timing. The combined application of these methods can effectively reduce the demand for local resources by receiver pins, thereby optimizing the routing performance of FPGA designs.

[0063] Furthermore, embodiments of this application also provide an FPGA routing convenience receiver pin aggregation optimization system, including a memory for storing computer-executable instructions, and a processor; the processor is used to implement the steps in the above-described method embodiments when executing the computer-executable instructions in the memory. The processor may be a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Microcontroller Unit (MCU), Neural Processing Unit (NPU), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices. The aforementioned memory may be read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or solid-state drive, etc. The steps of the methods disclosed in the embodiments of this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

[0064] Accordingly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the various method embodiments of this application. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media does not include transient media, such as modulated data signals and carrier waves.

[0065] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0066] The numbering used in describing the steps of a method does not inherently limit the order of these steps. For example, a step with a higher number does not necessarily have to be executed after a step with a lower number; it can be executed first and then second, or even in parallel, as long as this execution order is reasonable to someone skilled in the art. Similarly, multiple steps with consecutively numbered sequences (e.g., step 101, step 102, step 103, etc.) do not restrict other steps from being executed between them; for example, there can be other steps between step 101 and step 102.

[0067] This specification includes combinations of various embodiments described herein. Individual references to embodiments are made (e.g., "one embodiment," "some embodiments," or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word "or" is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.

[0068] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

[0069] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A method for optimizing receiver pin aggregation in FPGA routing convenience, characterized in that, include: Perform the following operations on at least one device in the FPGA: At least one neighboring PLB of a device is identified as a candidate PLB; wherein, based on the net of the PLB, a score is calculated for the PLB of the device and each of its neighboring PLBs, wherein if other devices in the PLB of the device have the same net as the device, each identical net is scored as 1 point; if a neighboring PLB has the same net as the device, each identical net is scored as 1 point; and each neighboring PLB with a score higher than that of the PLB of the device is selected as a candidate PLB. Based on the scores from highest to lowest, one of the candidate PLBs is selected as the target PLB, and the device is moved to the target PLB. If the physical constraints of the FPGA can be met after the move and the weighted total number of pin clusters of the FPGA before the move is greater than the weighted total number of pin clusters of the FPGA after the move, then the move is successful. If the move is successful, there is no need to continue trying to move the device to other candidate PLBs. The weighted total of the pin clusters is calculated as follows: sum the weights of all pin clusters, where the weight of a single pin cluster = (sum-1) / N+1; where N is the maximum number of receiving pins that a single RSB conversion interface can drive, sum is the total number of receiving pins belonging to the same net within a PLB, and / represents the rounding down method.

2. The FPGA routing convenience receiver pin aggregation optimization method as described in claim 1, wherein the physical constraints include one or any combination of the following: The target PLB contains devices of the same type as the device, the target PLB has sufficient spare capacity to accommodate the device, and the clock signal of the device is consistent with the clock signal in the target PLB.

3. The FPGA routing convenience receiver pin aggregation optimization method as described in claim 1, characterized in that, The at least one neighboring PLB includes PLBs whose Manhattan distance from the PLB containing the device is less than or equal to a predetermined threshold.

4. The FPGA routing convenience receiver pin aggregation optimization method as described in claim 3, characterized in that, The predetermined threshold is 2.

5. The FPGA routing convenience receiver pin aggregation optimization method as described in claim 1, characterized in that, The device includes one or any combination of the following: a lookup table, a register, and a random access memory.

6. An FPGA routing convenience receiver pin aggregation optimization system, characterized in that, include: Memory is used to store executable instructions for a computer; as well as, A processor, coupled to the memory, is configured to implement the steps of the method as described in any one of claims 1 to 5 when executing the computer-executable instructions.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the steps of the method as described in any one of claims 1 to 5.

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