An inverter chain circuit, module shielding a set pulse signal

Abstract

The application relates to the technical field of integrated circuit design, in particular to an inverter chain circuit shielding SET pulse signals and a module packaged based on the inverter chain circuit shielding SET pulse signals. The inverter chain is constructed based on a three-stage inverter structure, which not only has the basic function of an inverter, but also has the outstanding ability of shielding SET pulse signals through reasonable circuit design, can shield voltage jump in any direction, and ensures that the output node o3 can still output with correct logic state.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, more particularly, to a shielded SET pulse signal inverter chain circuit (referred to as RHIC inverter chain) and a module packaged based on the shielded SET pulse signal inverter chain circuit. BACKGROUND

[0002] An inverter is a basic functional module in digital circuits, commonly used in integrated circuits. Simply put, an inverter is a device that can invert the phase of an input signal by 180 degrees and output an inverted signal. An inverter chain is a hierarchical structure composed of several inverters.

[0003] When the sensitive area of an integrated circuit is bombarded by a single high-energy particle, the circuit will undergo a series of changes, which can be divided into two categories: hard errors and soft errors. Hard errors are caused by device breakdown or burning, resulting in device damage, circuit failure, and irrecoverability. Soft errors are changes in the logic values of the circuit, which are recoverable. Since the energy of space radiation particles is limited, the probability of a device experiencing a soft error is much higher than the probability of a device experiencing a hard error. Among soft errors, the probability of a single event upset (SEU) is much higher than that of other types of errors. When an inverter is affected by an SEU, it is equivalent to generating a SET pulse signal.

[0004] Existing inverter chains include, for example, Figure 1 a common inverter chain, Figure 2 a 2P-1N type source isolation technology inverter chain, Figure 3 a double output inverter chain. Figure 1 The inverter chain of the prior art cannot shield SET pulse signals, resulting in errors in the final output when an SEU occurs. Figure 2 , Figure 3 The inverter chain of the prior art can only shield positive voltage jumps, and the final output will still be incorrect when a negative voltage jump occurs. SUMMARY

[0005] Therefore, it is necessary to provide an inverter chain circuit and module that can shield SET pulse signals to address the problem that existing inverter chains cannot completely shield SET pulse signals.

[0006] The present application employs the following technical solutions:

[0007] In a first aspect, the present application provides an inverter chain circuit that shields SET pulse signals, comprising: an inverter unit one, an inverter unit two, and an inverter unit three.

[0008] Inverter unit one includes five PMOS transistors P1-P5 and five NMOS transistors N1-N5, used to provide internal nodes f1, f2, f3, f4, and o1. Specifically, f2 has pull-up transistors P1 and P2, and pull-down transistors P3, N1, N2, and N3; f4 has pull-up transistors P4, P5, and N4, and pull-down transistor N5; o1 has pull-up transistors P1, P2, and P3, and pull-down transistors N1 and N2. P1-P5 and N1-N5 are all controlled by the input signal in; inverter unit one outputs the input signal in to o1.

[0009] Inverter unit two includes five PMOS transistors P6-P10 and five NMOS transistors N6-N10, used to provide internal nodes f5, f6, f7, f8, and o2. Specifically, the pull-up transistors for f6 are P6 and P7, and the pull-down transistors are P8, N6, N7, and N8; the pull-up transistors for f8 are P9, P10, and N9, and the pull-down transistor is N10; the pull-up transistors for o2 are P6, P7, and P8, and the pull-down transistors are N6 and N7. P6 and P7 are controlled by f4, P8, P9, and P10 are controlled by f2, and N6-N10 are controlled by o1; inverter unit two outputs the signal from o1 to o2.

[0010] Inverter unit three includes five PMOS transistors P11-P15 and five NMOS transistors N11-N15, used to provide internal nodes f9, f10, f11, f12 and output node o3. Specifically, f10 has pull-up transistors P11 and P12, and pull-down transistors P13, N11, N12, and N13; f12 has pull-up transistors P14, P15, and N14, and pull-down transistor N15; o3 has pull-up transistors P11, P12, and P13, and pull-down transistors N11 and N12. P11 and P12 are controlled by f8, P13, P14, and P15 are controlled by f6, and N11-N15 are controlled by o2; inverter unit three outputs the signal from o2 to o3.

[0011] If in is low, o3 outputs a high level when any of the nodes f1 to f9, f11, f12, or o1 to o2 are bombarded, or when none of f1 to f12 or o1 to o3 are bombarded.

[0012] If in is high, o3 will output a low level when any of the nodes f1~f12 or o1~o2 is bombarded, or when none of f1~f12 or o1~o3 is bombarded.

[0013] The implementation of this type of inverter chain circuit that shields the SET pulse signal is based on the method or process of an embodiment of this disclosure.

[0014] Secondly, the present invention discloses an inverter chain module that shields the SET pulse signal, which is packaged using the inverter chain circuit that shields the SET pulse signal as disclosed in the first aspect.

[0015] The implementation of this inverter chain module that shields the SET pulse signal is based on the method or process of an embodiment of this disclosure.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] This invention constructs an inverter chain based on a three-stage inverter unit. It not only has the basic functions of an inverter, but also, through reasonable circuit design, makes the inverter chain have an outstanding ability to shield SET pulse signals. It can shield voltage jumps in any direction and ensure that the output node o3 can still output in the correct logic state. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a structural diagram of a common inverter chain in the background art of this invention;

[0020] Figure 2 This is a structural diagram of the 2P-1N type source isolation technology inverter chain in the background technology of this invention;

[0021] Figure 3 This is a structural diagram of a dual-output inverter chain in the background art of this invention;

[0022] Figure 4 This is a structural diagram of the RHIC inverter chain provided in Embodiment 1 of the present invention;

[0023] Figure 5 for Figure 4 Waveform diagram of the RHIC inverter chain operating without SEU;

[0024] Figure 6 for Figure 4 Internal circuit state diagram of the RHIC inverter chain when in is low;

[0025] Figure 7 for Figure 4 Internal circuit state diagram of the RHIC inverter chain when in is high;

[0026] Figure 8 for Figure 4 The waveform diagram of SEU appearing at f5 when in is low in the RHIC inverter chain;

[0027] Figure 9for Figure 4 The waveform of SEU appearing at f6 when in is low in the RHIC inverter chain;

[0028] Figure 10 for Figure 4 The waveform of SEU appearing at o2 when in is low in the RHIC inverter chain;

[0029] Figure 11 for Figure 4 The waveform of SEU appearing at f7 when in is low in the RHIC inverter chain;

[0030] Figure 12 for Figure 4 The waveform of SEU appearing at f8 when in is low in the RHIC inverter chain;

[0031] Figure 13 for Figure 4 The waveform of SEU appearing at o2 when in is high in the RHIC inverter chain;

[0032] Figure 14 for Figure 4 The waveform diagram of SEU appearing at f6 when in is high in the RHIC inverter chain;

[0033] Figure 15 for Figure 4 The waveform of SEU appearing at f7 when in is high in the RHIC inverter chain;

[0034] Figure 16 for Figure 4 The waveform diagram of SEU appearing at f8 when in is high in the RHIC inverter chain. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] Example 1

[0039] See Figure 4 This is a structural diagram of the RHIC inverter chain provided in Embodiment 1 of the present invention. The RHIC inverter chain includes three inverter units: inverter unit one, inverter unit two, and inverter unit three.

[0040] Figure 4 The first part is inverter unit one, which includes five PMOS transistors P1 to P5 and five NMOS transistors N1 to N5, used to provide internal nodes f1, f2, f3, f4, and o1. P1 to P5 and N1 to N5 are all controlled by the input signal in; inverter unit one outputs the input signal in to o1. Among them, o1 uses three stacked PMOS transistors for source isolation.

[0041] More specifically, the source of P1 is connected to VDD, and its gate is connected to in. The source of P2 is connected to the drain of P1 and has an internal node f1; its gate is connected to the gate of P1. The source of P3 is connected to the drain of P2 and has an internal node f2; its gate is connected to the gate of P2. The source of P4 is connected to VDD, and its gate is connected to in. The source of P5 is connected to VDD, and its gate is connected to in. The source of N1 is grounded to GND, its gate is connected to the gate of P3, its drain is connected to the drain of P3, and it has an internal node o1. The source of N1 is grounded to GND, its gate is connected to the gate of P3, and its drain is connected to the drain of P3. The source of N2 is grounded to GND, its gate is connected to in, and its drain is connected to the drain of P3. The source of N3 is grounded to GND, its gate is connected to in, and its drain is connected to the drain of P2. The gate of N4 is connected to the gate of P4, and its drain is connected to the drain of P4. The source of N5 is grounded to GND, the gate is connected to the gate of N4, the drain is connected to the drain of N4 and the drain of P5, and an internal node f4 is provided.

[0042] In other words, the pull-up transistors for f2 are P1 and P2, and the pull-down transistors are P3, N1, N2, and N3. The gates of all six transistors are controlled by in. The pull-up transistors for f4 are P4, P5, and N4, and the pull-down transistor is N5. The gates of all four transistors are controlled by in. The pull-up transistors for o1 are P1, P2, and P3 (i.e., o1 is source-isolated by the stacked P1, P2, and P3), and the pull-down transistors are N1 and N2. The gates of all five transistors are controlled by in.

[0043] Figure 4 The second part is inverter unit two, which includes five PMOS transistors P6-P10 and five NMOS transistors N6-N10, used to provide internal nodes f5, f6, f7, f8, and o2. P6 and P7 are controlled by f4, P8, P9, and P10 are controlled by f2, and N6-N10 are controlled by o1; inverter unit two outputs the signal from o1 to o2. Among them, o2 uses three stacked PMOS transistors for source isolation.

[0044] More specifically, the source of P6 is connected to VDD, and its gate is connected to f4. The source of P7 is connected to the drain of P6 and has an internal node f5; its gate is connected to the gate of P6. The source of P8 is connected to the drain of P7 and has an internal node f6; its gate is connected to f2. The source of P9 is connected to VDD, and its gate is connected to f2. The source of P10 is connected to VDD, and its gate is connected to f2. The source of N6 is grounded to GND, its gate is connected to o1, its drain is connected to the drain of P8, and it has an internal node o2. The source of N7 is grounded to GND, its gate is connected to o1, and its drain is connected to the drain of P8. The source of N8 is grounded to GND, its gate is connected to o1, and its drain is connected to the drain of P7. The gate of N9 is connected to o1, and its drain is connected to the drain of P9. The source of N10 is grounded to GND, its gate is connected to o1, its drain is connected to the drains of N9 and P10, and it has an internal node f8.

[0045] In other words, the pull-up transistors for f6 are P6 and P7, and the pull-down transistors are P8, N6, N7, and N8. The gates of P6 and P7 are controlled by f4, the gate of P8 is controlled by f2, and the gates of N6, N7, and N8 are controlled by o1.

[0046] The pull-up transistors of f8 are P9, P10, and N9, and the pull-down transistor is N10. The gates of P9 and P10 are controlled by f2, and the gates of N9 and N10 are controlled by o1.

[0047] The pull-up transistors for o2 are P6, P7, and P8 (o2 is source isolated by the stacked P6, P7, and P8), and the pull-down transistors are N6 and N7. The gates of P6 and P7 are controlled by f4, the gate of P8 is controlled by f2, and the gates of N6 and N7 are controlled by o1.

[0048] Figure 4 The third part is inverter unit three, which includes five PMOS transistors P11-P15 and five NMOS transistors N11-N15, used to provide internal nodes f9, f10, f11, and f12 and output node o3. P11 and P12 are controlled by f8, P13, P14, and P15 are controlled by f6, and N11-N15 are controlled by o2. Inverter unit three outputs the signal from o2 to o3. Among them, o3 uses three stacked PMOS transistors for source isolation.

[0049] More specifically, the source of P11 is connected to VDD, and its gate is connected to f8. The source of P12 is connected to the drain of P11 and has an internal node f9; its gate is connected to the gate of P11. The source of P13 is connected to the drain of P12 and has an internal node f10; its gate is connected to f6. The source of P14 is connected to VDD, and its gate is connected to f6. The source of P15 is connected to VDD, and its gate is connected to f6. The source of N11 is grounded to GND, its gate is connected to o2, its drain is connected to the drain of P13, and it has an internal node o3. The source of N12 is grounded to GND, its gate is connected to o2, and its drain is connected to the drain of P13. The source of N13 is grounded to GND, its gate is connected to o2, and its drain is connected to the drain of P12. The gate of N14 is connected to o2, and its drain is connected to the drain of P14. The source of N15 is grounded to GND, the gate is connected to o2, the drain is connected to the drain of N14 and the drain of P15, and an internal node f12 is provided.

[0050] The pull-up transistors of f10 are P11 and P12, and the pull-down transistors are P13, N11, N12, and N13. The gates of P11 and P12 are controlled by f8, the gate of P13 is controlled by f6, and the gates of N11, N12, and N13 are controlled by o2.

[0051] The pull-up transistors of f12 are P14, P15, and N14, and the pull-down transistor is N15. The gates of P14 and P15 are controlled by f6, and the gates of N14 and N15 are controlled by o2.

[0052] The pull-up transistors for o3 are P11, P12, and P13 (o3 is source isolated by the stacked P11, P12, and P13), and the pull-down transistors are N11 and N12. The gates of P11 and P12 are controlled by f8, the gate of P13 is controlled by f6, and the gates of N11 and N12 are controlled by o2.

[0053] The RHIC inverter chain provided in this embodiment 1 has transistors with the following dimensions: gate length of 140nm and gate width of 65nm.

[0054] The RHIC inverter chain has the basic function of an inverter: if in is high, o3 outputs low when f1~f12 and o1~o3 are not bombarded; if in is low, o3 outputs high when f1~f12 and o1~o3 are not bombarded.

[0055] See Figure 5 The above is a waveform diagram of the RHIC inverter chain operating without SEU. Specifically:

[0056] (1.1) Combination Figure 6 , Figure 6 This is the internal circuit state diagram of the RHIC inverter chain when in is low. Figure 6In this diagram, 0 represents a low level and 1 represents a high level. When in is low, P1-P5 are on, N1-N5 are off, and VDD charges f2 and o1 through P1, P2, and P3, and charges f4 through P5; f2, o1, and f4 are charged to a high level (in addition, VDD charges f1 through P1, and charges f3 through P4, so f1 and f3 are also charged to a high level); N6-N10 are on, and P6-P10 are off, o2 discharges to ground (GND) through N6, f6 discharges to ground (GND) through N8, and f8 discharges to ground (GND) through N10. D discharges, o2, f6, and f8 discharge to low level (in addition, f5 floats, and f7 discharges to ground GND through N9 and N10 to low level); P11 to P15 are turned on, N11 to N15 are turned off, VDD charges f10 and o3 through P11, P12, and P13, and VDD charges f12 through P15, charging f10, o3, and f12 to high level (in addition, VDD charges f9 through P11, and VDD charges f11 through P14, charging f9 and f11 to high level).

[0057] (1.2) Combination Figure 7 , Figure 7 This is the internal circuit state diagram of the RHIC inverter chain when in is high. Figure 7 In this diagram, 0 represents a low level and 1 represents a high level. When in is high, P1-P5 are off, N1-N5 are on, o1 discharges to ground (GND) through N2, f2 discharges to ground (GND) through N3, and f4 discharges to ground (GND) through N5. o1, f2, and f4 discharge to a low level (in addition, f1 floats, and f3 discharges to ground (GND) through N4 and N5). N6-N10 are off, P6-P10 are on, VDD charges f6 and o2 through P6, P7, and P8, and VDD charges f8 through P10. f6 and o2... f8 is charged to a high level (in addition, VDD charges f5 through P6, VDD charges f7 through P9, and f5 and f7 are charged to a high level); P11 to P15 are turned off, N11 to N15 are turned on, o3 discharges to ground GND through N12, f10 discharges to ground GND through N13, f12 discharges to ground GND through N15, and f10, o3, and f12 discharge to a low level (in addition, f9 is floating, and f11 discharges to ground GND through N14 and N15 to a low level).

[0058] The RHIC inverter chain also has SEU protection capability, that is, it shields the SET pulse signal.

[0059] (2.1) When in is low, referring to the above description, in inverter unit one, P1 to P5 are turned on, N1 to N5 are turned off, and f2, o1, f4, f1, and f3 are charged to high level; in inverter unit two, N6 to N10 are turned on, P6 to P10 are turned off, o2, f6, f8, and f7 are discharged to low level, and f5 level remains unchanged; in inverter unit three, P11 to P15 are turned on, N11 to N15 are turned off, and f10, o3, f12, f9, and f11 are charged to high level.

[0060] If any of the nodes f1 to f9, f11, f12, or o1 to o2 are bombarded, the output of o3 will remain unaffected and will still be at a high level.

[0061] Taking inverter unit 2 as an example, the SEU protection is explained and verified through simulation. See the results below. Figures 8-12 .

[0062] See Figure 8 When f5 is bombarded by radiated particles, its potential changes, but f5 is not connected to inverter unit three, so it will not affect o3.

[0063] See Figure 9 When f6 is bombarded by radiated particles, its potential will jump to a high level, causing P13, P14, and P15 to change from being on to being off. However, the pull-down transistors N11 and N12 of o3 are in the off state, so o3 remains at a high level. Since the pull-down transistor N8 of f6 is on, f6 will gradually return to a low level.

[0064] See Figure 10 When O2 is bombarded by radiated particles, its potential will undergo a positive jump. However, since the pull-up transistors of O2 are P6, P7, and P8 connected in series, and each PMOS transistor is separated by STI in the layout (i.e., source isolation technology is used), the amplitude of the positive voltage jump of O2 is reduced, preventing O2 from going high. Therefore, the pull-down transistors N11 and N12 of O3 remain in the off state, thus keeping the O3 node at a high level.

[0065] See Figure 11 When f7 is bombarded by radiated particles, its potential changes from low to high. However, since f7 is not connected to the third-stage inverter, it does not affect node o3. Furthermore, the pull-down transistors N9 and N10 of f7 are conducting, so the voltage of f7 will gradually recover from high to low.

[0066] See Figure 12When f8 is bombarded by radiated particles, its potential changes from low to high. P11 and P12 change from being on to being off, but the pull-down transistors N11 and N12 of o3 are off, so o3 remains at a high level. Meanwhile, the pull-down transistor N10 of f8 is on, so the voltage of f8 will gradually return to a low level.

[0067] Similarly, other nodes located in inverter unit 1 and inverter unit 3 will also be bombarded based on the same principle as above, without affecting the output of o3.

[0068] It should be noted that if f10 is bombarded by radiated particles, its potential changes from high to low. Since P13 is conductive, o3 will be affected by the low potential of f10, resulting in an output error.

[0069] (2.2) When in is high, referring to the above description, in inverter unit one, P1 to P5 are off, N1 to N5 are on, f2, o1, f4, and f3 are discharged to low level, and the level of f1 remains unchanged; in inverter unit two, N6 to N10 are off, P6 to P10 are on, and f6, o2, f8, f5, and f7 are charged to high level; in inverter unit three, P11 to P15 are off, N11 to N15 are on, and f10, o3, f12, and f11 are discharged to low level, and the level of f9 remains unchanged.

[0070] If any of the nodes f1 to f12 or o1 to o2 is bombarded, the output of o3 will remain unaffected and will still be at a low level.

[0071] First, we will take inverter unit 2 as an example to illustrate SEU protection and verify it through simulation. The results are shown below. Figures 13-16 .

[0072] When f5 is bombarded by radiated particles, its potential changes, but since f5 is not connected to inverter unit three, it will not affect o3.

[0073] See Figure 13 When O2 is bombarded by radiated particles, its voltage signal will undergo a negative transition, and the operating states of N11 and N12 will change from on to off. However, since the pull-up transistors P11, P12, and P13 of O3 are in the off state, O3 remains at a low level. And since the pull-up transistors P6, P7, and P8 of O2 are in the on state, O2 will gradually return to a high level.

[0074] See Figure 14When f6 is bombarded by radiated particles, its voltage signal will undergo a negative transition. The operating states of P13, P14, and P15 will change from off to on. However, the pull-up transistors P11 and P12 of o3 are in the off state, so node o3 remains at a low level. Meanwhile, the pull-up transistors P6 and P7 of f6 are in the on state, so node f6 will gradually return to a high level.

[0075] See Figure 15 When f7 is bombarded by radiated particles, its voltage signal will experience a negative transition. However, since f7 is not connected to inverter unit three, it will not affect node o3. Furthermore, the pull-up transistor P9 of f7 is conducting, so the voltage at node f7 will gradually return to a high level.

[0076] See Figure 16 When f8 is bombarded by radiated particles, its voltage signal will undergo a negative transition, and the operating states of P11 and P12 will change from off to on. However, since the pull-up transistor P13 of o3 is in the off state, o3 remains at a low level. And since the pull-up transistor P10 of f8 is in the on state, f8 will gradually return to a high level.

[0077] Similarly, other nodes located in inverter unit 1 and inverter unit 3 will also be bombarded based on the same principle as above, without affecting the output of o3.

[0078] The simulation verifications described above all involved first building a circuit model using TCAD software, and then subjecting the sensitive transistor to particle incident energy LET = 40.00 MeV·cm² / mg. Based on the above explanation of the principle and the simulation results, it can be seen that the RHIC inverter chain can ensure that o3 outputs in the correct logic state when SEU occurs, thereby shielding against erroneous SET pulse signals.

[0079] Example 2

[0080] This embodiment 2 discloses an inverter chain module that shields the SET pulse signal, which is packaged using the inverter chain circuit for shielding the SET pulse signal from embodiment 1. This modular packaging facilitates the promotion and application of the aforementioned inverter chain circuit for shielding the SET pulse signal.

[0081] The inverter chain module that shields the SET pulse signal has four pins: pin 1, pin 2, pin 3, and pin 4.

[0082] The first pin is used to connect the input signal in. Specifically, the first pin is connected to the gates of P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5.

[0083] The second pin is used to connect to the output node o3. Specifically, the second pin is connected to the drain of P13, N11, and N12.

[0084] The third pin is used to connect to VDD. Specifically, the third pin is connected to the source of P1, P4, P5, P6, P9, P10, P11, P14, and P15.

[0085] The fourth pin is used to connect to ground (GND). Specifically, the fourth pin is connected to the source of N1, N2, N3, N5, N6, N7, N8, N10, N11, N12, N13, and N15.

[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An inverter chain circuit that shields the SET pulse signal, characterized in that, include: Inverter unit one includes five PMOS transistors P1~P5 and five NMOS transistors N1~N5, used to provide internal nodes f1, f2, f3, f4, and o1; wherein, the pull-up transistors of f2 are P1 and P2, and the pull-down transistors are P3, N1, N2, and N3; the pull-up transistors of f4 are P4, P5, and N4, and the pull-down transistor is N5; the pull-up transistors of o1 are P1, P2, and P3, and the pull-down transistors are N1 and N2; P1~P5 and N1~N5 are all controlled by the input signal in; inverter unit one outputs the input signal in to o1; The source of P1 is connected to VDD, and its gate is connected to in; the source of P2 is connected to the drain of P1 and has f1 set, and its gate is connected to the gate of P1; the source of P3 is connected to the drain of P2 and has f2 set, and its gate is connected to the gate of P2; the source of P4 is connected to VDD, and its gate is connected to in; the source of P5 is connected to VDD, and its gate is connected to in; the source of N1 is grounded to GND, its gate is connected to the gate of P3, its drain is connected to the drain of P3, and has o1 set; the source of N2 is grounded to GND, its gate is connected to in, and its drain is connected to the drain of P3; the source of N3 is grounded to GND, its gate is connected to in, and its drain is connected to the drain of P2; the gate of N4 is connected to the gate of P4, and its drain is connected to the drain of P4; the source of N5 is grounded to GND, its gate is connected to the gate of N4, its drain is connected to the drain of N4 and the drain of P5, and has f4 set; Inverter unit two includes five PMOS transistors P6~P10 and five NMOS transistors N6~N10, used to provide internal nodes f5, f6, f7, f8, and o2; wherein, the pull-up transistors of f6 are P6 and P7, and the pull-down transistors are P8, N6, N7, and N8; the pull-up transistors of f8 are P9, P10, and N9, and the pull-down transistor is N10; the pull-up transistors of o2 are P6, P7, and P8, and the pull-down transistors are N6 and N7; P6 and P7 are controlled by f4, P8, P9, and P10 are controlled by f2, and N6~N10 are controlled by o1; inverter unit two outputs the signal from o1 to o2; as well as Inverter unit three includes five PMOS transistors P11-P15 and five NMOS transistors N11-N15, used to provide internal nodes f9, f10, f11, f12 and output node o3; wherein, the pull-up transistors of f10 are P11 and P12, and the pull-down transistors are P13, N11, N12, and N13; the pull-up transistors of f12 are P14, P15, and N14, and the pull-down transistor is N15; the pull-up transistors of o3 are P11, P12, and P13, and the pull-down transistors are N11 and N12; P11 and P12 are controlled by f8, P13, P14, and P15 are controlled by f6, and N11-N15 are controlled by o2; inverter unit three outputs the signal of o2 to o3; If in is low, o3 outputs a high level when any of the nodes f1~f9, f11, f12, o1~o2 are bombarded, or when none of f1~f12, o1~o3 are bombarded. If in is high, o3 will output a low level when any of the nodes f1~f12 or o1~o2 is bombarded, or when none of f1~f12 or o1~o3 is bombarded.

2. The inverter chain circuit for shielding the SET pulse signal according to claim 1, characterized in that, The second inverter unit includes: PMOS transistor P6 has its source connected to VDD and its gate connected to f4. PMOS transistor P7 has its source connected to the drain of P6 and has an internal node f5, and its gate connected to the gate of P6. PMOS transistor P8 has its source connected to the drain of P7 and has an internal node f6, and its gate connected to f2. PMOS transistor P9 has its source connected to VDD and its gate connected to f2; PMOS transistor P10 has its source connected to VDD and its gate connected to f2; NMOS transistor N6 has its source grounded to GND, its gate connected to o1, its drain connected to the drain of P8, and an internal node o2. NMOS transistor N7 has its source grounded to GND, its gate connected to o1, and its drain connected to the drain of P8. NMOS transistor N8 has its source grounded to GND, its gate connected to o1, and its drain connected to the drain of P7. NMOS transistor N9 has its gate connected to o1 and its drain connected to the drain of P9; and The NMOS transistor N10 has its source grounded to GND, its gate connected to o1, its drain connected to the drain of N9 and the drain of P10, and has an internal node f8.

3. The inverter chain circuit for shielding the SET pulse signal according to claim 2, characterized in that, The inverter unit three includes: PMOS transistor P11 has its source connected to VDD and its gate connected to f8; PMOS transistor P12 has its source connected to the drain of P11 and has an internal node f9, and its gate connected to the gate of P11. PMOS transistor P13 has its source connected to the drain of P12 and has an internal node f10, and its gate connected to f6. PMOS transistor P14 has its source connected to VDD and its gate connected to f6. PMOS transistor P15 has its source connected to VDD and its gate connected to f6. NMOS transistor N11 has its source grounded to GND, its gate connected to o2, its drain connected to the drain of P13, and an internal node o3. NMOS transistor N12 has its source grounded to GND, its gate connected to o2, and its drain connected to the drain of P13. NMOS transistor N13 has its source grounded to GND, its gate connected to o2, and its drain connected to the drain of P12. NMOS transistor N14, its gate is connected to O2, and its drain is connected to the drain of P14; and The NMOS transistor N15 has its source grounded to GND, its gate connected to o2, its drain connected to the drain of N14 and the drain of P15, and has an internal node f12.

4. The inverter chain circuit for shielding the SET pulse signal according to claim 3, characterized in that, All MOSFETs have a gate length of 140nm and a gate width of 65nm.

5. The inverter chain circuit for shielding the SET pulse signal according to claim 3, characterized in that, When f1~f12 and o1~o3 are not bombarded When in is low, P1~P5 are enabled, N1~N5 are disabled, VDD charges f2 and o1 through P1, P2, and P3, and charges f4 through P5; f2, o1, and f4 are charged to high level; N6~N10 are enabled, P6~P10 are disabled, o2 discharges to ground GND through N6, f6 discharges to ground GND through N8, f8 discharges to ground GND through N10, and o2, f6, and f8 discharge to low level; P11~P15 are enabled, N11~N15 are disabled, VDD charges f10 and o3 through P11, P12, and P13, and charges f12 through P15; f10, o3, and f12 are charged to high level.

6. The inverter chain circuit for shielding the SET pulse signal according to claim 3, characterized in that, When f1~f12 and o1~o3 are not bombarded When in is high, P1~P5 are off, N1~N5 are on, o1 discharges to ground GND through N2, f2 discharges to ground GND through N3, f4 discharges to ground GND through N5, and o1, f2, and f4 discharge to low level; N6~N10 are off, P6~P10 are on, VDD charges f6 and o2 through P6, P7, and P8, and VDD charges f8 through P10, and f6, o2, and f8 charge to high level; P11~P15 are off, N11~N15 are on, o3 discharges to ground GND through N12, f10 discharges to ground GND through N13, f12 discharges to ground GND through N15, and f10, o3, and f12 discharge to low level.

7. The inverter chain circuit for shielding the SET pulse signal according to claim 3, characterized in that, If in is low, o3 is charged to high; when any of the nodes f1~f9, f11, f12, o1~o2 are bombarded, N11 and N12 remain closed, and o3 remains high.

8. The inverter chain circuit for shielding the SET pulse signal according to claim 3, characterized in that, If in is high, o3 discharges to low level; when any node of f1~f12 or o1~o2 is bombarded, at least one of P11~P13 is turned off, and o3 remains at low level.

9. An inverter chain module that shields SET pulse signals, characterized in that, It is packaged using an inverter chain circuit that shields the SET pulse signal as described in any one of claims 1-8.

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