Security key generation system and method based on physical unclonable function
By using SRAM and Hamming distance calculation in the chip, the key generation method solves the problems of key generation vulnerability and power consumption sensitivity, achieves stable and secure key generation, and reduces hardware costs.
Patent Information
- Application Number
- CN202310407019.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-04-12
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2043-04-12
AI Technical Summary
Existing key generation and storage schemes are vulnerable to physical intrusion attacks and are power-sensitive. In addition, existing key generation schemes based on physical unclonable functions have the risk of key leakage.
SRAM is used as the physical unclonable function, combined with the stimulus generator, register group, decoder and extractor. Through multiple rounds of generation and reconstruction stages, the Hamming distance calculation is used to extract the key, which helps data to be stored in external storage to prevent key leakage.
It achieves the generation of stable keys inside the chip, reduces the area of hardware units, prevents key leakage, and is suitable for power-sensitive scenarios.
Smart Images
Figure CN116488801B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of hardware security technology, and in particular relates to a security key generation system and method based on a physical unclonable function. Background Art
[0002] The current mainstream key generation and storage scheme generally uses a true random number generator to generate a multi-bit random number; then extracts a portion of the random number as the chip key; and finally, stores the generated key in non-volatile storage or continuously powered volatile storage. However, these key storage schemes have the following disadvantages:
[0003] (1) Data stored in non-volatile memory is not lost when power is lost, and is vulnerable to physical intrusion attacks, including cross-sectioning, electron microscopy, etc. Although physical intrusion can be prevented by adding a physical protection layer, this approach will undoubtedly increase manufacturing costs and cannot fundamentally solve the problem of physical intrusion attacks.
[0004] (2) If the key is stored in volatile storage, the chip needs to be continuously powered. This solution is not conducive to the application of the chip in some power-sensitive application scenarios. In addition, this solution also faces the risk of key loss due to accidental power failure of the chip.
[0005] To overcome the shortcomings of these key generation and storage schemes, researchers are experimenting with using random variations in chip manufacturing to generate keys. A Physical Unclonable Function (PUF) exploits manufacturing variations to create a unique "fingerprint" for a specific device. Keys generated using PUFs are lost upon power failure and re-established upon power-up, thus overcoming the vulnerability of traditional key generation and storage schemes to physical intrusion.
[0006] Physical unclonable functions (PUFs) can be categorized as strong and weak PUFs. These two types of PUFs correspond to two different application scenarios. Strong PUFs can generate a large number of stimulus-response pairs, which is exponentially proportional to the size of the PUF. Therefore, strong PUFs are often used for security authentication. Weak PUFs generate only a linear number of stimulus-response pairs with the size of the PUF. These functions are often used for key generation. SRAM is the most commonly used weak PUF. The input stimulus of SRAM is the SRAM address, and the output response is the SRAM data output. Due to manufacturing variations in SRAM, there is a certain mismatch in the threshold voltages of its internal memory cell transistors, resulting in some memory cells maintaining the same response value every time power is applied.
[0007] Because the randomness of a physically unclonable key is derived from physical deviations, its output response is susceptible to environmental noise. However, each generated key must remain consistent, requiring an additional error correction unit to ensure key stability. Intermediate information generated during the error correction process may contain key information. Once an attacker obtains this information, the key can be easily deduced. Currently, the most popular key generation architecture is called a fuzzy extractor. This fuzzy extractor divides key generation into two phases: generation and reconstruction. During the generation phase, the response generated by the physically unclonable function and an external random key are input into an error correction encoder. The error correction encoder encodes the response and key to generate helper data. The helper data is stored in a public memory space. During the reconstruction phase, the output response and helper data are input into an error correction decoder. Because the response is susceptible to environmental noise, the resulting response will deviate from the response generated during the generation phase. The error correction decoder uses the helper data to restore the response and extract the input key from it. Because the helper data is stored in a public space and easily accessible to attackers, it cannot contain any key information. However, existing physically unclonable key generation schemes may suffer from key leakage. Summary of the Invention
[0008] The present invention aims to provide a secure key generation system and method based on a physical unclonable function to solve the above technical problems.
[0009] To solve the above technical problems, the specific technical solutions of the security key generation system and method based on physical unclonable function of the present invention are as follows:
[0010] A secure key generation system based on a physically unclonable function comprises a generation module and a reconstruction module. The generation module comprises: an SRAM, an excitation generator, a register group, and a decoder. The SRAM functions as a physically unclonable function and is used to generate a random response. The excitation generator is used to generate an excitation for the SRAM. The register group is used to store the response generated by the SRAM. The decoder is used to decode helper data based on an input key value. The reconstruction module comprises: an SRAM, an excitation generator, a register group, a decoder, and an extractor. The SRAM functions as a physically unclonable function and is used to generate a random response. The excitation generator is used to generate an excitation for the SRAM. The register group is used to store the response generated by the SRAM. The decoder is used to decode a sequence from the response. The extractor is used to compare the sequence with the input helper data to obtain a sequence with the smallest difference and extract the key.
[0011] Furthermore, the four hardware units of SRAM, excitation generator, register group, and decoder are used in both the generation stage and the reconstruction stage, and there is no time intersection between the two processes, so these four parts can be reused to reduce the area of the hardware units.
[0012] The present invention also discloses a security key generation method for a security key generation system, including a generation phase and a reconstruction phase.
[0013] The generation phase is used to generate an address signal from the hardware module generating the stimulus and send it to the SRAM, and the SRAM outputs a corresponding response;
[0014] In the reconstruction phase, the stimulus generator generates the same stimulus as that in the generation phase and sends it to the SRAM, and the SRAM outputs a corresponding response.
[0015] Furthermore, the external input key value in the generation phase is used as a pointer to a specific bit in the response, and the bit and the subsequent (h-1) bits are taken out as helper data, and the helper data is stored in an external storage space.
[0016] Furthermore, the helper data input in the reconstruction phase is used to compare with all sequences in the response and find the sequence with the smallest difference. The position of this sequence in the response is the restored key. The sequence is defined as a continuous binary sequence of length h in the response. The difference between the helper data and the sequence can be calculated using the Hamming distance HD:
[0017]
[0018] Where X and Y are two sequences of equal length, and i represents the i-th bit in the sequence. It means first performing bitwise exclusive-or operation on sequences X and Y, and then adding the results bit by bit.
[0019] Furthermore, the size of the SRAM depends on the length of the helper data h and the key length k. The key length k is 128 bits. The 128-bit key is split, and the generation phase and the reconstruction phase are also divided into multiple rounds.
[0020] Furthermore, the helper data is a binary sequence. If an attacker cannot obtain the response that generates this sequence, he or she cannot infer the position of the sequence in the response from the sequence, nor can he or she obtain any key-related information from the helper data. The response only exists in the circuit inside the chip and cannot be directly observed by the attacker.
[0021] Furthermore, the generation stage includes the following specific steps:
[0022] First, SRAM generates a response W according to the external input stimulusi , external input key key i Treated as a pointer to the key in the SRAM response i The length of the help data is h, and the key in the SRAM response i The continuous binary sequence with the length of h is taken out as the help data H of the i-th round. i , all the help data H generated i are stored in external memory.
[0023] Furthermore, the reconstruction phase includes the following specific steps:
[0024] SRAM generates a response W based on the external input stimulus i ', considering the influence of noise, W i ' represents the incentive during reconstruction, W i 'With W i The difference in bits at certain positions helps data H i It is taken out from the external memory and compared with each h-length sequence in the SRAM response to calculate the help data H i The Hamming distance between all sequences in the response is calculated. After completing the calculation of all Hamming distances, n Hamming distance results can be obtained. These n results are input into the comparator in sequence. The comparator will record the serial number of the smallest Hamming distance. This serial number is output as the key after all Hamming distance traversals are completed.
[0025] Furthermore, in the generation phase, an external input start signal and a generation phase signal are input, the excitation generator generates an excitation and sends it to the SRAM, the SRAM generates a corresponding response, the response is stored in the register group, the decoder uses the input key to decode the corresponding help data, and pulls the help data valid signal high. After the r-round generation phase is completed, the end signal is pulled high; in the reconstruction phase, an external input start signal and a reconstruction phase signal are input, the excitation generator generates an excitation and sends it to the SRAM, the SRAM generates a corresponding response, the response is stored in the register group, the extractor generates an index value and sends it to the decoder, the decoder decodes the sequence from the register group according to the index value and sends it to the extractor, the exclusive OR unit and adder in the extractor are used to realize the calculation of the Hamming distance, and after the Hamming distance calculation is completed, it is input into the comparator, the comparator records all the Hamming distances in the reconstruction phase and compares them one by one to find the minimum value. The sequence number corresponding to the minimum Hamming distance is the reconstructed key. When the comparator outputs the key, it pulls the key valid and high at the same time. After the r-round key reconstruction phase is completed, the completion signal is pulled high.
[0026] The present invention's secure key generation system and method based on a physically unclonable function offers the following advantages: The advantage lies in the fact that the helper data is a binary sequence. If an attacker cannot obtain the response that generated this sequence, they cannot infer the sequence's position within the response, and thus cannot obtain any key-related information from the helper data. Furthermore, the response exists only within the chip's internal circuitry and cannot be directly observed by an attacker, making this key generation scheme virtually immune to key leakage. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 Schematic diagram illustrating various parameters of the security key generation system of the present invention;
[0028] Figure 2 It is a schematic diagram of the generation phase of the present invention;
[0029] Figure 3 is a schematic diagram of the reconstruction phase of the present invention;
[0030] Figure 4 This is a hardware architecture diagram of the present invention. DETAILED DESCRIPTION
[0031] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a secure key generation system and method based on a physical unclonable function of the present invention in conjunction with the accompanying drawings.
[0032] This invention utilizes SRAM as a physically unclonable function and adds an error correction module to ensure the stability of the generated key. Similarly, this key generation scheme is divided into two processes: generation and reconstruction. Consider this key generation mode as a hardware unit implemented on the chip. The generation phase is typically performed only once: the key is input and helper data is generated during the first power-on test of the chip. The reconstruction phase, on the other hand, occurs during each chip initialization process after the test is completed. The helper data is retrieved and used to restore the key input during the generation phase.
[0033] The security key generation system based on a physical unclonable function of the present invention comprises a generation module and a reconstruction module.
[0034] The generation module includes an SRAM, a stimulus generator, a register bank, and a decoder. The SRAM, acting as a physically unclonable function, generates random responses. The stimulus generator generates stimuli for the SRAM. The register bank stores the responses generated by the SRAM. The decoder decodes the helper data based on the input key value.
[0035] The reconstruction module includes SRAM, a stimulus generator, a register bank, a decoder, and an extractor. The SRAM, acting as a physically unclonable function, generates random responses. The stimulus generator generates stimuli for the SRAM. The register bank stores the responses generated by the SRAM. The decoder decodes the sequence from the response, and the extractor compares the sequence with the input helper data to obtain the sequence with the smallest difference and extract the key. The four hardware units—the SRAM, stimulus generator, register bank, and decoder—are used in both the generation and reconstruction phases, and the two processes do not overlap in time. Therefore, these four components can be reused to reduce the hardware unit area.
[0036] The security key generation method based on physical unclonable function of the present invention includes a generation phase and a reconstruction phase.
[0037] During the generation phase, the hardware module generating the stimulus generates an address signal and sends it to the SRAM, which then outputs the corresponding response. At this point, the externally input key value is used as a pointer to a specific bit in the response. This bit and the subsequent (h-1) bits are retrieved as help data, which is stored in an external storage space. For example, if the input key value is 3 and the help data length h is 8, the pointer will point to the 3rd bit in the response, and bits 3 to 10 in the response will be retrieved as help data. Consider the hardware implementation of the generation phase described above.
[0038] During the reconstruction phase, the stimulus generator generates the same stimulus as during the generation phase and sends it to the SRAM. The SRAM outputs the corresponding response, which may differ slightly from the response during the generation phase due to environmental noise. The input helper data is compared with all sequences in the response to find the sequence with the smallest difference. The position of this sequence in the response is the recovered key. A sequence is defined as a continuous binary sequence of length h in the response. The difference between the helper data and the sequence can be calculated using the Hamming distance HD:
[0039]
[0040] Where X and Y are two sequences of equal length, and i represents the i-th bit in the sequence. It means first performing bitwise exclusive-or operation on sequences X and Y, and then adding the results bit by bit.
[0041] In the key generation method proposed in this invention, the size of the SRAM depends on the helper data length h and the key length k. Typically, the key length is 128 bits. Generating a 128-bit key directly would require an excessively large SRAM capacity. Therefore, splitting the 128-bit key into multiple rounds is considered. The generation and reconstruction phases are also performed in multiple rounds.
[0042] The advantage of this key generation scheme lies in the fact that the helper data is a binary sequence. If an attacker cannot obtain the response that generated this sequence, they cannot infer the sequence's position within the response, and thus cannot obtain any key-related information from the helper data. Furthermore, the response exists only within the chip's internal circuitry and cannot be directly observed by an attacker, making this key generation scheme virtually immune to key leakage.
[0043] Example:
[0044] Figure 1 Explain the meaning of each parameter in the present invention. i represents the response of the i-th round of generation / reconstruction process. w represents the length of the response. h represents the length of the helper data, that is, the sequence length. r represents the total number of rounds of generation / reconstruction process. P i，t W i Each round of generation / reconstruction is based on an independent response W.
[0045] Figure 2 This is a schematic diagram of the generation phase. First, the SRAM generates a response W according to the external input stimulus. i . External input key key i Treated as a pointer to the key in the SRAM response i The length of the help data is h, so the key in the SRAM response i The continuous binary sequence with the length of h is taken out as the help data H of the i-th round. i All help data generated by H i are stored in external memory.
[0046] Figure 3 The same SRAM generates a response W according to the external input stimulus. i '. Considering the influence of noise, W i ' represents the incentive during reconstruction, W i 'With W i Differences in bits at certain positions. Help data H i It is retrieved from the external memory and compared with each h-length sequence in the SRAM response. i The Hamming distance between the response and all sequences in the response is calculated. After all Hamming distances are calculated, n Hamming distance results are obtained. These n results are sequentially input into the comparator, which records the sequence number of the smallest Hamming distance. This sequence number is output as the key after all Hamming distances are traversed.
[0047] Figure 4This is the hardware architecture diagram for this key generation scheme. During the generation phase, the external inputs are a start signal and a generation phase signal. The excitation generator generates an excitation and sends it to the SRAM, which generates a corresponding response. The response is stored in a register bank. The decoder uses the input key to decode the corresponding helper data and pulls the helper data valid signal high. After all r rounds of generation phases are complete, the end signal is pulled high. During the reconstruction phase, the external inputs are a start signal and a reconstruction phase signal. The excitation generator generates an excitation and sends it to the SRAM, which generates a corresponding response. The response is stored in a register bank. The extractor generates an index value and sends it to the decoder. The decoder decodes the sequence from the register bank based on the index value and sends it to the extractor. The exclusive-OR unit and adder in the extractor calculate the Hamming distance. After the calculated Hamming distance is calculated, it is input to the comparator. The comparator records all Hamming distances during the reconstruction phase and compares them one by one to find the minimum value. The sequence number corresponding to the minimum Hamming distance is the reconstructed key. When the comparator outputs the key, it pulls the key valid signal high. After the r rounds of key reconstruction phase are complete, the completion signal is pulled high.
[0048] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.
Claims
1. A security key generation method for a security key generation system, characterized in that: Including the generation phase and the reconstruction phase, The generation phase is used to generate an address signal from the hardware module generating the stimulus and send it to the SRAM, and the SRAM outputs a corresponding response; The generation phase includes the following specific steps: First, SRAM generates a response W according to the external input stimulus i , external input key key i Treated as a pointer to the key in the SRAM response i The length of the help data is h, and the key in the SRAM response i The continuous binary sequence with the length of h is taken out as the help data H of the i-th round. i , all the help data H generated i are stored in external storage; In the reconstruction phase, the stimulus generator generates the same stimulus as in the generation phase and sends it to the SRAM. SRAM outputs the corresponding response; The reconstruction phase includes the following specific steps: SRAM generates a response W based on the external input stimulus i ', considering the influence of noise, W i ' represents the incentive during reconstruction, W i 'With W i The difference in bits at certain positions helps data H i It is taken out from the external memory and compared with each h-length sequence in the SRAM response to calculate the help data H i The Hamming distance between all sequences in the response is calculated. After completing the calculation of all Hamming distances, n Hamming distance results can be obtained. These n results are input into the comparator in sequence. The comparator will record the serial number of the smallest Hamming distance. This serial number is output as the key after all Hamming distance traversals are completed.
2. The method for generating a security key according to claim 1, wherein: The external input key value in the generation phase is used as a pointer to point to a specific bit in the response, and the bit and the subsequent (h-1) bits are taken out as helper data, which is stored in an external storage space.
3. The method for generating a security key according to claim 1, wherein: The helper data input in the reconstruction phase is used to compare with all the sequences in the response and find the sequence with the smallest difference. The position of this sequence in the response is the restored key. The sequence is defined as a continuous binary sequence of length h in the response. The difference between the helper data and the sequence can be calculated by the Hamming distance HD: Where X and Y are two sequences of equal length, i represents the i-th bit in the sequence, It means first performing bitwise exclusive-or operation on sequences X and Y, and then adding the results bit by bit.
4. The method for generating a security key according to claim 1, wherein: The size of the SRAM depends on the length of the helper data h and the key length k. The key length k is 128 bits. The 128-bit key is split, and the processes of the generation phase and the reconstruction phase are also divided into multiple rounds.
5. The method for generating a security key according to claim 1, wherein: The helper data is a binary sequence. If an attacker cannot obtain the response that generates this sequence, they cannot infer the position of the sequence in the response from the sequence, and therefore cannot obtain any key-related information from the helper data. The response only exists in the circuit inside the chip and cannot be directly observed by the attacker.
6. The method for generating a security key according to claim 1, wherein: In the generation phase, an external input start signal and a generation phase signal are input, the excitation generator generates an excitation and sends it to the SRAM, the SRAM generates a corresponding response, the response is stored in the register group, the decoder uses the input key to decode the corresponding help data, and pulls the help data valid signal high. After the r-round generation phase is completed, the end signal is pulled high; in the reconstruction phase, an external input start signal and a reconstruction phase signal are input, the excitation generator generates an excitation and sends it to the SRAM, the SRAM generates a corresponding response, the response is stored in the register group, the extractor generates an index value and sends it to the decoder, the decoder decodes the sequence from the register group according to the index value and sends it to the extractor, the exclusive OR unit and adder in the extractor are used to realize the calculation of the Hamming distance, and after the Hamming distance calculation is completed, it is input into the comparator, the comparator records all the Hamming distances in the reconstruction phase and compares them one by one to find the minimum value. The serial number corresponding to the minimum Hamming distance is the reconstructed key. When the comparator outputs the key, it pulls the key valid and high at the same time. After the r-round key reconstruction phase is completed, the completion signal is pulled high.
7. A security key generation system according to any one of claims 1 to 6, characterized in that: The system includes a generation module and a reconstruction module, wherein the generation module includes: An SRAM, an excitation generator, a register group and a decoder, wherein the SRAM is used as a physically unclonable function to generate a random response; the excitation generator is used to generate an excitation for the SRAM; the register group is used to store the response generated by the SRAM; the decoder is used to decode helper data according to an input key value; the reconstruction module includes an SRAM, an excitation generator, a register group, a decoder and an extractor, wherein the SRAM is used as a physically unclonable function to generate a random response; the excitation generator is used to generate an excitation for the SRAM; the register group is used to store the response generated by the SRAM; the decoder is used to decode a sequence from the response, and the extractor is used to compare the sequence with the input helper data to obtain a sequence with the smallest difference and extract the key.
8. The security key generation system according to claim 7, wherein: The four hardware units, namely SRAM, excitation generator, register group and decoder, are used in both the generation stage and the reconstruction stage, and there is no time intersection between the two processes, so these four parts can be reused to reduce the area of the hardware units.