A multi-channel secondary cache-based module design method
By splitting the multi-channel L2 cache into multiple 64-bit channels and designing an arbitration module for each RAM, and adopting a polling mechanism and arbitration result judgment, the congestion problem of multi-channel cache in big data scenarios is solved, improving data transmission efficiency and system performance.
Patent Information
- Application Number
- CN202310318107.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-28
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2043-03-28
AI Technical Summary
Multi-channel secondary caches are prone to internal congestion and data transmission delays in scenarios with large data volumes, and the probability of errors when data enters and leaves the FIFO is high, making them unsuitable for high-performance computing needs.
The 256-bit read/write input channel is split into four 64-bit channels, each corresponding to a RAM. An arbitration module is designed for each RAM, and a polling mechanism is used for arbitration to reduce the number of internal arbitrations. Data is read and written through an N-to-one data selector, and the arbitration result is determined by the strb signal. A reverse pressure signal is configured to prevent data congestion.
It reduces the number of internal arbitrations, avoids congestion, increases data transmission bandwidth, improves system performance and fault tolerance, and is suitable for large data volume scenarios.
Smart Images
Figure CN116501658B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip design technology, specifically relating to a module design method based on a multi-channel L2 cache. Background Technology
[0002] In modern computer architectures, caching is a crucial component for improving computer performance. As processor and memory speeds continue to increase, the time cost of accessing main memory also rises, making caching even more important.
[0003] Cache refers to a high-speed data exchange memory that exchanges data with the CPU before main memory, thus achieving a very fast speed. L1 Cache (Level 1 Cache) is the CPU's first-level cache. The capacity and structure of the built-in L1 cache have a significant impact on CPU performance. However, cache memory is composed of static RAM, which has a complex structure. Given the limited CPU die area, the capacity of the L1 cache cannot be made too large.
[0004] Therefore, most modern computers employ multi-level caches. L2 Cache (Level 2 cache) is the CPU's second-level high-speed cache, available in both internal and external chip versions. Internal L2 caches operate at the same speed as the CPU's clock speed, while external L2 caches operate at half the clock speed. Generally, increasing the number of L2 cache channels can improve data transfer bandwidth and support parallel processing by more processor cores, thereby improving overall system performance. Furthermore, increasing the number of L2 cache channels can improve system fault tolerance and reduce data transfer latency, thus improving the response speed between the processor and the L2 cache.
[0005] However, compared to ordinary secondary caches with fewer channels, multi-channel secondary caches present significantly higher technical challenges. This is because each additional external path leads to an exponential increase in the internal arbitration scenario, which can easily cause internal congestion and greatly increase the time required for data to enter and exit the FIFO, as well as the probability of errors during data entry and exit. This makes it unsuitable for scenarios with large data volumes. Summary of the Invention
[0006] To overcome the aforementioned shortcomings of the prior art, this invention provides a module design method based on a multi-channel secondary cache. By splitting the multi-channel secondary cache, the number of internal arbitrations is reduced, congestion is avoided, and each RAM is equipped with its own arbitration module. By adjusting the polling mechanism of the arbitration module, it is made more suitable for scenarios with large data volumes and multiple channels.
[0007] The technical problem to be solved by this invention is achieved through the following technical solution:
[0008] A module design method based on multi-channel secondary cache includes:
[0009] The design includes multiple read / write input channels and multiple RAM L2 caches. The 256-bit read / write input channel is decomposed into four 64-bit channels to convert the input 256-bit read / write instructions into four 64-bit read / write instructions and store them in the corresponding instruction FIFOs. Each instruction FIFO corresponds to a RAM.
[0010] An arbitration module is designed for each RAM. Based on the address in the read / write instruction, the RAM to be used by each channel is obtained. When at least two channels have the same RAM in the current cycle, arbitration is performed in the arbitration module corresponding to that RAM.
[0011] Based on the arbitration result, an N-to-1 data selector is used to read the data from the RAM corresponding to the read instruction; or to write the data from the write instruction to the corresponding RAM.
[0012] In one embodiment of the present invention, the plurality of read / write input channels include 5 write 256-bit channels, 8 write 64-bit channels, 6 read 256-bit channels, and 16 read 64-bit channels.
[0013] In one embodiment of the present invention, the secondary cache contains 128 RAMs for storing data, all of which are single-port SRAMs.
[0014] In one embodiment of the present invention, the arbitration module uses a polling mechanism for arbitration, and saves the index after the current execution during polling so that the starting index position can be obtained in the next execution.
[0015] In one embodiment of the present invention, the arbitration module arbitrates according to the fixed priority of each channel; wherein the fixed priority of each channel is as follows: write priority is greater than read priority, and 256-bit channel priority is greater than 64-bit channel priority.
[0016] In one embodiment of the present invention, it further includes:
[0017] Design a strb module to compare the arbitration result with the corresponding strb signal after the current RAM arbitration is completed, and return the corresponding rps signal to the channel after determining that the arbitration of the 256 bits of data corresponding to the current channel and the strb signal has been completed.
[0018] In one embodiment of the present invention, the step of reading data from the RAM corresponding to the read instruction using an N-to-one data selector based on the arbitration result includes:
[0019] The data read from the corresponding RAM according to the address in the read instruction is stored in a temporary FIFO, and the entire data is read out after all the valid 64-bit data of the current channel has been read into the corresponding temporary FIFO.
[0020] In one embodiment of the present invention, the step of reading data from the RAM corresponding to the read instruction using an N-to-one data selector based on the arbitration result further includes:
[0021] When the temporary FIFO is full, the corresponding channel is pressured by a reverse pressure signal so that it cannot arbitrate new data temporarily.
[0022] In one embodiment of the present invention, it further includes:
[0023] Configure a debug interface for each read / write input channel so that debug data can be directly written to the corresponding RAM when debug enable is high.
[0024] In one embodiment of the present invention, it further includes:
[0025] For each RAM, a corresponding gating is designed, and the clock is turned on only when read / write is enabled.
[0026] The beneficial effects of this invention are:
[0027] 1. The module design method based on multi-channel secondary cache provided by this invention reduces the number of internal arbitrations by splitting the multi-channel secondary cache, avoiding congestion and improving bandwidth; at the same time, each RAM is equipped with its own arbitration module, and by adjusting the polling mechanism of the arbitration module, it is more suitable for scenarios with large data volume and multiple channels.
[0028] 2. In order to prevent signal loss, the present invention writes the data part into RAM after arbitration is completed, and also uses the strb signal to judge the arbitration result. After all the data in the current part has been arbitrated, the corresponding rps signal is returned, which increases the flexibility of the 256-bit read and write channel.
[0029] 3. The present invention also equips the read channel with a reverse pressure signal to avoid data congestion.
[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0031] Figure 1 This is a flowchart illustrating a module design method based on a multi-channel secondary cache provided in an embodiment of the present invention;
[0032] Figure 2This is a schematic diagram of the input channel of the multi-channel secondary cache module provided in an embodiment of the present invention;
[0033] Figure 3 This is a schematic diagram illustrating the process of reading data from the corresponding RAM according to a read channel instruction provided in an embodiment of the present invention. Detailed Implementation
[0034] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0035] Example 1
[0036] Please see Figure 1 , Figure 1 This is a flowchart illustrating a module design method based on a multi-channel secondary cache provided in an embodiment of the present invention, which includes:
[0037] Step 1: Design a level 2 cache including multiple read / write input channels and multiple RAMs, and decompose the 256-bit read / write input channel into four 64-bit channels to convert the input 256-bit read / write instructions into four 64-bit read / write instructions and store them in the corresponding FIFOs; where each FIFO corresponds to a RAM.
[0038] Specifically, for the input channel section, this embodiment adopts the following design scheme:
[0039] The design includes multiple input channels: 5 write 256-bit channels, 8 write 64-bit channels, 6 read 256-bit channels, and 16 read 64-bit channels. For the read / write 256-bit channels, the input channel section will be decomposed into 4 64-bit channels, while the original 64-bit read / write channels remain unchanged.
[0040] For the RAM used to store data, this embodiment designs 128 RAMs, all of which are single-port SRAMs.
[0041] Furthermore, for the read / write paths, the input data includes a clock signal and a reset signal. For the 256-bit read path, the input instruction data includes the read address, read request, and read strb; for the 256-bit write path, the input instruction data includes the write address, write data, write strb, and write request. For the write channel, based on the stored address, the input channel calculates which RAM the address belongs to, i.e., which RAM the write channel will write the data to. For the read channel, based on the stored address, the corresponding RAM is calculated, i.e., which RAM the read channel will read the data from.
[0042] Specifically, when a 256-bit write instruction enters the multi-channel L2 cache, it is first re-decoded and converted into four 64-bit write instructions, which are then stored in the instruction FIFO. For example... Figure 2 As shown, Figure 2 This is a schematic diagram of the input channel of the multi-channel secondary cache module provided in this embodiment of the invention. The input instructions are split and aligned before being stored in four instruction FIFOs, each corresponding to a RAM. For example, each 256-bit instruction is split into four 64-bit segments, which are then placed in FIFO64, FIFO128, FIFO192, and FIFO256 respectively. If the 64-bit data corresponds to RAM0, RAM4, RAM8, etc., it is placed in FIFO64; if it corresponds to RAM1, RAM5, RAM9, etc., it is placed in FIFO128; if it corresponds to RAM2, RAM6, RAM10, etc., it is placed in FIFO192; and if it corresponds to RAM3, RAM7, RAM11, etc., it is placed in FIFO256. As long as a FIFO is not empty, it is read; however, the address switching for reading only occurs when the ARB arbitrates the current request.
[0043] Understandably, 64-bit write instructions do not need to be split; they only need to be decoded based on the address.
[0044] The splitting of read instructions is similar to that of write instructions, except that the input of read instructions only has address bits and no data bits.
[0045] Step 2: Design a corresponding arbitration module for each RAM. Obtain the RAM that each channel will operate on based on the address in the read / write instruction. If at least two channels have the same RAM in the current cycle, perform arbitration in the arbitration module corresponding to that RAM.
[0046] Since the 128 RAMs in this embodiment are all single-port SRAMs, simultaneous read and write operations are not possible. Therefore, simultaneous arbitration is required for all read and write operations, ensuring that only one read or write access is allowed for each RAM at a time.
[0047] Based on this, this embodiment designs a corresponding arbitration module for each RAM. Specifically, each 64-bit read / write channel enters the arbiter corresponding to the RAM it will be operating on, and decides whether to generate arbitration based on the transmitted data. If multiple input channels correspond to different RAMs in the current cycle, no arbitration mechanism is involved. If at least two input channels correspond to the same RAM in the current cycle, the channels need to be arbitrated before entering the RAM.
[0048] In this embodiment, the arbitration module uses a polling mechanism for arbitration, and saves the index after the current execution during polling so that the starting index position can be obtained in the next execution, thereby achieving the purpose of load balancing.
[0049] Specifically, to improve the efficiency of consecutive accesses to the same RAM, this embodiment optimizes and adjusts the standard round-robin arbitration strategy. When the arbitration result is a certain channel, if the next request is still to access this RAM, then arbitration will not switch. Arbitration will remain on that channel until the instruction FIFO is empty, or the next access is not to this RAM, or 16 consecutive cycles have been occupied. All three conditions will cause arbitration to be restarted.
[0050] Optionally, as an implementation method, the arbitration module arbitrates according to the fixed priority of each channel; specifically, the fixed priority of each channel is as follows: write priority is greater than read priority, and 256-bit channel priority is greater than 64-bit channel priority.
[0051] This embodiment reduces the number of internal arbitrations by splitting the multi-channel secondary cache, thus avoiding congestion and improving bandwidth.
[0052] Furthermore, to prevent signal loss, this embodiment also designs a strb module to compare the arbitration result with the corresponding strb signal after the current RAM arbitration is completed, and to return the corresponding rps signal to the channel after determining that the arbitration of the 256-bit data corresponding to the current channel and the strb signal has been completed.
[0053] In other words, in this embodiment, after arbitration, the data portion is written to RAM, and an indicator signal is left to indicate that arbitration has been completed for that portion. Once the indicator signal matches the strb signal, the corresponding rps signal is returned. For a 256-bit read / write path, the data is initially divided into four 64-bit segments in the input channel to facilitate arbitration and subsequent writing to RAM. After arbitration, the arbitration module feeds back the arbitration result to the strb module. This module collects the results belonging to the same 256-bit read / write channel and compares them with the strb signal of that 256-bit channel. If the number of returned 64 bits matches the strb signal, it indicates that arbitration for the entire 256-bit path has been completed, and the rps signal is returned to that path.
[0054] Specifically, for the strb comparison of the 256-bit signal, when the arbitration reaches the current FIFO, the corresponding bit of the 64-bit signal will be set to 1. The hardware logic first compares the address 0 of the split 256-bit signal with the address 0 of the FIFO strb. If the comparison is successful, it means that the 0th request has been processed. Then, the execution status of address 1 will be compared, and so on. If all four 64-bit signals have been executed, the rsp signal will be returned.
[0055] It is understandable that there is no strb signal for a 64-bit channel, because the strb signal is used to mark valid data, and the smallest unit of valid data is 64 bits. For a 256-bit channel, if strb is 4'b0111, it means that the high 64 bits of the 256-bit data are invalid.
[0056] To prevent signal loss, this invention writes the data portion into RAM after arbitration and uses the strb signal to determine the arbitration result. After all the data in the current portion has been arbitrated, the corresponding rps signal is returned, increasing the flexibility of the 256-bit read / write channel.
[0057] Step 3: Based on the arbitration result, use an N-to-1 data selector to read the data from the RAM corresponding to the read instruction; or write the data from the write instruction into the corresponding RAM.
[0058] Specifically, after arbitration, the arbitration result is passed to an N-to-1 data selector, where N is the number of channels in the multi-channel system. If the selected channel is a write channel, it will transfer the data into RAM; if the selected channel is a read channel, it will read the data from RAM.
[0059] Optional, such as Figure 3 As shown, in this embodiment, after reading the data from the corresponding RAM according to the address in the read instruction, the data is stored in a temporary FIFO, and the entire data is read out after all the valid 64-bit data of the current channel has been read into the corresponding temporary FIFO.
[0060] Understandably, each channel has its own temporary FIFO. For 256-bit data, all valid 64 bits of data must be read into the corresponding temporary FIFO before the entire data is read out. If some data is not read out due to arbitration reasons, the other data will remain in that FIFO, making it easy for the FIFO to fill up.
[0061] To address this, this embodiment also incorporates a reverse pressure signal after the temporary FIFO is full. This reverse pressure signal will apply reverse pressure to the corresponding read channels, preventing them from arbitrating new data and thus avoiding data congestion.
[0062] After arbitration, the write channel data is written to RAM, marking the completion of the write instruction; after arbitration, the read channel data is read from RAM and temporarily stored in a temporary FIFO, marking the completion of the read instruction.
[0063] Understandably, for read accesses that are not 256 address aligned, the data will be reordered, and the order of the data output from the read channel will be consistent with the order of the input data.
[0064] Furthermore, in this embodiment, a debug interface is configured for each read / write input channel. When debug enable is high, all other channels are disabled, and only the debug channel can operate. In debug mode, debug writes / debug reads do not require arbitration, and data can be directly written to the corresponding RAM.
[0065] Specifically, considering that arbitration may be underway when debug mode occurs, processing of polling requests prioritizing debug mode responses will be paused. Therefore, debug read, debug write, and normal read / write requests after arbitration will not occur simultaneously. Based on this, this embodiment uses a MUX to merge the above three types of requests. When debug enable is high, timing signals that ultimately conform to the SPRAM interface can be generated.
[0066] In addition, to reduce power consumption, this embodiment gates the clock for each RAM, and the clock is only turned on when read / write is enabled, and this function can be disabled by software.
[0067] The module design method based on multi-channel secondary cache provided by this invention reduces the number of internal arbitrations by splitting the multi-channel secondary cache, avoiding congestion and improving bandwidth; at the same time, each RAM is equipped with its own arbitration module, and by adjusting the polling mechanism of the arbitration module, it is more suitable for scenarios with large data volume and multiple channels.
[0068] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A module design method based on multi-channel L2 cache, characterized in that, include: The design includes multiple read / write input channels and multiple RAM L2 caches. The 256-bit read / write input channel is decomposed into four 64-bit channels to convert the input 256-bit read / write instructions into four 64-bit read / write instructions and store them in the corresponding instruction FIFOs. Each instruction FIFO corresponds to a RAM. An arbitration module is designed for each RAM. Based on the address in the read / write instruction, the RAM to be used by each channel is obtained. When at least two channels have the same RAM in the current cycle, arbitration is performed in the arbitration module corresponding to that RAM. Based on the arbitration result, an N-to-1 data selector is used to read the data from the RAM corresponding to the read instruction; or to write the data from the write instruction to the corresponding RAM.
2. The module design method based on a multi-channel secondary cache according to claim 1, characterized in that, The multiple read / write input channels include 5 write 256-bit channels, 8 write 64-bit channels, 6 read 256-bit channels, and 16 read 64-bit channels.
3. The module design method based on a multi-channel secondary cache according to claim 1, characterized in that, The secondary cache contains 128 RAMs for storing data, all of which are single-port SRAMs.
4. The module design method based on a multi-channel secondary cache according to claim 1, characterized in that, The arbitration module uses a polling mechanism for arbitration, and saves the index after the current execution during polling so that the starting index position can be obtained in the next execution.
5. The module design method based on a multi-channel secondary cache according to claim 1, characterized in that, The arbitration module arbitrates according to the fixed priority of each channel; the fixed priority of each channel is as follows: write priority is greater than read priority, and 256-bit channel priority is greater than 64-bit channel priority.
6. The module design method based on a multi-channel secondary cache according to claim 1, characterized in that, Also includes: Design a strb module to compare the arbitration result with the corresponding strb signal after the current RAM arbitration is completed, and return the corresponding rps signal to the channel after determining that the arbitration of the 256 bits of data corresponding to the current channel and the strb signal has been completed.
7. The module design method based on a multi-channel secondary cache according to claim 1, characterized in that, The step of reading data from RAM corresponding to a read instruction using an N-to-one data selector based on the arbitration result includes: The data read from the corresponding RAM according to the address in the read instruction is stored in a temporary FIFO, and the entire data is read out after all the valid 64-bit data of the current channel has been read into the corresponding temporary FIFO.
8. The module design method based on a multi-channel secondary cache according to claim 7, characterized in that, The method of reading data from RAM corresponding to a read instruction using an N-to-one data selector based on the arbitration result also includes: When the temporary FIFO is full, the corresponding channel is pressured by a reverse pressure signal so that it cannot arbitrate new data temporarily.
9. The module design method based on a multi-channel secondary cache according to claim 1, characterized in that, Also includes: Configure a debug interface for each read / write input channel so that debug data can be directly written to the corresponding RAM when debug enable is high.
10. A module design method based on a multi-channel secondary cache according to claim 1, characterized in that, Also includes: For each RAM, a corresponding gating is designed, and the clock is turned on only when read / write is enabled.